338 lines
11 KiB
C++
338 lines
11 KiB
C++
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// Implementation of the vmem related function for POSIX-like platforms.
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// There's some minimal amount of platform specific hacks to support
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// Android and OSX since they are slightly different in some areas.
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#include <sys/mman.h>
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#include <sys/types.h>
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#include <sys/stat.h>
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#include <fcntl.h>
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#include <cerrno>
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#include <unistd.h>
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#include "hw/mem/_vmem.h"
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#include "hw/sh4/sh4_if.h"
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#include "stdclass.h"
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#ifndef MAP_NOSYNC
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#define MAP_NOSYNC 0 //missing from linux :/ -- could be the cause of android slowness ?
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#endif
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#ifdef __ANDROID__
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#include <linux/ashmem.h>
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#ifndef ASHMEM_DEVICE
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#define ASHMEM_DEVICE "/dev/ashmem"
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#undef PAGE_MASK
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#define PAGE_MASK (PAGE_SIZE-1)
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#else
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#define PAGE_SIZE 4096
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#define PAGE_MASK (PAGE_SIZE-1)
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#endif
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// Android specific ashmem-device stuff for creating shared memory regions
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int ashmem_create_region(const char *name, size_t size) {
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int fd = open(ASHMEM_DEVICE, O_RDWR);
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if (fd < 0)
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return -1;
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if (ioctl(fd, ASHMEM_SET_SIZE, size) < 0) {
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close(fd);
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return -1;
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}
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return fd;
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}
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#endif // #ifdef __ANDROID__
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bool mem_region_lock(void *start, size_t len)
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{
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size_t inpage = (uintptr_t)start & PAGE_MASK;
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if (mprotect((u8*)start - inpage, len + inpage, PROT_READ))
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die("mprotect failed...");
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return true;
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}
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bool mem_region_unlock(void *start, size_t len)
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{
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size_t inpage = (uintptr_t)start & PAGE_MASK;
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if (mprotect((u8*)start - inpage, len + inpage, PROT_READ | PROT_WRITE))
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// Add some way to see why it failed? gdb> info proc mappings
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die("mprotect failed...");
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return true;
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}
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bool mem_region_set_exec(void *start, size_t len)
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{
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size_t inpage = (uintptr_t)start & PAGE_MASK;
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if (mprotect((u8*)start - inpage, len + inpage, PROT_READ | PROT_WRITE | PROT_EXEC))
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{
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WARN_LOG(VMEM, "mem_region_set_exec: mprotect failed. errno %d", errno);
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return false;
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}
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return true;
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}
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void *mem_region_reserve(void *start, size_t len)
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{
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void *p = mmap(start, len, PROT_NONE, MAP_PRIVATE | MAP_ANON, -1, 0);
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if (p == MAP_FAILED)
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{
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perror("mmap");
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return NULL;
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}
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else
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return p;
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}
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bool mem_region_release(void *start, size_t len)
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{
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return munmap(start, len) == 0;
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}
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void *mem_region_map_file(void *file_handle, void *dest, size_t len, size_t offset, bool readwrite)
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{
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int flags = MAP_SHARED | MAP_NOSYNC | (dest != NULL ? MAP_FIXED : 0);
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void *p = mmap(dest, len, PROT_READ | (readwrite ? PROT_WRITE : 0), flags, (int)(uintptr_t)file_handle, offset);
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if (p == MAP_FAILED)
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{
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perror("mmap");
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return NULL;
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}
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else
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return p;
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}
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bool mem_region_unmap_file(void *start, size_t len)
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{
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return mem_region_release(start, len);
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}
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// Allocates memory via a fd on shmem/ahmem or even a file on disk
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static int allocate_shared_filemem(unsigned size) {
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int fd = -1;
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#if defined(__ANDROID__)
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// Use Android's specific shmem stuff.
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fd = ashmem_create_region(0, size);
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#else
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#if HOST_OS != OS_DARWIN
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fd = shm_open("/dcnzorz_mem", O_CREAT | O_EXCL | O_RDWR, S_IREAD | S_IWRITE);
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shm_unlink("/dcnzorz_mem");
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#endif
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// if shmem does not work (or using OSX) fallback to a regular file on disk
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if (fd < 0) {
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std::string path = get_writable_data_path("/dcnzorz_mem");
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fd = open(path.c_str(), O_CREAT|O_RDWR|O_TRUNC, S_IRWXU|S_IRWXG|S_IRWXO);
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unlink(path.c_str());
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}
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// If we can't open the file, fallback to slow mem.
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if (fd < 0)
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return -1;
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// Finally make the file as big as we need!
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if (ftruncate(fd, size)) {
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// Can't get as much memory as needed, fallback.
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close(fd);
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return -1;
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}
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#endif
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return fd;
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}
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// Implement vmem initialization for RAM, ARAM, VRAM and SH4 context, fpcb etc.
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// The function supports allocating 512MB or 4GB addr spaces.
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int vmem_fd = -1;
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static int shmem_fd2 = -1;
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static void *reserved_base;
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static size_t reserved_size;
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// vmem_base_addr points to an address space of 512MB (or 4GB) that can be used for fast memory ops.
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// In negative offsets of the pointer (up to FPCB size, usually 65/129MB) the context and jump table
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// can be found. If the platform init returns error, the user is responsible for initializing the
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// memory using a fallback (that is, regular mallocs and falling back to slow memory JIT).
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VMemType vmem_platform_init(void **vmem_base_addr, void **sh4rcb_addr) {
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// Firt let's try to allocate the shm-backed memory
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vmem_fd = allocate_shared_filemem(RAM_SIZE_MAX + VRAM_SIZE_MAX + ARAM_SIZE_MAX);
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if (vmem_fd < 0)
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return MemTypeError;
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// Now try to allocate a contiguous piece of memory.
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VMemType rv;
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#ifdef HOST_64BIT_CPU
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reserved_size = 0x100000000L + sizeof(Sh4RCB) + 0x10000; // 4GB + context size + 64K padding
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reserved_base = mem_region_reserve(NULL, reserved_size);
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rv = MemType4GB;
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#endif
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if (reserved_base == NULL)
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{
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reserved_size = 512*1024*1024 + sizeof(Sh4RCB) + ARAM_SIZE_MAX + 0x10000;
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reserved_base = mem_region_reserve(NULL, reserved_size);
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if (!reserved_base) {
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close(vmem_fd);
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return MemTypeError;
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}
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rv = MemType512MB;
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}
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// Align pointer to 64KB too, some Linaro bug (no idea but let's just be safe I guess).
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uintptr_t ptrint = (uintptr_t)reserved_base;
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ptrint = (ptrint + 0x10000 - 1) & (~0xffff);
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*sh4rcb_addr = (void*)ptrint;
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*vmem_base_addr = (void*)(ptrint + sizeof(Sh4RCB));
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const size_t fpcb_size = sizeof(((Sh4RCB *)NULL)->fpcb);
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void *sh4rcb_base_ptr = (void*)(ptrint + fpcb_size);
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// Now map the memory for the SH4 context, do not include FPCB on purpose (paged on demand).
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mem_region_unlock(sh4rcb_base_ptr, sizeof(Sh4RCB) - fpcb_size);
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return rv;
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}
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// Just tries to wipe as much as possible in the relevant area.
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void vmem_platform_destroy() {
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if (reserved_base != NULL)
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mem_region_release(reserved_base, reserved_size);
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}
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// Resets a chunk of memory by deleting its data and setting its protection back.
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void vmem_platform_reset_mem(void *ptr, unsigned size_bytes) {
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// Mark them as non accessible.
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mprotect(ptr, size_bytes, PROT_NONE);
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// Tell the kernel to flush'em all (FIXME: perhaps unmap+mmap 'd be better?)
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madvise(ptr, size_bytes, MADV_DONTNEED);
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#if defined(MADV_REMOVE)
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madvise(ptr, size_bytes, MADV_REMOVE);
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#elif defined(MADV_FREE)
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madvise(ptr, size_bytes, MADV_FREE);
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#endif
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}
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// Allocates a bunch of memory (page aligned and page-sized)
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void vmem_platform_ondemand_page(void *address, unsigned size_bytes) {
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verify(mem_region_unlock(address, size_bytes));
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}
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// Creates mappings to the underlying file including mirroring sections
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void vmem_platform_create_mappings(const vmem_mapping *vmem_maps, unsigned nummaps) {
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for (unsigned i = 0; i < nummaps; i++) {
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// Ignore unmapped stuff, it is already reserved as PROT_NONE
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if (!vmem_maps[i].memsize)
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continue;
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// Calculate the number of mirrors
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u64 address_range_size = vmem_maps[i].end_address - vmem_maps[i].start_address;
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unsigned num_mirrors = (address_range_size) / vmem_maps[i].memsize;
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verify((address_range_size % vmem_maps[i].memsize) == 0 && num_mirrors >= 1);
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for (unsigned j = 0; j < num_mirrors; j++) {
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u64 offset = vmem_maps[i].start_address + j * vmem_maps[i].memsize;
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verify(mem_region_unmap_file(&virt_ram_base[offset], vmem_maps[i].memsize));
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verify(mem_region_map_file((void*)(uintptr_t)vmem_fd, &virt_ram_base[offset],
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vmem_maps[i].memsize, vmem_maps[i].memoffset, vmem_maps[i].allow_writes) != NULL);
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}
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}
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}
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// Prepares the code region for JIT operations, thus marking it as RWX
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bool vmem_platform_prepare_jit_block(void *code_area, unsigned size, void **code_area_rwx) {
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// Try to map is as RWX, this fails apparently on OSX (and perhaps other systems?)
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if (!mem_region_set_exec(code_area, size))
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{
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// Well it failed, use another approach, unmap the memory area and remap it back.
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// Seems it works well on Darwin according to reicast code :P
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munmap(code_area, size);
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void *ret_ptr = mmap(code_area, size, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_FIXED | MAP_PRIVATE | MAP_ANON, 0, 0);
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// Ensure it's the area we requested
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if (ret_ptr != code_area)
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return false; // Couldn't remap it? Perhaps RWX is disabled? This should never happen in any supported Unix platform.
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}
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// Pointer location should be same:
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*code_area_rwx = code_area;
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return true;
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}
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// Use two addr spaces: need to remap something twice, therefore use allocate_shared_filemem()
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bool vmem_platform_prepare_jit_block(void *code_area, unsigned size, void **code_area_rw, uintptr_t *rx_offset) {
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shmem_fd2 = allocate_shared_filemem(size);
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if (shmem_fd2 < 0)
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return false;
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// Need to unmap the section we are about to use (it might be already unmapped but nevertheless...)
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munmap(code_area, size);
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// Map the RX bits on the code_area, for proximity, as usual.
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void *ptr_rx = mmap(code_area, size, PROT_READ | PROT_EXEC,
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MAP_SHARED | MAP_NOSYNC | MAP_FIXED, shmem_fd2, 0);
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if (ptr_rx != code_area)
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return false;
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// Now remap the same memory as RW in some location we don't really care at all.
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void *ptr_rw = mmap(NULL, size, PROT_READ | PROT_WRITE,
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MAP_SHARED | MAP_NOSYNC, shmem_fd2, 0);
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*code_area_rw = ptr_rw;
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*rx_offset = (char*)ptr_rx - (char*)ptr_rw;
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INFO_LOG(DYNAREC, "Info: Using NO_RWX mode, rx ptr: %p, rw ptr: %p, offset: %lu", ptr_rx, ptr_rw, (unsigned long)*rx_offset);
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return (ptr_rw != MAP_FAILED);
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}
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// Some OSes restrict cache flushing, cause why not right? :D
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#if HOST_CPU == CPU_ARM64
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// Code borrowed from Dolphin https://github.com/dolphin-emu/dolphin
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static void Arm64_CacheFlush(void* start, void* end) {
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if (start == end)
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return;
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#if HOST_OS == OS_DARWIN
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// Header file says this is equivalent to: sys_icache_invalidate(start, end - start);
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sys_cache_control(kCacheFunctionPrepareForExecution, start, end - start);
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#else
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// Don't rely on GCC's __clear_cache implementation, as it caches
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// icache/dcache cache line sizes, that can vary between cores on
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// big.LITTLE architectures.
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u64 addr, ctr_el0;
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static size_t icache_line_size = 0xffff, dcache_line_size = 0xffff;
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size_t isize, dsize;
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__asm__ volatile("mrs %0, ctr_el0" : "=r"(ctr_el0));
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isize = 4 << ((ctr_el0 >> 0) & 0xf);
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dsize = 4 << ((ctr_el0 >> 16) & 0xf);
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// use the global minimum cache line size
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icache_line_size = isize = icache_line_size < isize ? icache_line_size : isize;
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dcache_line_size = dsize = dcache_line_size < dsize ? dcache_line_size : dsize;
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addr = (u64)start & ~(u64)(dsize - 1);
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for (; addr < (u64)end; addr += dsize)
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// use "civac" instead of "cvau", as this is the suggested workaround for
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// Cortex-A53 errata 819472, 826319, 827319 and 824069.
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__asm__ volatile("dc civac, %0" : : "r"(addr) : "memory");
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__asm__ volatile("dsb ish" : : : "memory");
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addr = (u64)start & ~(u64)(isize - 1);
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for (; addr < (u64)end; addr += isize)
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__asm__ volatile("ic ivau, %0" : : "r"(addr) : "memory");
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__asm__ volatile("dsb ish" : : : "memory");
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__asm__ volatile("isb" : : : "memory");
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#endif
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}
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void vmem_platform_flush_cache(void *icache_start, void *icache_end, void *dcache_start, void *dcache_end) {
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Arm64_CacheFlush(dcache_start, dcache_end);
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// Dont risk it and flush and invalidate icache&dcache for both ranges just in case.
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if (icache_start != dcache_start)
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Arm64_CacheFlush(icache_start, icache_end);
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}
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#endif // #if HOST_CPU == CPU_ARM64
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