254 lines
4.6 KiB
ArmAsm
254 lines
4.6 KiB
ArmAsm
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.arm
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.align 8
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.equ SH4_TIMESLICE, 448
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.equ BM_BLOCKLIST_MASK, 65532 @FFFC
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.equ CPU_RATIO, 5
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@@@@@@@@@@ some helpers @@@@@@@@@@
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.global do_sqw_nommu_area_3
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@r0: addr
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@r1: sq_both
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do_sqw_nommu_area_3:
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add r3,r1,#0x0C000000 @ get ram ptr from r1, part 1
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and r2,r0,#0x20 @ SQ# selection, isolate
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ubfx r0,r0,#5,#19 @ get ram offset
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add r1,r2 @ SQ# selection, add to SQ ptr
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add r3,#512 @ get ram ptr from r1, part 2
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add r3,r0,lsl #5 @ ram + offset
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vldm r1,{d0-d3}
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vstm r3,{d0-d3}
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bx lr
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.global TAWriteSQ
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@r0: addr
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@r1: sq_both
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TAWriteSQ:
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BIC R3, R0, #0xFE000000 @clear unused bits
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AND R0, R0, #0x20 @SQ#, isolate
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CMP R3, #0x800000 @TA write?
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ADD R0, R1, R0 @SQ#, add to SQ ptr
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BCC _Z13ta_vtx_data32Pv @TA write?
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TAWriteSQ_yuv:
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CMP R3, #0x1000000 @Yuv write ?
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BCS TAWriteSQ_vram
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MOV R1, #1
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B _Z8YUV_dataPjj
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TAWriteSQ_vram: @vram write ..
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#ifdef TARGET_IPHONE
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bkpt #0
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#else
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bkpt
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#endif
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ubfx r0,r3,#5,#18 @ get vram offset
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add r3,r1,#0x04000000 @ get vram ptr from r1, part 1
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add r3,#512 @ get ram ptr from r1, part 2
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add r3,r0,lsl #5 @ ram + offset
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vldm r1,{d0-d3}
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vstm r3,{d0-d3}
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bx lr
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@@@@@@@@@@ ngen_LinkBlock_*****_stub @@@@@@@@@@
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.global ngen_LinkBlock_Generic_stub
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ngen_LinkBlock_Generic_stub:
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mov r1,r4 @ djump/pc -> in case we need it ..
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b ngen_LinkBlock_Shared_stub
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.global ngen_LinkBlock_cond_Branch_stub
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ngen_LinkBlock_cond_Branch_stub:
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mov r1,#1
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b ngen_LinkBlock_Shared_stub
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.global ngen_LinkBlock_cond_Next_stub
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ngen_LinkBlock_cond_Next_stub:
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mov r1,#0
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b ngen_LinkBlock_Shared_stub
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.global ngen_LinkBlock_Shared_stub
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ngen_LinkBlock_Shared_stub:
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mov r0,lr
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sub r0,#4 @go before the call
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bl rdv_LinkBlock
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bx r0
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@@@@@@@@@@ ngen_FailedToFindBlock_ @@@@@@@@@@
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.global ngen_FailedToFindBlock_
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ngen_FailedToFindBlock_:
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mov r0,r4
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bl rdv_FailedToFindBlock
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bx r0
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@@@@@@@@@@ ngen_blockcheckfail @@@@@@@@@@
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.global ngen_blockcheckfail
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ngen_blockcheckfail:
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bl rdv_BlockCheckFail
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bx r0
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@@@@@@@@@@ ngen_mainloop @@@@@@@@@@
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@ you can load the address of the sh4 reg struct on the mainloop init
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@ using (u8*)regptr-(u8*)Sh4cntx
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@ all registers are < 1024 bytes from that
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@ so you can use reg+imm forms for it
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.global ngen_mainloop
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ngen_mainloop:
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push { r4-r12,lr }
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mov r9, #SH4_TIMESLICE @ load cycle counter
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mov r8, r0 @Load context
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ldr r4, [r8,#-184] @load pc
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b no_update @Go to mainloop !
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@this code is here for fall-through behavior of do_iter
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.global intc_sched
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intc_sched: @ next_pc _MUST_ be on ram
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add r9,r9,#SH4_TIMESLICE
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mov r4,lr
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bl UpdateSystem
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mov lr,r4
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cmp r0,#0
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bxeq lr @faster than bxeq r4 (as it should, call stack cache)
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do_iter:
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mov r0,r4
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bl rdv_DoInterrupts
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mov r4,r0
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.global no_update
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no_update: @ next_pc _MUST_ be on r4 *R4 NOT R0 anymore*
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sub r2,r8,#33816576
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ubfx r1,r4,#1,#23
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ldr pc,[r2,r1,lsl #2]
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@bic r1,r4,#0xFF000000
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@ldr pc,[r2,r1,lsl #1]
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pop {r4-r12,lr}
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bx lr
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end_ngen_mainloop:
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@@@@@@@@@@ ngen_mainloop @@@@@@@@@@
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.global arm_compilecode
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arm_compilecode:
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bl CompileCode
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b arm_dispatch
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#ifdef TARGET_IPHONE
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Xarm_Reg: .word arm_Reg
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XEntryPoints: .word EntryPoints
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#endif
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.global arm_mainloop
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arm_mainloop: @(cntx,lookup_base,cycles)
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push {r4,r5,r8,r9,lr}
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#ifdef TARGET_IPHONE
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ldr r8,Xarm_Reg @load cntx
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ldr r4,XEntryPoints @load lookup base
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#else
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ldr r8,=arm_Reg @load cntx
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ldr r4,=EntryPoints @load lookup base
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#endif
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ldr r5,[r8,#192] @load cycle count
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add r5,r0 @add cycles for this timeslice
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b arm_dispatch
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.global arm_dispatch
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arm_dispatch:
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#ifdef TARGET_IPHONE
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ldrd r0,r1,[r8,#184] @load: Next PC, interrupt
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#else
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ldrd r0,[r8,#184] @load: Next PC, interrupt
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#endif
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ubfx r2,r0,#2,#19
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cmp r1,#0
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bne arm_dofiq
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ldr pc,[r4,r2,lsl #2]
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arm_dofiq:
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bl CPUFiq
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b arm_dispatch
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.global arm_exit
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arm_exit:
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str r5,[r8,#192] @if timeslice is over, save remaining cycles
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pop {r4,r5,r8,r9,pc}
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@@@@@@
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@matrix mul
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#ifndef _ANDROID
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.global ftrv_asm
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ftrv_asm:
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@r0=dst,r1=vec,r2=mtx
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@3x vld1.32 might be faster
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vldm r2,{d16-d24}
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vldm r1, {d0-d1}
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VMUL.F32 Q2,Q8,d0[0]
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VMLA.F32 Q2,Q9,d0[1]
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VMLA.F32 Q2,Q10,d1[0]
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VMLA.F32 Q2,Q11,d1[1]
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vstm r0,{d4,d5}
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bx lr
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.global fipr_asm
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fipr_asm:
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@ vdot
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@ idp=fr[n+0]*fr[m+0];
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@ idp+=fr[n+1]*fr[m+1];
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@ idp+=fr[n+2]*fr[m+2];
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@ idp+=fr[n+3]*fr[m+3];
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vldm r0, {d0,d1}
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vldm r1, {d2,d3}
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vmul.f32 q0,q1
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@NEON is quite nice actually ! if only its performance was good enough ...
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vpadd.f32 d0,d0,d1 @d0={d0[0]+d0[1], d1[0]+d1[1]}
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vpadd.f32 d0,d0,d0 @d0={d0[0]+d0[1]+d1[0]+d1[1], d0[0]+d0[1]+d1[0]+d1[1]}
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@store to ret ..
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vmov r0,s0
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bx lr
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#endif
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