137 lines
3.3 KiB
C++
137 lines
3.3 KiB
C++
//gah , ccn emulation
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//CCN: Cache and TLB controller
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#include "types.h"
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#include "hw/sh4/sh4_mmr.h"
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#include "types.h"
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#include "ccn.h"
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#include "../sh4_core.h"
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#include "hw/pvr/pvr_mem.h"
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#include "hw/mem/_vmem.h"
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//Types
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u32 CCN_QACR_TR[2];
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template<u32 idx>
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void CCN_QACR_write(u32 addr, u32 value)
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{
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SH4IO_REGN(CCN,CCN_QACR0_addr+idx*4,32)=value;
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//CCN_QACR[idx].reg_data=value;
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u32 area=((CCN_QACR_type&)value).Area;
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CCN_QACR_TR[idx]=(area<<26)-0xE0000000; //-0xE0000000 because 0xE0000000 is added on the translation again ...
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switch(area)
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{
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case 3:
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if (_nvmem_enabled())
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do_sqw_nommu=&do_sqw_nommu_area_3;
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else
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do_sqw_nommu=&do_sqw_nommu_area_3_nonvmem;
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break;
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case 4:
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do_sqw_nommu=(sqw_fp*)&TAWriteSQ;
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break;
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default: do_sqw_nommu=&do_sqw_nommu_full;
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}
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}
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void CCN_MMUCR_write(u32 addr, u32 value)
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{
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CCN_MMUCR_type temp;
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temp.reg_data=value;
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// if ((temp.AT!=CCN_MMUCR.AT) && (temp.AT==1))
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// {
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// printf("<*******>MMU Enabled , ONLY SQ remaps work<*******>\n");
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// }
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if (temp.TI)
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{
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temp.TI=0;
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}
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CCN_MMUCR=temp;
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}
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void CCN_CCR_write(u32 addr, u32 value)
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{
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CCN_CCR_type temp;
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temp.reg_data=value;
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//what is 0xAC13DBF8 from ?
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if (temp.ICI && curr_pc!=0xAC13DBF8)
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{
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//printf("Sh4: i-cache invalidation %08X\n",curr_pc);
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// Shikigami No Shiro II sets ICI frequently
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// Any reason to flush the dynarec cache for this?
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//sh4_cpu.ResetCache();
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}
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temp.ICI=0;
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temp.OCI=0;
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CCN_CCR=temp;
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}
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//Init/Res/Term
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void ccn_init()
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{
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//CCN PTEH 0xFF000000 0x1F000000 32 Undefined Undefined Held Held Iclk
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sh4_rio_reg(CCN,CCN_PTEH_addr,RIO_DATA,32);
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//CCN PTEL 0xFF000004 0x1F000004 32 Undefined Undefined Held Held Iclk
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sh4_rio_reg(CCN,CCN_PTEL_addr,RIO_DATA,32);
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//CCN TTB 0xFF000008 0x1F000008 32 Undefined Undefined Held Held Iclk
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sh4_rio_reg(CCN,CCN_TTB_addr,RIO_DATA,32);
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//CCN TEA 0xFF00000C 0x1F00000C 32 Undefined Held Held Held Iclk
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sh4_rio_reg(CCN,CCN_TEA_addr,RIO_DATA,32);
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//CCN MMUCR 0xFF000010 0x1F000010 32 0x00000000 0x00000000 Held Held Iclk
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sh4_rio_reg(CCN,CCN_MMUCR_addr,RIO_WF,32,0,&CCN_MMUCR_write);
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//CCN BASRA 0xFF000014 0x1F000014 8 Undefined Held Held Held Iclk
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sh4_rio_reg(CCN,CCN_BASRA_addr,RIO_DATA,8);
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//CCN BASRB 0xFF000018 0x1F000018 8 Undefined Held Held Held Iclk
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sh4_rio_reg(CCN,CCN_BASRB_addr,RIO_DATA,8);
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//CCN CCR 0xFF00001C 0x1F00001C 32 0x00000000 0x00000000 Held Held Iclk
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sh4_rio_reg(CCN,CCN_CCR_addr,RIO_WF,32,0,&CCN_CCR_write);
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//CCN TRA 0xFF000020 0x1F000020 32 Undefined Undefined Held Held Iclk
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sh4_rio_reg(CCN,CCN_TRA_addr,RIO_DATA,32);
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//CCN EXPEVT 0xFF000024 0x1F000024 32 0x00000000 0x00000020 Held Held Iclk
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sh4_rio_reg(CCN,CCN_EXPEVT_addr,RIO_DATA,32);
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//CCN INTEVT 0xFF000028 0x1F000028 32 Undefined Undefined Held Held Iclk
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sh4_rio_reg(CCN,CCN_INTEVT_addr,RIO_DATA,32);
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//CCN PTEA 0xFF000034 0x1F000034 32 Undefined Undefined Held Held Iclk
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sh4_rio_reg(CCN,CCN_PTEA_addr,RIO_DATA,32);
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//CCN QACR0 0xFF000038 0x1F000038 32 Undefined Undefined Held Held Iclk
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sh4_rio_reg(CCN,CCN_QACR0_addr,RIO_WF,32,0,&CCN_QACR_write<0>);
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//CCN QACR1 0xFF00003C 0x1F00003C 32 Undefined Undefined Held Held Iclk
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sh4_rio_reg(CCN,CCN_QACR1_addr,RIO_WF,32,0,&CCN_QACR_write<1>);
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}
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void ccn_reset()
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{
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CCN_TRA = 0x0;
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CCN_EXPEVT = 0x0;
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CCN_MMUCR.reg_data = 0x0;
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CCN_CCR.reg_data = 0x0;
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}
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void ccn_term()
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{
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}
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