131 lines
2.4 KiB
C++
131 lines
2.4 KiB
C++
/*
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PVR-SB handling
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DMA hacks are here
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*/
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#include "pvr_sb_regs.h"
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#include "ta.h"
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#include "hw/holly/holly_intc.h"
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#include "hw/holly/sb.h"
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#include "hw/sh4/modules/dmac.h"
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#include "hw/sh4/sh4_mem.h"
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static void RegWrite_SB_C2DST(u32 addr, u32 data)
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{
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if (data & 1)
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{
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SB_C2DST = 1;
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DMAC_Ch2St();
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}
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}
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//PVR-DMA
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static void do_pvr_dma()
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{
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u32 src = SB_PDSTAR; // System RAM address
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u32 dst = SB_PDSTAP; // VRAM address
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u32 len = SB_PDLEN;
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if (0x8201 != (DMAC_DMAOR.full & DMAOR_MASK))
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{
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INFO_LOG(PVR, "DMAC: DMAOR has invalid settings (%X) !", DMAC_DMAOR.full);
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return;
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}
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DEBUG_LOG(PVR, "PVR-DMA %x %s %x len %x", src, SB_PDDIR ? "<-" : "->", dst, len);
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if (SB_PDDIR)
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//PVR -> System
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WriteMemBlock_nommu_dma(src, dst, len);
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else
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//System -> PVR
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WriteMemBlock_nommu_dma(dst,src,len);
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DMAC_SAR(0) = src + len;
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DMAC_CHCR(0).TE = 1;
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DMAC_DMATCR(0) = 0;
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SB_PDST = 0;
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asic_RaiseInterrupt(holly_PVR_DMA);
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}
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static void RegWrite_SB_PDST(u32 addr, u32 data)
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{
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if (data & 1)
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{
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SB_PDST = 1;
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do_pvr_dma();
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}
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}
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// Auto sort DMA
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static u32 calculate_start_link_addr()
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{
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u8* base = &mem_b[SB_SDSTAW & RAM_MASK];
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u32 rv;
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if (SB_SDWLT == 0)
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//16b width
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rv = ((u16*)base)[SB_SDDIV];
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else
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//32b width
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rv = ((u32*)base)[SB_SDDIV];
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SB_SDDIV++; //next index
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return rv;
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}
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static void pvr_do_sort_dma()
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{
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DEBUG_LOG(PVR, "Sort-DMA SB_SDSTAW %x SB_SDDIV %x SB_SDBAAW %x", SB_SDSTAW, SB_SDDIV, SB_SDBAAW);
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SB_SDDIV = 0; // index is 0 now
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u32 link_addr = calculate_start_link_addr();
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while (link_addr != 2)
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{
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if (SB_SDLAS == 1)
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link_addr *= 32;
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else
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link_addr &= ~31;
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u32 ea = (SB_SDBAAW + link_addr) & RAM_MASK;
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u32* ea_ptr = (u32 *)&mem_b[ea];
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link_addr = ea_ptr[0x1C >> 2];//Next link
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//transfer global param
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ta_vtx_data((const SQBuffer *)ea_ptr, ea_ptr[0x18 >> 2]);
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if (link_addr == 1)
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link_addr = calculate_start_link_addr();
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}
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// End of DMA
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SB_SDST = 0;
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SB_SDSTAW += 32;
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asic_RaiseInterrupt(holly_PVR_SortDMA);
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}
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static void RegWrite_SB_SDST(u32 addr, u32 data)
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{
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if (data & 1)
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pvr_do_sort_dma();
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}
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void pvr_sb_Init()
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{
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//0x005F7C18 SB_PDST RW PVR-DMA start
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sb_rio_register(SB_PDST_addr,RIO_WF,0,&RegWrite_SB_PDST);
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//0x005F6808 SB_C2DST RW ch2-DMA start
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sb_rio_register(SB_C2DST_addr,RIO_WF,0,&RegWrite_SB_C2DST);
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//0x005F6820 SB_SDST RW Sort-DMA start
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sb_rio_register(SB_SDST_addr,RIO_WF,0,&RegWrite_SB_SDST);
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}
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void pvr_sb_Term()
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{
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}
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void pvr_sb_Reset(bool hard)
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{
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}
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