370 lines
7.2 KiB
C++
370 lines
7.2 KiB
C++
/*
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Mostly buggy, old, glue code that somehow still works
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Most of the work is now delegated on vtlb and only helpers are here
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*/
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#include "types.h"
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#include "sh4_mem.h"
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#include "hw/holly/sb_mem.h"
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#include "sh4_mmr.h"
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#include "modules/modules.h"
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#include "hw/pvr/pvr_mem.h"
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#include "hw/sh4/sh4_core.h"
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#include "hw/mem/_vmem.h"
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#include "modules/mmu.h"
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#include "sh4_cache.h"
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//main system mem
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VArray2 mem_b;
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#ifndef NO_MMU
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// Memory handlers
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ReadMem8Func ReadMem8;
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ReadMem16Func ReadMem16;
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ReadMem16Func IReadMem16;
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ReadMem32Func ReadMem32;
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ReadMem64Func ReadMem64;
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WriteMem8Func WriteMem8;
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WriteMem16Func WriteMem16;
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WriteMem32Func WriteMem32;
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WriteMem64Func WriteMem64;
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#endif
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//AREA 1
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static _vmem_handler area1_32b;
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static void map_area1_init()
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{
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area1_32b = _vmem_register_handler_Template(pvr_read_area1, pvr_write_area1);
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}
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static void map_area1(u32 base)
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{
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// VRAM
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//Lower 32 mb map
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//64b interface
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_vmem_map_block(vram.data, 0x04 | base, 0x04 | base, VRAM_MASK);
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//32b interface
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_vmem_map_handler(area1_32b, 0x05 | base, 0x05 | base);
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//Upper 32 mb mirror
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//0x0600 to 0x07FF
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_vmem_mirror_mapping(0x06 | base, 0x04 | base, 0x02);
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}
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//AREA 2
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static void map_area2_init()
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{
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}
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static void map_area2(u32 base)
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{
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}
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//AREA 3
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static void map_area3_init()
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{
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}
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static void map_area3(u32 base)
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{
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// System RAM
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_vmem_map_block_mirror(mem_b.data, 0x0C | base,0x0F | base, RAM_SIZE);
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}
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//AREA 4
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static _vmem_handler area4_handler_lower;
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static _vmem_handler area4_handler_upper;
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static void map_area4_init()
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{
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area4_handler_lower = _vmem_register_handler(pvr_read_area4<u8, false>, pvr_read_area4<u16, false>, pvr_read_area4<u32, false>,
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pvr_write_area4<u8, false>, pvr_write_area4<u16, false>, pvr_write_area4<u32, false>);
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area4_handler_upper = _vmem_register_handler(pvr_read_area4<u8, true>, pvr_read_area4<u16, true>, pvr_read_area4<u32, true>,
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pvr_write_area4<u8, true>, pvr_write_area4<u16, true>, pvr_write_area4<u32, true>);
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}
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static void map_area4(u32 base)
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{
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// VRAM 64b/32b interface
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_vmem_map_handler(area4_handler_lower, 0x11 | base, 0x11 | base);
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// upper mirror
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_vmem_map_handler(area4_handler_upper, 0x13 | base, 0x13 | base);
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}
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//AREA 5 -- Ext. Device
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//Read Ext.Device
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template <class T>
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T DYNACALL ReadMem_extdev_T(u32 addr)
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{
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return (T)libExtDevice_ReadMem_A5(addr, sizeof(T));
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}
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//Write Ext.Device
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template <class T>
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void DYNACALL WriteMem_extdev_T(u32 addr,T data)
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{
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libExtDevice_WriteMem_A5(addr, data, sizeof(T));
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}
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_vmem_handler area5_handler;
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static void map_area5_init()
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{
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area5_handler = _vmem_register_handler_Template(ReadMem_extdev_T,WriteMem_extdev_T);
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}
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static void map_area5(u32 base)
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{
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//map whole region to plugin handler
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_vmem_map_handler(area5_handler,base|0x14,base|0x17);
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}
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//AREA 6 -- Unassigned
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static void map_area6_init()
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{
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}
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static void map_area6(u32 base)
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{
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}
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//set vmem to default values
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void mem_map_default()
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{
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_vmem_init();
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//U0/P0
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//0x0xxx xxxx -> normal memmap
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//0x2xxx xxxx -> normal memmap
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//0x4xxx xxxx -> normal memmap
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//0x6xxx xxxx -> normal memmap
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//-----------
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//P1
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//0x8xxx xxxx -> normal memmap
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//-----------
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//P2
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//0xAxxx xxxx -> normal memmap
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//-----------
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//P3
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//0xCxxx xxxx -> normal memmap
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//-----------
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//P4
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//0xExxx xxxx -> internal area
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//Init Memmaps (register handlers)
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map_area0_init();
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map_area1_init();
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map_area2_init();
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map_area3_init();
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map_area4_init();
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map_area5_init();
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map_area6_init();
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map_area7_init();
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// 00-0C: 7 times the normal memmap mirrors
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for (int i = 0; i < 7; i++)
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{
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map_area0(i << 5); //Bios,Flahsrom,i/f regs,Ext. Device,Sound Ram
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map_area1(i << 5); //VRAM
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map_area2(i << 5); //Unassigned
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map_area3(i << 5); //RAM
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map_area4(i << 5); //TA
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map_area5(i << 5); //Ext. Device
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map_area6(i << 5); //Unassigned
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map_area7(i << 5); //Sh4 Regs
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}
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// E0: p4 region
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map_p4();
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}
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void mem_Init()
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{
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//Allocate mem for memory/bios/flash
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sh4_area0_Init();
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sh4_mmr_init();
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MMU_init();
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}
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//Reset Sysmem/Regs -- Pvr is not changed , bios/flash are not zeroed out
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void mem_Reset(bool hard)
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{
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//mem is reset on hard restart (power on), not soft reset
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if (hard)
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{
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//fill mem w/ 0's
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mem_b.Zero();
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}
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//Reset registers
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sh4_area0_Reset(hard);
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sh4_mmr_reset(hard);
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MMU_reset();
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}
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void mem_Term()
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{
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MMU_term();
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sh4_mmr_term();
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sh4_area0_Term();
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_vmem_term();
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}
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void WriteMemBlock_nommu_dma(u32 dst, u32 src, u32 size)
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{
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bool dst_ismem, src_ismem;
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void* dst_ptr = _vmem_write_const(dst, dst_ismem, 4);
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void* src_ptr = _vmem_read_const(src, src_ismem, 4);
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if (dst_ismem && src_ismem)
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{
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memcpy(dst_ptr, src_ptr, size);
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}
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else if (src_ismem)
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{
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WriteMemBlock_nommu_ptr(dst, (u32*)src_ptr, size);
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}
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else
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{
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verify(size % 4 == 0);
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for (u32 i = 0; i < size; i += 4)
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WriteMem32_nommu(dst + i, ReadMem32_nommu(src + i));
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}
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}
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void WriteMemBlock_nommu_ptr(u32 dst, u32* src, u32 size)
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{
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bool dst_ismem;
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void* dst_ptr = _vmem_write_const(dst, dst_ismem, 4);
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if (dst_ismem)
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{
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memcpy(dst_ptr, src, size);
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}
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else
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{
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for (u32 i = 0; i < size;)
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{
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u32 left = size - i;
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if (left >= 4)
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{
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WriteMem32_nommu(dst + i, src[i >> 2]);
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i += 4;
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}
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else if (left >= 2)
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{
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WriteMem16_nommu(dst + i, ((u16 *)src)[i >> 1]);
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i += 2;
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}
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else
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{
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WriteMem8_nommu(dst + i, ((u8 *)src)[i]);
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i++;
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}
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}
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}
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}
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void WriteMemBlock_nommu_sq(u32 dst, u32* src)
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{
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bool dst_ismem;
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void* dst_ptr = _vmem_write_const(dst, dst_ismem, 4);
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if (dst_ismem)
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{
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memcpy(dst_ptr, src, 32);
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}
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else
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{
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for (u32 i = 0; i < 32; i += 4)
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WriteMem32_nommu(dst + i, src[i >> 2]);
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}
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}
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//Get pointer to ram area , 0 if error
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//For debugger(gdb) - dynarec
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u8* GetMemPtr(u32 Addr,u32 size)
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{
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verify((((Addr>>29) &0x7)!=7));
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switch ((Addr>>26)&0x7)
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{
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case 3:
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return &mem_b[Addr & RAM_MASK];
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case 0:
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case 1:
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case 2:
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case 4:
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case 5:
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case 6:
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case 7:
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default:
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// INFO_LOG(COMMON, "unsupported area : addr=0x%X", Addr);
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return 0;
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}
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}
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static bool interpreterRunning = false;
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void SetMemoryHandlers()
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{
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#ifndef NO_MMU
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#ifdef STRICT_MODE
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if (settings.dynarec.Enable && interpreterRunning)
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{
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// Flush caches when interp -> dynarec
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ocache.WriteBackAll();
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icache.Invalidate();
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}
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if (!settings.dynarec.Enable)
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{
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interpreterRunning = true;
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IReadMem16 = &IReadCachedMem;
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ReadMem8 = &ReadCachedMem<u8>;
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ReadMem16 = &ReadCachedMem<u16>;
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ReadMem32 = &ReadCachedMem<u32>;
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ReadMem64 = &ReadCachedMem<u64>;
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WriteMem8 = &WriteCachedMem<u8>;
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WriteMem16 = &WriteCachedMem<u16>;
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WriteMem32 = &WriteCachedMem<u32>;
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WriteMem64 = &WriteCachedMem<u64>;
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return;
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}
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interpreterRunning = false;
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#endif
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if (CCN_MMUCR.AT == 1 && settings.dreamcast.FullMMU)
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{
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IReadMem16 = &mmu_IReadMem16;
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ReadMem8 = &mmu_ReadMem<u8>;
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ReadMem16 = &mmu_ReadMem<u16>;
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ReadMem32 = &mmu_ReadMem<u32>;
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ReadMem64 = &mmu_ReadMem<u64>;
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WriteMem8 = &mmu_WriteMem<u8>;
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WriteMem16 = &mmu_WriteMem<u16>;
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WriteMem32 = &mmu_WriteMem<u32>;
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WriteMem64 = &mmu_WriteMem<u64>;
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}
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else
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{
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ReadMem8 = &_vmem_ReadMem8;
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ReadMem16 = &_vmem_ReadMem16;
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IReadMem16 = &_vmem_ReadMem16;
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ReadMem32 = &_vmem_ReadMem32;
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ReadMem64 = &_vmem_ReadMem64;
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WriteMem8 = &_vmem_WriteMem8;
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WriteMem16 = &_vmem_WriteMem16;
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WriteMem32 = &_vmem_WriteMem32;
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WriteMem64 = &_vmem_WriteMem64;
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}
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#endif
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}
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