325 lines
6.6 KiB
C++
325 lines
6.6 KiB
C++
/*
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Copyright 2021 flyinghead
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This file is part of Flycast.
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Flycast is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 2 of the License, or
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(at your option) any later version.
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Flycast is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Flycast. If not, see <https://www.gnu.org/licenses/>.
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*/
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#pragma once
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#include "types.h"
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#include "emulator.h"
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#include "hw/sh4/sh4_if.h"
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#include "hw/sh4/sh4_mem.h"
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#include "hw/sh4/sh4_interpreter.h"
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#include "cfg/option.h"
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#include <array>
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#include <signal.h>
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#include <map>
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#ifndef SIGTRAP
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#define SIGTRAP 5
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#endif
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#ifndef SIGBUS
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#define SIGBUS 7
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#endif
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const std::array<Sh4RegType, 59> Sh4RegList {
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reg_r0,
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reg_r1,
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reg_r2,
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reg_r3,
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reg_r4,
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reg_r5,
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reg_r6,
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reg_r7,
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reg_r8,
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reg_r9,
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reg_r10,
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reg_r11,
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reg_r12,
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reg_r13,
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reg_r14,
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reg_r15,
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reg_nextpc,
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reg_pr,
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reg_gbr,
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reg_vbr,
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reg_mach,
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reg_macl,
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reg_sr_status,
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reg_fpul,
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reg_fpscr,
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reg_fr_0, reg_fr_1, reg_fr_2, reg_fr_3, reg_fr_4, reg_fr_5, reg_fr_6, reg_fr_7,
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reg_fr_8, reg_fr_9, reg_fr_10, reg_fr_11, reg_fr_12, reg_fr_13, reg_fr_14, reg_fr_15,
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reg_ssr,
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reg_spc,
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// correct?
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reg_r0, reg_r1, reg_r2, reg_r3, reg_r4, reg_r5, reg_r6, reg_r7,
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reg_r0_Bank, reg_r1_Bank, reg_r2_Bank, reg_r3_Bank, reg_r4_Bank, reg_r5_Bank, reg_r6_Bank, reg_r7_Bank,
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};
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class DebugAgent
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{
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public:
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void doContinue(u32 pc = 1)
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{
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if (pc != 1)
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Sh4cntx.pc = pc;
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dc_resume();
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}
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void step()
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{
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bool restoreBreakpoint = removeMatchpoint(0, Sh4cntx.pc, 2);
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u32 savedPc = Sh4cntx.pc;
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dc_step();
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if (restoreBreakpoint)
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insertMatchpoint(0, savedPc, 2);
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}
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int readAllRegs(u32 **regs)
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{
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static std::array<u32, Sh4RegList.size()> allregs;
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for (u32 i = 0; i < Sh4RegList.size(); i++)
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{
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if (Sh4RegList[i] == reg_sr_status)
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allregs[i] = sh4_sr_GetFull();
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else if (Sh4RegList[i] != NoReg)
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allregs[i] = *GetRegPtr(Sh4RegList[i]);
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}
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*regs = &allregs[0];
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return allregs.size();
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}
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void writeAllRegs(const std::vector<u32>& regs)
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{
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for (u32 i = 0; i < Sh4RegList.size(); i++)
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if (Sh4RegList[i] != NoReg)
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*GetRegPtr(Sh4RegList[i]) = regs[i];
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}
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u32 readReg(u32 regNum)
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{
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if (regNum >= Sh4RegList.size())
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return 0;
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Sh4RegType reg = Sh4RegList[regNum];
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if (reg == reg_sr_status)
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return sh4_sr_GetFull();
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if (reg != NoReg)
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return *GetRegPtr(reg);
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return 0;
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}
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void writeReg(u32 regNum, u32 value)
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{
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if (regNum >= Sh4RegList.size())
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return;
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Sh4RegType reg = Sh4RegList[regNum];
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if (reg == reg_sr_status)
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sh4_sr_SetFull(value);
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else if (reg != NoReg)
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*GetRegPtr(reg) = value;
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}
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const u8 *readMem(u32 addr, u32 len)
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{
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static std::vector<u8> data;
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data.resize(len);
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u8 *p = &data[0];
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while (len > 0)
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{
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if (len >= 4 && (addr & 3) == 0)
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{
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*(u32 *)p = ReadMem32_nommu(addr);
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addr += 4;
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len -= 4;
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p += 4;
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}
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else if (len >= 2 && (addr & 1) == 0)
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{
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*(u16 *)p = ReadMem16_nommu(addr);
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addr += 2;
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len -= 2;
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p += 2;
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}
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else
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{
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*p++ = ReadMem8_nommu(addr);
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addr++;
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len--;
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}
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}
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return &data[0];
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}
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void writeMem(u32 addr, const std::vector<u8>& data)
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{
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const u8 *p = &data[0];
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u32 len = data.size();
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while (len > 0)
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{
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if (len >= 4 && (addr & 3) == 0)
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{
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WriteMem32_nommu(addr, *(u32 *)p);
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addr += 4;
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len -= 4;
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p += 4;
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}
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else if (len >= 2 && (addr & 3) == 0)
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{
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WriteMem16_nommu(addr, *(u16 *)p);
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addr += 2;
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len -= 2;
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p += 2;
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}
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else
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{
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WriteMem8_nommu(addr, *p++);
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addr++;
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len--;
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}
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}
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}
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bool insertMatchpoint(char type, u32 addr, u32 len)
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{
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if (type == 0 && len != 2) {
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WARN_LOG(COMMON, "insertMatchpoint: length != 2: %d", len);
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return false;
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}
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// TODO other matchpoint types
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if (breakpoints.find(addr) != breakpoints.end())
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return true;
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breakpoints[addr] = Breakpoint(type, addr);
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breakpoints[addr].savedOp = ReadMem16_nommu(addr);
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WriteMem16_nommu(addr, 0xC308); // trapa #0x20
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return true;
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}
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bool removeMatchpoint(char type, u32 addr, u32 len)
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{
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if (type == 0 && len != 2) {
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WARN_LOG(COMMON, "removeMatchpoint: length != 2: %d", len);
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return false;
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}
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auto it = breakpoints.find(addr);
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if (it == breakpoints.end())
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return false;
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WriteMem16_nommu(addr, it->second.savedOp);
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breakpoints.erase(it);
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return true;
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}
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u32 interrupt()
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{
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config::DynarecEnabled = false;
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exception = SIGINT;
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dc_stop();
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return exception;
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}
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// called on the emu thread
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void debugTrap(u32 event)
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{
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exception = findException(event);
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Sh4cntx.pc -= 2; // FIXME delay slot
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}
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void postDebugTrap()
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{
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// needed to join the emu thread since debugTrap() is called by it
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dc_stop();
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}
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u32 currentException()
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{
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return exception;
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}
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void restart()
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{
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dc_stop();
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dc_reset(true);
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dc_resume();
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}
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void detach()
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{
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dc_resume();
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}
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void kill()
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{
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dc_exit();
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}
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void resetAgent()
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{
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stack.clear();
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}
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int findException(u32 event)
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{
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switch (event)
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{
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case 0x0A0: // Instruction/data TLB protection violation exception (read)
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case 0x0C0: // Data TLB protection violation exception (write)
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return SIGSEGV;
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case 0x0E0: // Instruction/data address error (read)
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case 0x100: // data address error (write)
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return SIGBUS;
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case 0x160: // trapa
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case 0x1E0: // User break before/after instruction execution
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return SIGTRAP;
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case 0x180: // General illegal instruction exception
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case 0x1A0: // Slot illegal instruction exception
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return SIGILL;
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case 0x120: // FPU exception
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case 0x800: // General FPU disable exception
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case 0x820: // Slot FPU disable exception
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return SIGFPE;
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default:
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return SIGABRT;
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}
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}
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const u32 *getStack(u32& size)
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{
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verify(!Sh4cntx.CpuRunning);
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size = stack.size() * 8;
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return (const u32 *)&stack[0];
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}
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void subroutineCall()
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{
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subroutineReturn();
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stack.push_back(std::make_pair(Sh4cntx.pc, Sh4cntx.r[15]));
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}
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void subroutineReturn()
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{
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while (!stack.empty() && Sh4cntx.r[15] >= stack.back().second)
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stack.pop_back();
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}
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u32 exception = 0;
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struct Breakpoint {
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Breakpoint() = default;
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Breakpoint(u16 type, u32 addr) : addr(addr), type(type) { }
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u32 addr = 0;
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u16 type = 0;
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u16 savedOp = 0;
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};
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std::map<u32, Breakpoint> breakpoints;
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std::vector<std::pair<u32, u32>> stack;
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};
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