248 lines
6.0 KiB
C++
248 lines
6.0 KiB
C++
/*
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Interrupt list caching and handling
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SH4 has a very flexible interrupt controller. In order to handle it efficiently, a sorted
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interrupt bitfield is build from the set interrupt priorities. Higher priorities get allocated
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into higher bits, and a simple mask is kept. In order to check for pending interrupts a simple
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!=0 test works, and to identify the pending interrupt bsr(pend) will give the sorted id. As
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this is a single cycle operation on most platforms, the interrupt checking/identification
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is very fast !
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*/
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#include "types.h"
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#include "sh4_interrupts.h"
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#include "sh4_core.h"
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#include "sh4_mmr.h"
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#include "oslib/oslib.h"
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#include "debug/gdb_server.h"
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#include <cassert>
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//these are fixed
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const u16 IRLPriority = 0x0246;
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#define IRLP9 &IRLPriority,0
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#define IRLP11 &IRLPriority,4
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#define IRLP13 &IRLPriority,8
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#define GIPA(p) &INTC_IPRA.reg_data,4*p
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#define GIPB(p) &INTC_IPRB.reg_data,4*p
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#define GIPC(p) &INTC_IPRC.reg_data,4*p
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struct InterptSourceList_Entry
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{
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const u16* PrioReg;
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u32 Shift;
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Sh4ExceptionCode IntEvnCode;
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int GetPrLvl() const { return (*PrioReg >> Shift) & 0xF; }
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};
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static const InterptSourceList_Entry InterruptSourceList[sh4_INT_ID_COUNT] =
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{
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//IRL
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{ IRLP9, Sh4Ex_ExtInterrupt9 }, //sh4_IRL_9
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{ IRLP11, Sh4Ex_ExtInterruptB }, //sh4_IRL_11
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{ IRLP13, Sh4Ex_ExtInterruptD }, //sh4_IRL_13
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//HUDI
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{ GIPC(0), Sh4Ex_HUDI }, //sh4_HUDI_HUDI
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//GPIO (missing on dc ?)
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{ GIPC(3), Sh4Ex_GPIO }, //sh4_GPIO_GPIOI
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//DMAC
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{ GIPC(2), Sh4Ex_DMAC_DTME0 }, //sh4_DMAC_DMTE0
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{ GIPC(2), Sh4Ex_DMAC_DTME1 }, //sh4_DMAC_DMTE1
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{ GIPC(2), Sh4Ex_DMAC_DTME2 }, //sh4_DMAC_DMTE2
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{ GIPC(2), Sh4Ex_DMAC_DTME3 }, //sh4_DMAC_DMTE3
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{ GIPC(2), Sh4Ex_DMAC_DMAE }, //sh4_DMAC_DMAE
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//TMU
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{ GIPA(3), Sh4Ex_TMU0 }, //sh4_TMU0_TUNI0
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{ GIPA(2), Sh4Ex_TMU1 }, //sh4_TMU1_TUNI1
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{ GIPA(1), Sh4Ex_TMU2 }, //sh4_TMU2_TUNI2
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{ GIPA(1), Sh4Ex_TMU2_TICPI2 }, //sh4_TMU2_TICPI2
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//RTC
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{ GIPA(0), Sh4Ex_RTC_ATI }, //sh4_RTC_ATI
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{ GIPA(0), Sh4Ex_RTC_PRI }, //sh4_RTC_PRI
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{ GIPA(0), Sh4Ex_RTC_CUI }, //sh4_RTC_CUI
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//SCI
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{ GIPB(1), Sh4Ex_SCI_ERI }, //sh4_SCI1_ERI
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{ GIPB(1), Sh4Ex_SCI_RXI }, //sh4_SCI1_RXI
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{ GIPB(1), Sh4Ex_SCI_TXI }, //sh4_SCI1_TXI
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{ GIPB(1), Sh4Ex_SCI_TEI }, //sh4_SCI1_TEI
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//SCIF
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{ GIPC(1), Sh4Ex_SCIF_ERI }, //sh4_SCIF_ERI
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{ GIPC(1), Sh4Ex_SCIF_RXI }, //sh4_SCIF_RXI
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{ GIPC(1), Sh4Ex_SCIF_BRI }, //sh4_SCIF_BRI
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{ GIPC(1), Sh4Ex_SCIF_TXI }, //sh4_SCIF_TXI
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//WDT
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{ GIPB(3), Sh4Ex_WDT }, //sh4_WDT_ITI
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//REF
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{ GIPB(2), Sh4Ex_REF_RCMI }, //sh4_REF_RCMI
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{ GIPA(2), Sh4Ex_REF_ROVI }, //sh4_REF_ROVI
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};
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//Maps siid -> EventID
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alignas(64) Sh4ExceptionCode InterruptEnvId[32];
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//Maps piid -> 1<<siid
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alignas(64) u32 InterruptBit[32];
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//Maps sh4 interrupt level to inclusive bitfield
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alignas(64) u32 InterruptLevelBit[16];
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static bool Do_Interrupt(Sh4ExceptionCode intEvn);
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u32 interrupt_vpend; // Vector of pending interrupts
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u32 interrupt_vmask; // Vector of masked interrupts (-1 inhibits all interrupts)
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u32 decoded_srimask; // Vector of interrupts allowed by SR.IMSK (-1 inhibits all interrupts)
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//bit 0 ~ 27 : interrupt source 27:0. 0 = lowest level, 27 = highest level.
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static void recalc_pending_itrs()
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{
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Sh4cntx.interrupt_pend = interrupt_vpend & interrupt_vmask & decoded_srimask;
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}
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//Rebuild sorted interrupt id table (priorities were updated)
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void SIIDRebuild()
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{
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int cnt = 0;
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u32 vpend = interrupt_vpend;
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u32 vmask = interrupt_vmask;
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interrupt_vpend = 0;
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interrupt_vmask = 0;
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//rebuild interrupt table
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for (int ilevel = 0; ilevel < 16; ilevel++)
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{
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for (int isrc = 0; isrc < sh4_INT_ID_COUNT; isrc++)
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{
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if (InterruptSourceList[isrc].GetPrLvl() == ilevel)
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{
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InterruptEnvId[cnt] = InterruptSourceList[isrc].IntEvnCode;
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u32 p = InterruptBit[isrc] & vpend;
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u32 m = InterruptBit[isrc] & vmask;
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InterruptBit[isrc] = 1 << cnt;
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if (p)
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interrupt_vpend |= InterruptBit[isrc];
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if (m)
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interrupt_vmask |= InterruptBit[isrc];
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cnt++;
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}
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}
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InterruptLevelBit[ilevel] = (1 << cnt) - 1;
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}
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SRdecode();
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}
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//Decode SR.IMSK into a interrupt mask, update and return the interrupt state
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bool SRdecode()
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{
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if (sr.BL)
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decoded_srimask=~0xFFFFFFFF;
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else
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decoded_srimask=~InterruptLevelBit[sr.IMASK];
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recalc_pending_itrs();
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return Sh4cntx.interrupt_pend;
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}
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int UpdateINTC()
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{
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if (!Sh4cntx.interrupt_pend)
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return 0;
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return Do_Interrupt(InterruptEnvId[bitscanrev(Sh4cntx.interrupt_pend)]);
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}
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void SetInterruptPend(InterruptID intr)
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{
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interrupt_vpend |= InterruptBit[intr];
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recalc_pending_itrs();
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}
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void ResetInterruptPend(InterruptID intr)
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{
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interrupt_vpend &= ~InterruptBit[intr];
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recalc_pending_itrs();
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}
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void SetInterruptMask(InterruptID intr)
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{
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interrupt_vmask |= InterruptBit[intr];
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recalc_pending_itrs();
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}
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void ResetInterruptMask(InterruptID intr)
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{
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interrupt_vmask &= ~InterruptBit[intr];
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recalc_pending_itrs();
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}
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static bool Do_Interrupt(Sh4ExceptionCode intEvn)
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{
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CCN_INTEVT = intEvn;
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ssr = sh4_sr_GetFull();
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spc = next_pc;
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sgr = r[15];
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sr.BL = 1;
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sr.MD = 1;
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sr.RB = 1;
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UpdateSR();
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next_pc = vbr + 0x600;
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debugger::subroutineCall();
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return true;
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}
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bool Do_Exception(u32 epc, Sh4ExceptionCode expEvn)
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{
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assert((expEvn >= Sh4Ex_TlbMissRead && expEvn <= Sh4Ex_SlotIllegalInstr)
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|| expEvn == Sh4Ex_FpuDisabled || expEvn == Sh4Ex_SlotFpuDisabled || expEvn == Sh4Ex_UserBreak);
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if (sr.BL != 0)
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throw FlycastException("Fatal: SH4 exception when blocked");
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CCN_EXPEVT = expEvn;
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ssr = sh4_sr_GetFull();
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spc = epc;
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sgr = r[15];
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sr.BL = 1;
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sr.MD = 1;
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sr.RB = 1;
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UpdateSR();
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next_pc = vbr + (expEvn == Sh4Ex_TlbMissRead || expEvn == Sh4Ex_TlbMissWrite ? 0x400 : 0x100);
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debugger::subroutineCall();
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//printf("RaiseException: from pc %08x to %08x, event %x\n", epc, next_pc, expEvn);
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return true;
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}
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//Init/Res/Term
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void interrupts_init()
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{
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}
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void interrupts_reset()
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{
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//reset interrupts cache
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interrupt_vpend = 0;
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interrupt_vmask = 0xFFFFFFFF;
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decoded_srimask = 0;
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for (u32 i = 0; i < sh4_INT_ID_COUNT; i++)
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InterruptBit[i] = 1 << i;
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//rebuild the interrupts table
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SIIDRebuild();
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}
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void interrupts_term()
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{
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}
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