Flyinghead 84f6bd3fef libretro build fixes		2023-01-09 17:44:40 +01:00
..
dyna	dynarec: reg alloc 64-bit regs. avoid some interpreter fallbacks	2022-12-23 16:06:54 +01:00
interpr	get rid of INLINE, NOINLINE, __forceinline	2022-10-22 22:14:19 +02:00
modules	libretro build fixes	2023-01-09 17:44:40 +01:00
fsca-table.h	Moving code around, cleanups	2013-12-28 22:20:08 +01:00
sh4_cache.h	cheats: don't rely on cheat count on load. Fix compile warnings	2021-12-11 18:33:28 +01:00
sh4_core.h	get rid of INLINE, NOINLINE, __forceinline	2022-10-22 22:14:19 +02:00
sh4_core_regs.cpp	dyna: implement missing ops: ldc/stc sr/fpscr, tas, div1	2022-12-17 11:09:51 +01:00
sh4_if.h	dyna: implement missing ops: ldc/stc sr/fpscr, tas, div1	2022-12-17 11:09:51 +01:00
sh4_interpreter.h	dyna: implement missing ops: ldc/stc sr/fpscr, tas, div1	2022-12-17 11:09:51 +01:00
sh4_interrupts.cpp	naomi: close cart on reset. sh4: replace some verify by throw	2021-08-03 09:47:13 +02:00
sh4_interrupts.h	clang-tidy: run readability-inconsistent-declaration-parameter-name and improve parameter names	2021-03-15 19:52:54 +01:00
sh4_mem.cpp	clean up types.h, refactoring	2022-04-14 11:34:45 +02:00
sh4_mem.h	mmu: add address cache to mem slow path. better fastmmu hashtable.	2021-05-14 19:03:57 +02:00
sh4_mmr.cpp	dynarec: reg alloc 64-bit regs. avoid some interpreter fallbacks	2022-12-23 16:06:54 +01:00
sh4_mmr.h	holly, sh4: reg access handlers don't need size. SB_FFST constant 0	2022-12-06 20:42:00 +01:00
sh4_opcode_list.cpp	dyna: implement missing ops: ldc/stc sr/fpscr, tas, div1	2022-12-17 11:09:51 +01:00
sh4_opcode_list.h	get rid of INLINE, NOINLINE, __forceinline	2022-10-22 22:14:19 +02:00
sh4_rom.cpp	Split CFLAGS/CXXFLAGS on core.mk, warning fixes	2014-05-12 20:53:43 +03:00
sh4_rom.h	Moving code around, cleanups	2013-12-28 22:20:08 +01:00
sh4_sched.cpp	sh4: proper write masks for memory-mapped registers	2022-12-06 17:58:30 +01:00
sh4_sched.h	fix sh4 scheduler. use common cycle counter in sh4 context	2021-10-07 16:18:32 +02:00