861 lines
18 KiB
C++
Executable File
861 lines
18 KiB
C++
Executable File
/*
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* <E_DataOp.h Title="ARMv7 ISA Emitter Middle-ware: Data-Processing Instructions" />
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*
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* <?CTYPE
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*
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* <opcode1>{<cond>}{S} <Rd>, <shifter_operand>
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* <opcode1> := MOV | MVN
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*
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* <opcode2>{<cond>} <Rn>, <shifter_operand>
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* <opcode2> := CMP | CMN | TST | TEQ
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*
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* <opcode3>{<cond>}{S} <Rd>, <Rn>, <shifter_operand>
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* <opcode3> := ADD | SUB | RSB | ADC | SBC | RSC | AND | BIC | EOR | ORR
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*
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* ?/>
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*/
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#pragma once
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namespace ARM
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{
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/*
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* imm Rd,[Rn,] imm
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* reg Rd,Rn,Rm shift
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* rsr Rd,Rn,Rm type Rs
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*
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* sp.imm Rd {SP} imm
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* sp.reg Rd {SP} Rm shift
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*
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*/
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#if 0
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#define dpInstr(iName, iId) \
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EAPI iName (eReg Rd, eReg Rn, u32 Imm) ; \
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EAPI iName (eReg Rd, eReg Rn, eReg Rm, eShiftOp type=S_LSL, u32 Imm=0) ; \
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EAPI iName (eReg Rd, eReg Rn, eReg Rm, eShiftOp type, eReg Rs) ;
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#endif
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/*
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ADC IMM 0x02A00000
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ADC REG 0x00A00000
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ADC RSR 0x00A00010
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ADD IMM 0x02800000
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ADD REG 0x00800000
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ADD RSR 0x00800010
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ADD.SP.IMM 0x028D0000
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ADD.SP.REG 0x008D0000
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AND IMM 0x02000000
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AND REG 0x00000000
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AND RSR 0x00000010
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// ASR's do not fit this pattern moved elsewhere //
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BIC IMM 0x03C00000
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BIC REG 0x01C00000
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BIC RSR 0x01C00010
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CMN IMM 0x03700000 // N imm
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CMN REG 0x01700000 // NMshift
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CMN RSR 0x01700010 // NMtypeS
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CMP IMM 0x03500000 // N imm
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CMP REG 0x01500000
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CMP RSR 0x01500010
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EOR IMM 0x02200000
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EOR REG 0x00200000
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EOR REG 0x00200010
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*/
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#define DP_PARAMS (eReg Rd, eReg Rn, ShiftOp Shift, ConditionCode CC=AL)
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#define DP_RPARAMS (eReg Rd, eReg Rn, eReg Rm, ConditionCode CC=AL)
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#define DP_COMMON \
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DECL_I; \
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\
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SET_CC; \
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I |= (Rn&15)<<16; \
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I |= (Rd&15)<<12; \
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I |= (Shift&0xFFF)
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#define DP_RCOMMON \
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DECL_I; \
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\
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SET_CC; \
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I |= (Rn&15)<<16; \
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I |= (Rd&15)<<12; \
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I |= (Rm&15)
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#define DP_OPCODE(opcode) \
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I |= (opcode)<<21
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EAPI AND DP_PARAMS { DP_COMMON; DP_OPCODE(DP_AND); EMIT_I; }
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EAPI EOR DP_PARAMS { DP_COMMON; DP_OPCODE(DP_EOR); EMIT_I; }
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EAPI SUB DP_PARAMS { DP_COMMON; DP_OPCODE(DP_SUB); EMIT_I; }
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EAPI RSB DP_PARAMS { DP_COMMON; DP_OPCODE(DP_RSB); EMIT_I; }
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EAPI ADD DP_PARAMS { DP_COMMON; DP_OPCODE(DP_ADD); EMIT_I; }
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EAPI ADC DP_PARAMS { DP_COMMON; DP_OPCODE(DP_ADC); EMIT_I; }
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EAPI SBC DP_PARAMS { DP_COMMON; DP_OPCODE(DP_SBC); EMIT_I; }
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EAPI RSC DP_PARAMS { DP_COMMON; DP_OPCODE(DP_RSC); EMIT_I; }
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EAPI TST DP_PARAMS { DP_COMMON; DP_OPCODE(DP_TST); EMIT_I; }
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EAPI TEQ DP_PARAMS { DP_COMMON; DP_OPCODE(DP_TEQ); EMIT_I; }
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// EAPI CMP DP_PARAMS { DP_COMMON; DP_OPCODE(DP_CMP); EMIT_I; }
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EAPI CMN DP_PARAMS { DP_COMMON; DP_OPCODE(DP_CMN); EMIT_I; }
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EAPI ORR DP_PARAMS { DP_COMMON; DP_OPCODE(DP_ORR); EMIT_I; }
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EAPI MOV DP_PARAMS { DP_COMMON; DP_OPCODE(DP_MOV); EMIT_I; }
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EAPI BIC DP_PARAMS { DP_COMMON; DP_OPCODE(DP_BIC); EMIT_I; }
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EAPI MVN DP_PARAMS { DP_COMMON; DP_OPCODE(DP_MVN); EMIT_I; }
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#if defined(_DEVEL) && defined(_NODEF_) // These require testing -> CMP/MOV Shifter(Reg)? fmt broken? // Simple third reg type w/ no shifter
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EAPI AND DP_PARAMS { DP_RCOMMON; DP_OPCODE(DP_AND); EMIT_I; }
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EAPI EOR DP_PARAMS { DP_RCOMMON; DP_OPCODE(DP_EOR); EMIT_I; }
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EAPI SUB DP_PARAMS { DP_RCOMMON; DP_OPCODE(DP_SUB); EMIT_I; }
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EAPI RSB DP_PARAMS { DP_RCOMMON; DP_OPCODE(DP_RSB); EMIT_I; }
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EAPI ADD DP_PARAMS { DP_RCOMMON; DP_OPCODE(DP_ADD); EMIT_I; }
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EAPI ADC DP_PARAMS { DP_RCOMMON; DP_OPCODE(DP_ADC); EMIT_I; }
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EAPI SBC DP_PARAMS { DP_RCOMMON; DP_OPCODE(DP_SBC); EMIT_I; }
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EAPI RSC DP_PARAMS { DP_RCOMMON; DP_OPCODE(DP_RSC); EMIT_I; }
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EAPI TST DP_PARAMS { DP_RCOMMON; DP_OPCODE(DP_TST); EMIT_I; }
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EAPI TEQ DP_PARAMS { DP_RCOMMON; DP_OPCODE(DP_TEQ); EMIT_I; }
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EAPI CMP DP_PARAMS { DP_RCOMMON; DP_OPCODE(DP_CMP); EMIT_I; }
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EAPI CMN DP_PARAMS { DP_RCOMMON; DP_OPCODE(DP_CMN); EMIT_I; }
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EAPI ORR DP_PARAMS { DP_RCOMMON; DP_OPCODE(DP_ORR); EMIT_I; }
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EAPI MOV DP_PARAMS { DP_RCOMMON; DP_OPCODE(DP_MOV); EMIT_I; }
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EAPI BIC DP_PARAMS { DP_RCOMMON; DP_OPCODE(DP_BIC); EMIT_I; }
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EAPI MVN DP_PARAMS { DP_RCOMMON; DP_OPCODE(DP_MVN); EMIT_I; }
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#endif
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static u32 ARMImmid8r4_enc(u32 imm32)
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{
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for (int i=0;i<=30;i+=2)
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{
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u32 immv=(imm32<<i) | (imm32>>(32-i));
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if (i == 0)
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immv = imm32;
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if (immv<256)
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{
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return ((i/2)<<8) | immv;
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}
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}
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return -1;
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}
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static u32 ARMImmid8r4(u32 imm8r4)
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{
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u32 rv = ARMImmid8r4_enc(imm8r4);
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verify(rv!=-1);
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return rv;
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}
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static bool is_i8r4(u32 i32) { return ARMImmid8r4_enc(i32) != -1; }
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EAPI ADD(eReg Rd, eReg Rn, eReg Rm, u32 RmLSL, bool S, ConditionCode CC=AL)
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{
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DECL_Id(0x00800000);
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if (S)
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I |= 1<<20;
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I |= (RmLSL&31)<<7;
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SET_CC;
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I |= (Rn&15)<<16;
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I |= (Rd&15)<<12;
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I |= (Rm&15);
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EMIT_I;
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}
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EAPI ADD(eReg Rd, eReg Rn, eReg Rm, bool S, ConditionCode CC=AL)
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{
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ADD(Rd,Rn,Rm,0,S,CC);
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}
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EAPI ADD(eReg Rd, eReg Rn, eReg Rm, ShiftOp Shift, u32 Imm8, ConditionCode CC=AL)
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{
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DECL_Id(0x00800000);
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SET_CC;
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I |= (Rn&15)<<16;
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I |= (Rd&15)<<12;
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I |= (Rm&15);
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I |= Shift<<5;
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I |= (Imm8&31)<<7;
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EMIT_I;
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}
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EAPI ADD(eReg Rd, eReg Rn, eReg Rm, ConditionCode CC=AL)
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{
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ADD(Rd,Rn,Rm,false,CC);
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}
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EAPI ADD(eReg Rd, eReg Rn, s32 Imm8, ConditionCode CC=AL)
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{
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DECL_Id(0x02800000);
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SET_CC;
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I |= (Rn&15)<<16;
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I |= (Rd&15)<<12;
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I |= ARMImmid8r4(Imm8); // * 12b imm is 8b imm 4b rot. spec, add rot support!
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EMIT_I;
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}
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EAPI ADC(eReg Rd, eReg Rn, eReg Rm, bool S, ConditionCode CC=AL)
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{
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DECL_Id(0x00A00000);
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if (S)
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I |= 1<<20;
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SET_CC;
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I |= (Rn&15)<<16;
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I |= (Rd&15)<<12;
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I |= (Rm&15);
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EMIT_I;
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}
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EAPI ADC(eReg Rd, eReg Rn, eReg Rm, ConditionCode CC=AL)
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{
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ADC(Rd,Rn,Rm,false,CC);
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}
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EAPI ADC(eReg Rd, eReg Rn, s32 Imm8, ConditionCode CC=AL)
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{
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DECL_Id(0x02A00000);
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SET_CC;
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I |= (Rn&15)<<16;
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I |= (Rd&15)<<12;
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I |= ARMImmid8r4(Imm8); // * 12b imm is 8b imm 4b rot. spec, add rot support!
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EMIT_I;
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}
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EAPI ADC(eReg Rd, eReg Rn, eReg Rm, bool S, ShiftOp Shift, u32 Imm8, ConditionCode CC=AL)
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{
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DECL_Id(0x00A00000);
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if (S)
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I |= 1<<20;
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SET_CC;
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I |= (Rn&15)<<16;
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I |= (Rd&15)<<12;
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I |= (Rm&15);
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I |= Shift<<5;
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I |= (Imm8&31)<<7;
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EMIT_I;
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}
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EAPI ADR(eReg Rd, s32 Imm8, ConditionCode CC=AL)
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{
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DECL_Id(0x028F0000);
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SET_CC;
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I |= (Rd&15)<<12;
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I |= ARMImmid8r4(Imm8); // * 12b imm is 8b imm 4b rot. spec, add rot support!
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EMIT_I;
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}
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EAPI ADR_Zero(eReg Rd, s32 Imm8, ConditionCode CC=AL) // Special case for subtraction of 0
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{
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DECL_Id(0x024F0000);
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SET_CC;
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I |= (Rd&15)<<12;
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I |= ARMImmid8r4(Imm8); // * 12b imm is 8b imm 4b rot. spec, add rot support!
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EMIT_I;
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}
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EAPI ORR(eReg Rd, eReg Rn, eReg Rm, ConditionCode CC=AL)
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{
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DECL_Id(0x01800000);
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SET_CC;
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I |= (Rn&15)<<16;
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I |= (Rd&15)<<12;
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I |= (Rm&15);
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EMIT_I;
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}
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EAPI ORR(eReg Rd, eReg Rn, s32 Imm8, ConditionCode CC=AL)
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{
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DECL_Id(0x03800000);
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SET_CC;
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I |= (Rn&15)<<16;
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I |= (Rd&15)<<12;
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I |= ARMImmid8r4(Imm8); // * 12b imm is 8b imm 4b rot. spec, add rot support!
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EMIT_I;
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}
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EAPI ORR(eReg Rd, eReg Rn, eReg Rm, ShiftOp Shift, eReg Rs, ConditionCode CC=AL)
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{
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DECL_Id(0x01800000);
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SET_CC;
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I |= (Rn&15)<<16;
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I |= (Rd&15)<<12;
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I |= (Rm&15);
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I |= Shift<<5;
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I |= (Rs&15)<<8;
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I |= 1<<4;
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EMIT_I;
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}
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EAPI ORR(eReg Rd, eReg Rn, eReg Rm, bool S, ShiftOp Shift, u32 Imm8, ConditionCode CC=AL)
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{
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DECL_Id(0x01800000);
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if (S)
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I |= 1<<20;
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SET_CC;
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I |= (Rn&15)<<16;
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I |= (Rd&15)<<12;
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I |= (Rm&15);
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I |= Shift<<5;
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I |= (Imm8&31)<<7;
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EMIT_I;
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}
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EAPI AND(eReg Rd, eReg Rn, eReg Rm, bool S, ConditionCode CC=AL)
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{
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DECL_Id(0x00000000);
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if (S)
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I |= 1<<20;
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SET_CC;
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I |= (Rn&15)<<16;
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I |= (Rd&15)<<12;
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I |= (Rm&15);
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EMIT_I;
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}
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EAPI AND(eReg Rd, eReg Rn, eReg Rm, ConditionCode CC=AL)
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{
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DECL_Id(0x00000000);
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SET_CC;
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I |= (Rn&15)<<16;
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I |= (Rd&15)<<12;
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I |= (Rm&15);
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EMIT_I;
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}
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EAPI AND(eReg Rd, eReg Rn, s32 Imm8, ConditionCode CC=AL)
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{
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DECL_Id(0x02000000);
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SET_CC;
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I |= (Rn&15)<<16;
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I |= (Rd&15)<<12;
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I |= ARMImmid8r4(Imm8); // * 12b imm is 8b imm 4b rot. spec, add rot support!
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EMIT_I;
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}
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EAPI AND(eReg Rd, eReg Rn, s32 Imm8, bool S, ConditionCode CC=AL)
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{
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DECL_Id(0x02000000);
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if (S)
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I |= 1<<20;
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SET_CC;
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I |= (Rn&15)<<16;
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I |= (Rd&15)<<12;
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I |= ARMImmid8r4(Imm8); // * 12b imm is 8b imm 4b rot. spec, add rot support!
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EMIT_I;
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}
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EAPI EOR(eReg Rd, eReg Rn, eReg Rm, ConditionCode CC=AL)
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{
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DECL_Id(0x00200000);
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SET_CC;
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I |= (Rn&15)<<16;
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I |= (Rd&15)<<12;
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I |= (Rm&15);
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EMIT_I;
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}
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EAPI EOR(eReg Rd, eReg Rn, eReg Rm, bool S, ConditionCode CC=AL)
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{
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DECL_Id(0x00200000);
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if (S)
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I |= 1<<20;
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SET_CC;
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I |= (Rn&15)<<16;
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I |= (Rd&15)<<12;
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I |= (Rm&15);
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EMIT_I;
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}
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EAPI EOR(eReg Rd, eReg Rn, s32 Imm8, ConditionCode CC=AL)
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{
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DECL_Id(0x02200000);
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SET_CC;
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I |= (Rn&15)<<16;
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I |= (Rd&15)<<12;
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I |= ARMImmid8r4(Imm8); // * 12b imm is 8b imm 4b rot. spec, add rot support!
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EMIT_I;
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}
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EAPI SUB(eReg Rd, eReg Rn, eReg Rm, ConditionCode CC=AL)
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{
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DECL_Id(0x00400000);
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SET_CC;
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I |= (Rn&15)<<16;
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I |= (Rd&15)<<12;
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I |= (Rm&15);
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EMIT_I;
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}
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EAPI SUB(eReg Rd, eReg Rn, s32 Imm8, bool S, ConditionCode CC=AL)
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{
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DECL_Id(0x02400000);
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SET_CC;
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I |= (Rn&15)<<16;
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I |= (Rd&15)<<12;
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I |= ARMImmid8r4(Imm8); // * 12b imm is 8b imm 4b rot. spec, add rot support!
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if (S)
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I |= 1<<20;
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EMIT_I;
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}
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EAPI SUB(eReg Rd, eReg Rn, s32 Imm8, ConditionCode CC=AL) { SUB(Rd,Rn,Imm8,false,CC); }
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EAPI SBC(eReg Rd, eReg Rn, eReg Rm, bool S, ConditionCode CC=AL)
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{
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DECL_Id(0x00C00000);
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if (S)
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I |= 1<<20;
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SET_CC;
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I |= (Rn&15)<<16;
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I |= (Rd&15)<<12;
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I |= (Rm&15);
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EMIT_I;
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}
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EAPI SBC(eReg Rd, eReg Rn, eReg Rm, ConditionCode CC=AL)
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{
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SBC(Rd,Rn,Rm,false,CC);
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}
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EAPI RSB(eReg Rd, eReg Rn, eReg Rm, ConditionCode CC=AL)
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{
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DECL_Id(0x00600000);
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SET_CC;
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I |= (Rn&15)<<16;
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I |= (Rd&15)<<12;
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I |= (Rm&15);
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EMIT_I;
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}
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EAPI RSB(eReg Rd, eReg Rn, s32 Imm8, ConditionCode CC=AL)
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{
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DECL_Id(0x02600000);
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SET_CC;
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I |= (Rn&15)<<16;
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I |= (Rd&15)<<12;
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I |= ARMImmid8r4(Imm8); // * 12b imm is 8b imm 4b rot. spec, add rot support!
|
|
EMIT_I;
|
|
}
|
|
|
|
EAPI RSB(eReg Rd, eReg Rn, s32 Imm8, bool S, ConditionCode CC=AL)
|
|
{
|
|
DECL_Id(0x02600000);
|
|
|
|
if (S)
|
|
I |= 1<<20;
|
|
|
|
SET_CC;
|
|
I |= (Rn&15)<<16;
|
|
I |= (Rd&15)<<12;
|
|
I |= ARMImmid8r4(Imm8); // * 12b imm is 8b imm 4b rot. spec, add rot support!
|
|
EMIT_I;
|
|
}
|
|
|
|
|
|
EAPI MVN(eReg Rd, eReg Rm, ConditionCode CC=AL)
|
|
{
|
|
DECL_Id(0x01E00000);
|
|
|
|
SET_CC;
|
|
I |= (Rd&15)<<12;
|
|
I |= (Rm&15);
|
|
EMIT_I;
|
|
}
|
|
|
|
|
|
EAPI MVN(eReg Rd, s32 Imm8, ConditionCode CC=AL)
|
|
{
|
|
DECL_Id(0x03E00000);
|
|
|
|
SET_CC;
|
|
I |= (Rd&15)<<12;
|
|
I |= ARMImmid8r4(Imm8); // * 12b imm is 8b imm 4b rot. spec, add rot support!
|
|
EMIT_I;
|
|
}
|
|
|
|
|
|
EAPI TST(eReg Rn, eReg Rm, ConditionCode CC=AL)
|
|
{
|
|
DECL_Id(0x01100000);
|
|
|
|
SET_CC;
|
|
I |= (Rn&15)<<16;
|
|
I |= (Rm&15);
|
|
EMIT_I;
|
|
}
|
|
|
|
|
|
EAPI TST(eReg Rn, u32 Imm12, ConditionCode CC=AL)
|
|
{
|
|
DECL_Id(0x03100000);
|
|
|
|
SET_CC;
|
|
I |= (Rn&15)<<16;
|
|
I |= ARMImmid8r4(Imm12);
|
|
EMIT_I;
|
|
}
|
|
|
|
EAPI BIC(eReg Rd, eReg Rn, s32 Imm8, ConditionCode CC=AL)
|
|
{
|
|
DECL_Id(0x03C00000);
|
|
|
|
SET_CC;
|
|
I |= (Rn&15)<<16;
|
|
I |= (Rd&15)<<12;
|
|
I |= ARMImmid8r4(Imm8); // * 12b imm is 8b imm 4b rot. spec, add rot support!
|
|
EMIT_I;
|
|
}
|
|
|
|
|
|
/*
|
|
*
|
|
*/
|
|
|
|
EAPI UBFX(eReg Rd, eReg Rm, u8 lsb, u8 width, ConditionCode CC=AL)
|
|
{
|
|
DECL_Id(0x07E00050);
|
|
verify(lsb+width<=32);
|
|
|
|
SET_CC;
|
|
I |= (Rd&15)<<12;
|
|
I |= (Rm&15);
|
|
I |= (lsb&31)<<7;
|
|
I |= ((width-1)&31)<<16;
|
|
EMIT_I;
|
|
}
|
|
|
|
EAPI SBFX(eReg Rd, eReg Rm, u8 lsb, u8 width, ConditionCode CC=AL)
|
|
{
|
|
DECL_Id(0x07A00050);
|
|
verify(lsb+width<=32);
|
|
|
|
SET_CC;
|
|
I |= (Rd&15)<<12;
|
|
I |= (Rm&15);
|
|
I |= (lsb&31)<<7;
|
|
I |= ((width-1)&31)<<16;
|
|
EMIT_I;
|
|
}
|
|
|
|
EAPI MOV(eReg Rd, eReg Rm, ConditionCode CC=AL)
|
|
{
|
|
DECL_Id(0x01A00000);
|
|
|
|
SET_CC;
|
|
I |= (Rd&15)<<12;
|
|
I |= (Rm&15);
|
|
EMIT_I;
|
|
}
|
|
|
|
EAPI MOV(eReg Rd, eReg Rm, bool S, ConditionCode CC=AL)
|
|
{
|
|
DECL_Id(0x01A00000);
|
|
|
|
if (S)
|
|
I |= 1<<20;
|
|
|
|
SET_CC;
|
|
I |= (Rd&15)<<12;
|
|
I |= (Rm&15);
|
|
EMIT_I;
|
|
}
|
|
|
|
EAPI MOV(eReg Rd, eReg Rm, ShiftOp Shift, u32 Imm8, ConditionCode CC=AL)
|
|
{
|
|
DECL_Id(0x01A00000);
|
|
|
|
SET_CC;
|
|
I |= (Rd&15)<<12;
|
|
I |= (Rm&15);
|
|
I |= Shift<<5;
|
|
I |= (Imm8&31)<<7;
|
|
EMIT_I;
|
|
}
|
|
|
|
EAPI MOV(eReg Rd, eReg Rm, ShiftOp Shift, eReg Rs, ConditionCode CC=AL)
|
|
{
|
|
DECL_Id(0x01A00000);
|
|
|
|
SET_CC;
|
|
I |= (Rd&15)<<12;
|
|
I |= (Rm&15);
|
|
I |= Shift<<5;
|
|
I |= (Rs&15)<<8;
|
|
I |= 1<<4;
|
|
EMIT_I;
|
|
}
|
|
|
|
EAPI MOVW(eReg Rd, u32 Imm16, ConditionCode CC=AL)
|
|
{
|
|
DECL_Id(0x03000000);
|
|
|
|
SET_CC;
|
|
I |= (Imm16&0xF000)<<4;
|
|
I |= (Rd&15)<<12;
|
|
I |= (Imm16&0x0FFF);
|
|
EMIT_I;
|
|
}
|
|
|
|
EAPI MOVT(eReg Rd, u32 Imm16, ConditionCode CC=AL)
|
|
{
|
|
DECL_Id(0x03400000);
|
|
|
|
SET_CC;
|
|
I |= (Imm16&0xF000)<<4;
|
|
I |= (Rd&15)<<12;
|
|
I |= (Imm16&0x0FFF);
|
|
EMIT_I;
|
|
}
|
|
|
|
EAPI MOV(eReg Rd, s32 Imm8, ConditionCode CC=AL)
|
|
{
|
|
DECL_Id(0x03A00000);
|
|
|
|
SET_CC;
|
|
I |= (Rd&15)<<12;
|
|
I |= ARMImmid8r4(Imm8); // * 12b imm is 8b imm 4b rot. spec, add rot support!
|
|
EMIT_I;
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
EAPI CMP(eReg Rn, eReg Rm, ConditionCode CC=AL)
|
|
{
|
|
DECL_Id(0x01500000);
|
|
|
|
SET_CC;
|
|
I |= (Rn&15)<<16;
|
|
I |= (Rm&15);
|
|
EMIT_I;
|
|
}
|
|
|
|
|
|
EAPI CMP(eReg Rn, s32 Imm8, ConditionCode CC=AL)
|
|
{
|
|
DECL_Id(0x03500000);
|
|
|
|
SET_CC;
|
|
I |= (Rn&15)<<16;
|
|
I |= ARMImmid8r4(Imm8); // *FIXME* 12b imm is 8b imm 4b rot. spec, add rot support!
|
|
EMIT_I;
|
|
}
|
|
|
|
EAPI CMP(eReg Rd, eReg Rm, ShiftOp Shift, eReg Rs, ConditionCode CC=AL)
|
|
{
|
|
DECL_Id(0x01500000);
|
|
|
|
SET_CC;
|
|
I |= (Rd&15)<<12;
|
|
I |= (Rm&15);
|
|
I |= Shift<<5;
|
|
I |= (Rs&15)<<8;
|
|
I |= 1<<4;
|
|
EMIT_I;
|
|
}
|
|
|
|
EAPI CMP(eReg Rd, eReg Rm, ShiftOp Shift, u32 Imm8, ConditionCode CC=AL)
|
|
{
|
|
DECL_Id(0x01500000);
|
|
|
|
SET_CC;
|
|
I |= (Rd&15)<<12;
|
|
I |= (Rm&15);
|
|
I |= Shift<<5;
|
|
I |= (Imm8&31)<<7;
|
|
EMIT_I;
|
|
}
|
|
|
|
EAPI LSL(eReg Rd, eReg Rn, eReg Rm, ConditionCode CC=AL)
|
|
{
|
|
DECL_Id(0x01A00010);
|
|
|
|
SET_CC;
|
|
I |= (Rd&15)<<12;
|
|
I |= (Rm&15)<<8;
|
|
I |= (Rn&15)<<0;
|
|
EMIT_I;
|
|
}
|
|
EAPI LSL(eReg Rd, eReg Rm, s32 imm5, ConditionCode CC=AL)
|
|
{
|
|
DECL_Id(0x01A00000);
|
|
|
|
SET_CC;
|
|
I |= (Rd&15)<<12;
|
|
I |= (Rm&15)<<0;
|
|
I |= (imm5&31)<<7;
|
|
EMIT_I;
|
|
}
|
|
|
|
EAPI LSR(eReg Rd, eReg Rn, eReg Rm, ConditionCode CC=AL)
|
|
{
|
|
DECL_Id(0x01A00030);
|
|
|
|
SET_CC;
|
|
I |= (Rd&15)<<12;
|
|
I |= (Rm&15)<<8;
|
|
I |= (Rn&15)<<0;
|
|
EMIT_I;
|
|
}
|
|
|
|
EAPI RRX(eReg Rd, eReg Rm,bool S=false, ConditionCode CC=AL)
|
|
{
|
|
DECL_Id(0x01A00060);
|
|
|
|
if (S)
|
|
I |= 1<<20;
|
|
|
|
SET_CC;
|
|
I |= (Rd&15)<<12;
|
|
I |= (Rm&15)<<0;
|
|
EMIT_I;
|
|
}
|
|
|
|
|
|
EAPI LSR(eReg Rd, eReg Rm, s32 imm5, bool S, ConditionCode CC=AL)
|
|
{
|
|
DECL_Id(0x01A00020);
|
|
|
|
if (S)
|
|
I |= 1<<20;
|
|
|
|
SET_CC;
|
|
I |= (Rd&15)<<12;
|
|
I |= (Rm&15)<<0;
|
|
I |= (imm5&31)<<7;
|
|
EMIT_I;
|
|
}
|
|
|
|
EAPI LSR(eReg Rd, eReg Rm, s32 imm5, ConditionCode CC=AL)
|
|
{
|
|
LSR(Rd,Rm,imm5,false,CC);
|
|
}
|
|
|
|
|
|
EAPI ASR(eReg Rd, eReg Rn, eReg Rm, ConditionCode CC=AL)
|
|
{
|
|
DECL_Id(0x01A00050);
|
|
|
|
SET_CC;
|
|
I |= (Rd&15)<<12;
|
|
I |= (Rm&15)<<8;
|
|
I |= (Rn&15)<<0;
|
|
EMIT_I;
|
|
}
|
|
|
|
EAPI ASR(eReg Rd, eReg Rm, s32 imm5, ConditionCode CC=AL)
|
|
{
|
|
DECL_Id(0x01A00040);
|
|
|
|
SET_CC;
|
|
I |= (Rd&15)<<12;
|
|
I |= (Rm&15)<<0;
|
|
I |= (imm5&31)<<7;
|
|
EMIT_I;
|
|
}
|
|
|
|
EAPI ROR(eReg Rd, eReg Rn, eReg Rm, ConditionCode CC=AL)
|
|
{
|
|
DECL_Id(0x01A00070);
|
|
|
|
SET_CC;
|
|
I |= (Rd&15)<<12;
|
|
I |= (Rm&15)<<8;
|
|
I |= (Rn&15)<<0;
|
|
EMIT_I;
|
|
}
|
|
|
|
EAPI ROR(eReg Rd, eReg Rm, s32 imm5, ConditionCode CC=AL)
|
|
{
|
|
DECL_Id(0x01A00060);
|
|
|
|
SET_CC;
|
|
I |= (Rd&15)<<12;
|
|
I |= (Rm&15)<<0;
|
|
I |= (imm5&31)<<7;
|
|
EMIT_I;
|
|
}
|
|
|
|
|
|
|
|
|
|
#undef DP_PARAMS
|
|
#undef DP_RPARAMS
|
|
|
|
#undef DP_COMMON
|
|
#undef DP_RCOMMON
|
|
|
|
#undef DP_OPCODE
|
|
|
|
|
|
|
|
};
|