248 lines
5.9 KiB
C++
248 lines
5.9 KiB
C++
#include "pvr_regs.h"
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#include "pvr_mem.h"
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#include "Renderer_if.h"
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#include "ta.h"
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#include "spg.h"
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#include <map>
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bool pal_needs_update=true;
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bool fog_needs_update=true;
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u8 pvr_regs[pvr_RegSize];
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#define PVR_REG_NAME(r) { r##_addr, #r },
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const std::map<u32, const char *> pvr_reg_names = {
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PVR_REG_NAME(ID)
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PVR_REG_NAME(REVISION)
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PVR_REG_NAME(SOFTRESET)
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PVR_REG_NAME(STARTRENDER)
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PVR_REG_NAME(TEST_SELECT)
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PVR_REG_NAME(PARAM_BASE)
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PVR_REG_NAME(REGION_BASE)
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PVR_REG_NAME(SPAN_SORT_CFG)
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PVR_REG_NAME(VO_BORDER_COL)
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PVR_REG_NAME(FB_R_CTRL)
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PVR_REG_NAME(FB_W_CTRL)
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PVR_REG_NAME(FB_W_LINESTRIDE)
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PVR_REG_NAME(FB_R_SOF1)
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PVR_REG_NAME(FB_R_SOF2)
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PVR_REG_NAME(FB_R_SIZE)
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PVR_REG_NAME(FB_W_SOF1)
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PVR_REG_NAME(FB_W_SOF2)
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PVR_REG_NAME(FB_X_CLIP)
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PVR_REG_NAME(FB_Y_CLIP)
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PVR_REG_NAME(FPU_SHAD_SCALE)
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PVR_REG_NAME(FPU_CULL_VAL)
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PVR_REG_NAME(FPU_PARAM_CFG)
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PVR_REG_NAME(HALF_OFFSET)
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PVR_REG_NAME(FPU_PERP_VAL)
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PVR_REG_NAME(ISP_BACKGND_D)
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PVR_REG_NAME(ISP_BACKGND_T)
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PVR_REG_NAME(ISP_FEED_CFG)
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PVR_REG_NAME(SDRAM_REFRESH)
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PVR_REG_NAME(SDRAM_ARB_CFG)
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PVR_REG_NAME(SDRAM_CFG)
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PVR_REG_NAME(FOG_COL_RAM)
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PVR_REG_NAME(FOG_COL_VERT)
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PVR_REG_NAME(FOG_DENSITY)
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PVR_REG_NAME(FOG_CLAMP_MAX)
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PVR_REG_NAME(FOG_CLAMP_MIN)
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PVR_REG_NAME(SPG_TRIGGER_POS)
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PVR_REG_NAME(SPG_HBLANK_INT)
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PVR_REG_NAME(SPG_VBLANK_INT)
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PVR_REG_NAME(SPG_CONTROL)
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PVR_REG_NAME(SPG_HBLANK)
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PVR_REG_NAME(SPG_LOAD)
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PVR_REG_NAME(SPG_VBLANK)
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PVR_REG_NAME(SPG_WIDTH)
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PVR_REG_NAME(TEXT_CONTROL)
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PVR_REG_NAME(VO_CONTROL)
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PVR_REG_NAME(VO_STARTX)
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PVR_REG_NAME(VO_STARTY)
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PVR_REG_NAME(SCALER_CTL)
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PVR_REG_NAME(PAL_RAM_CTRL)
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PVR_REG_NAME(SPG_STATUS)
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PVR_REG_NAME(FB_BURSTCTRL)
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PVR_REG_NAME(FB_C_SOF)
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PVR_REG_NAME(Y_COEFF)
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PVR_REG_NAME(PT_ALPHA_REF)
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PVR_REG_NAME(TA_OL_BASE)
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PVR_REG_NAME(TA_ISP_BASE)
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PVR_REG_NAME(TA_OL_LIMIT)
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PVR_REG_NAME(TA_ISP_LIMIT)
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PVR_REG_NAME(TA_NEXT_OPB)
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PVR_REG_NAME(TA_ITP_CURRENT)
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PVR_REG_NAME(TA_GLOB_TILE_CLIP)
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PVR_REG_NAME(TA_ALLOC_CTRL)
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PVR_REG_NAME(TA_LIST_INIT)
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PVR_REG_NAME(TA_YUV_TEX_BASE)
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PVR_REG_NAME(TA_YUV_TEX_CTRL)
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PVR_REG_NAME(TA_YUV_TEX_CNT)
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PVR_REG_NAME(TA_LIST_CONT)
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PVR_REG_NAME(TA_NEXT_OPB_INIT)
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PVR_REG_NAME(SIGNATURE1)
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PVR_REG_NAME(SIGNATURE2)
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};
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#undef PVR_REG_NAME
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static const char *regName(u32 paddr)
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{
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u32 addr = paddr & pvr_RegMask;
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static char regName[32];
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auto it = pvr_reg_names.find(addr);
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if (it == pvr_reg_names.end())
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{
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if (addr >= FOG_TABLE_START_addr && addr <= FOG_TABLE_END_addr)
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sprintf(regName, "FOG_TABLE[%x]", addr - FOG_TABLE_START_addr);
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else if (addr >= TA_OL_POINTERS_START_addr && addr <= TA_OL_POINTERS_END_addr)
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sprintf(regName, "TA_OL_POINTERS[%x]", addr - TA_OL_POINTERS_START_addr);
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else if (addr >= PALETTE_RAM_START_addr && addr <= PALETTE_RAM_END_addr)
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sprintf(regName, "PALETTE[%x]", addr - PALETTE_RAM_START_addr);
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else
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sprintf(regName, "?%08x", paddr);
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return regName;
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}
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else
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return it->second;
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}
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u32 pvr_ReadReg(u32 addr)
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{
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if ((addr & pvr_RegMask) != SPG_STATUS_addr)
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DEBUG_LOG(PVR, "read %s.%c == %x", regName(addr),
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((addr >> 26) & 7) == 2 ? 'b' : (addr & 0x2000000) ? '1' : '0',
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PvrReg(addr, u32));
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return PvrReg(addr,u32);
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}
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void pvr_WriteReg(u32 paddr,u32 data)
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{
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u32 addr = paddr & pvr_RegMask;
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DEBUG_LOG(PVR, "write %s.%c = %x", regName(paddr),
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((paddr >> 26) & 7) == 2 ? 'b' : (paddr & 0x2000000) ? '1' : '0',
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data);
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switch (addr)
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{
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case ID_addr:
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case REVISION_addr:
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case TA_YUV_TEX_CNT_addr:
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return; // read only
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case STARTRENDER_addr:
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//start render
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rend_start_render();
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return;
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case TA_LIST_INIT_addr:
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if (data >> 31)
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{
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ta_vtx_ListInit();
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TA_NEXT_OPB = TA_NEXT_OPB_INIT;
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TA_ITP_CURRENT = TA_ISP_BASE;
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}
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return;
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case SOFTRESET_addr:
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if (data & 1)
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ta_vtx_SoftReset();
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return;
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case TA_LIST_CONT_addr:
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//a write of anything works ?
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ta_vtx_ListInit();
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break;
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case SPG_CONTROL_addr:
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case SPG_LOAD_addr:
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if (PvrReg(addr, u32) != data)
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{
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PvrReg(addr, u32) = data;
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CalculateSync();
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}
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return;
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case FB_R_CTRL_addr:
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{
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bool vclk_div_changed = (PvrReg(addr, u32) ^ data) & (1 << 23);
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PvrReg(addr, u32) = data;
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if (vclk_div_changed)
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CalculateSync();
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}
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return;
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case FB_R_SIZE_addr:
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if (PvrReg(addr, u32) != data)
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{
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PvrReg(addr, u32) = data;
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fb_dirty = false;
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check_framebuffer_write();
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}
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return;
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case TA_YUV_TEX_BASE_addr:
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PvrReg(addr, u32) = data & 0x00FFFFF8;
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YUV_init();
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return;
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case TA_YUV_TEX_CTRL_addr:
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PvrReg(addr, u32) = data;
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YUV_init();
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return;
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case FB_R_SOF1_addr:
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case FB_R_SOF2_addr:
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data &= 0x00fffffc;
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rend_swap_frame(data);
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break;
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case FB_W_SOF1_addr:
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data &= 0x01fffffc;
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rend_set_fb_write_addr(data);
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break;
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case FB_W_SOF2_addr:
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data &= 0x01fffffc;
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break;
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case PAL_RAM_CTRL_addr:
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pal_needs_update = pal_needs_update || ((data ^ PAL_RAM_CTRL) & 3) != 0;
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break;
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default:
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if (addr >= PALETTE_RAM_START_addr && PvrReg(addr,u32) != data)
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pal_needs_update = true;
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else if (addr >= FOG_TABLE_START_addr && addr <= FOG_TABLE_END_addr && PvrReg(addr,u32) != data)
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fog_needs_update = true;
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break;
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}
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PvrReg(addr, u32) = data;
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}
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void Regs_Reset(bool hard)
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{
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if (hard)
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memset(&pvr_regs[0], 0, sizeof(pvr_regs));
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ID_Reg = 0x17FD11DB;
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REVISION = 0x00000011;
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SOFTRESET = 0x00000007;
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SPG_HBLANK_INT.full = 0x031D0000;
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SPG_VBLANK_INT.full = 0x00150104;
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FPU_PARAM_CFG = 0x0007DF77;
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HALF_OFFSET = 0x00000007;
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ISP_FEED_CFG = 0x00402000;
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SDRAM_REFRESH = 0x00000020;
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SDRAM_ARB_CFG = 0x0000001F;
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SDRAM_CFG = 0x15F28997;
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SPG_HBLANK.full = 0x007E0345;
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SPG_LOAD.full = 0x01060359;
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SPG_VBLANK.full = 0x01500104;
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SPG_WIDTH.full = 0x07F1933F;
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VO_CONTROL.full = 0x00000108;
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VO_STARTX.full = 0x0000009D;
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VO_STARTY.full = 0x00150015;
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SCALER_CTL.full = 0x00000400;
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FB_BURSTCTRL = 0x00090639;
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PT_ALPHA_REF = 0x000000FF;
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}
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