209 lines
3.7 KiB
C++
209 lines
3.7 KiB
C++
#include "aica_mem.h"
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#include "aica.h"
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#include "aica_if.h"
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#include "dsp.h"
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#include "sgc_if.h"
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alignas(4) u8 aica_reg[0x8000];
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//00000000~007FFFFF @DRAM_AREA*
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//00800000~008027FF @CHANNEL_DATA
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//00802800~00802FFF @COMMON_DATA
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//00803000~00807FFF @DSP_DATA
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template<u32 sz>
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u32 ReadReg(u32 addr)
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{
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if (addr >= 0x2800 && addr < 0x2818)
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{
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if (sz == 1)
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ReadCommonReg(addr, true);
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else
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ReadCommonReg(addr, false);
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}
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else if (addr >= 0x4000 && addr < 0x4580)
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{
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if (addr & 2)
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{
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INFO_LOG(AICA, "Unaligned DSP register read @ %x", addr);
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return 0;
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}
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DEBUG_LOG(AICA, "DSP register read @ %x", addr);
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// DSP TEMP/MEMS
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u32 v;
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if (addr < 0x4500)
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{
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v = addr < 0x4400 ? dsp::state.TEMP[(addr - 0x4000) / 8] : dsp::state.MEMS[(addr - 0x4400) / 8];
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if (addr & 4)
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v = (v >> 8) & 0xffff;
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else
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v &= 0xff;
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}
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// DSP MIXS
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else
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{
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v = dsp::state.MIXS[(addr - 0x4500) / 8];
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if (addr & 4)
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v = (v >> 4) & 0xffff;
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else
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v &= 0xf;
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}
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if (sz == 1)
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{
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if (addr & 1)
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v >>= 8;
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else
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v &= 0xff;
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}
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return v;
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}
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return ReadMemArr<sz>(aica_reg, addr);
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}
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template<u32 sz>
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void WriteReg(u32 addr,u32 data)
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{
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if (addr < 0x2000)
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{
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//Channel data
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u32 chan = addr >> 7;
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u32 reg = addr & 0x7F;
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WriteMemArr<sz>(aica_reg, addr, data);
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WriteChannelReg(chan, reg, sz);
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return;
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}
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if (addr < 0x2800)
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{
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if (sz == 1)
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WriteMemArr<1>(aica_reg, addr, data);
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else
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WriteMemArr<2>(aica_reg, addr, data);
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return;
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}
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if (addr < 0x2818)
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{
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if (sz == 1)
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{
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WriteCommonReg8(addr, data);
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}
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else
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{
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WriteCommonReg8(addr, data & 0xFF);
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WriteCommonReg8(addr + 1, data >> 8);
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}
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return;
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}
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if (addr >= 0x3000)
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{
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if (addr & 2)
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{
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INFO_LOG(AICA, "Unaligned DSP register write @ %x", addr);
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return;
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}
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if (addr >= 0x4000 && addr < 0x4580)
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{
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// DSP TEMP/MEMS
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if (addr < 0x4500)
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{
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s32 &v = addr < 0x4400 ? dsp::state.TEMP[(addr - 0x4000) / 8] : dsp::state.MEMS[(addr - 0x4400) / 8];
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if (addr & 4)
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{
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if (sz == 1)
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{
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if (addr & 1)
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v = (v & 0x0000ffff) | (((s32)data << 24) >> 8);
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else
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v = (v & 0xffff00ff) | ((data & 0xff) << 8);
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}
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else
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{
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v = (v & 0xff) | (((s32)data << 16) >> 8);
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}
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}
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else
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{
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if (sz != 1 || (addr & 1) == 0)
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v = (v & ~0xff) | (data & 0xff);
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// else ignored
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}
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DEBUG_LOG(AICA, "DSP TEMP/MEMS register write<%d> @ %x = %d", sz, addr, v);
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}
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// DSP MIXS
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else
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{
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s32 &v = dsp::state.MIXS[(addr - 0x4500) / 8];
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if (addr & 4)
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{
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if (sz == 1)
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{
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if (addr & 1)
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v = (v & 0x00000fff) | (((s32)data << 24) >> 12);
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else
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v = (v & 0xfffff00f) | ((data & 0xff) << 4);
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}
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else
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{
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v = (v & 0xf) | (((s32)data << 16) >> 12);
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}
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}
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else
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{
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if (sz != 1 || (addr & 1) == 0)
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v = (v & ~0xf) | (data & 0xf);
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// else ignored
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}
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DEBUG_LOG(AICA, "DSP MIXS register write<%d> @ %x = %d", sz, addr, v);
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}
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return;
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}
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if (sz == 1)
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{
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WriteMemArr<1>(aica_reg, addr, data);
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dsp::writeProg(addr);
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}
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else
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{
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WriteMemArr<2>(aica_reg, addr, data);
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dsp::writeProg(addr);
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dsp::writeProg(addr + 1);
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}
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return;
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}
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if (sz == 1)
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WriteAicaReg<1>(addr, data);
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else
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WriteAicaReg<2>(addr, data);
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}
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//Aica reads (both sh4&arm)
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u32 libAICA_ReadReg(u32 addr, u32 size)
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{
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if (size == 1)
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return ReadReg<1>(addr & 0x7FFF);
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else
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return ReadReg<2>(addr & 0x7FFF);
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}
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void libAICA_WriteReg(u32 addr, u32 data, u32 size)
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{
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if (size == 1)
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WriteReg<1>(addr & 0x7FFF, data);
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else
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WriteReg<2>(addr & 0x7FFF, data);
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}
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void init_mem()
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{
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memset(aica_reg, 0, sizeof(aica_reg));
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aica_ram.data[ARAM_SIZE - 1] = 1;
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aica_ram.Zero();
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}
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void term_mem()
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{
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}
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