314 lines
4.8 KiB
C++
314 lines
4.8 KiB
C++
#pragma once
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#include "types.h"
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#include "oslib/oslib.h"
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#include "assert.h"
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#define SCIEB_addr 0x289C
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#define SCIPD_addr (0x289C+4)
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#define SCIRE_addr (0x289C+8)
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#define MCIEB_addr 0x28B4
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#define MCIPD_addr (0x28B4+4)
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#define MCIRE_addr (0x28B4+8)
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#define TIMER_A 0x2890
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#define TIMER_B (0x2890+4)
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#define TIMER_C (0x2890+8)
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#define REG_L (0x2D00)
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#define REG_M (0x2D04)
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#define entry(name,sz) u32 name:sz;
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struct CommonData_struct
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{
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//+0
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entry(MVOL,4);
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entry(VER,4);
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entry(DAC18B,1);
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entry(MEM8MB,1);
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entry(pad0_0,5);
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entry(Mono,1);
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u32 :16;
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//+4
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entry(RBP,12);
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entry(pad1_0,1);
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entry(RBL,2);
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entry(TESTB0,1);
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u32 :16;
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//+8
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entry(MIBUF,8);
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entry(MIEMP,1);
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entry(MIFUL ,1);
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entry(MIOVF ,1);
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entry(MOEMP ,1);
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entry(MOFUL ,1);
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entry(pad3_0,3);
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u32 :16;
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//+C
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entry(MOBUF,8);
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entry(MSLC,6);
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entry(AFSET,1);
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entry(padC_0,1);
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u32 :16;
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//+10
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entry(EG,13);
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entry(SGC,2);
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entry(LP,1);
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u32 :16;
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//+14
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entry(CA,16);
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u32 :16;
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//quite a bit padding here :)
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u8 pad_med_0[0x6C-4];
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//+80
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entry(MRWINH,4);
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entry($T,1);
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entry($TSCD,3);
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entry(pad80_0,1);
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entry(DMEA_hi,7);
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u32 :16;
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//+84
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entry(pad84_0,2);
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entry(DMEA_lo,14);
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u32 :16;
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//+88
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entry(pad88_0,2);
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entry(DRGA,13);
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entry(DGATE,1);
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u32 :16;
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//+8C
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entry(DEXE,1);
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entry(pad8C_0,1);
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entry(DLG,13);
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entry(DDIR,1);
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u32 :16;
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//+90
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entry(TIMA,8);
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entry(TACTL,3);
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entry(pad90_0,5);
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u32 :16;
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//+94
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entry(TIMB,8);
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entry(TBCTL,3);
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entry(pad94_0,5);
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u32 :16;
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//+98
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entry(TIMC,8);
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entry(TCCTL,3);
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entry(pad98_0,5);
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u32 :16;
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//+9C
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entry(SCIEB,11);
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entry(pad9C_0,5);
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u32 :16;
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//+A0
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entry(SCIPD,11);
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entry(padA0_0,5);
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u32 :16;
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//+A4
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entry(SCIRE,11);
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entry(padA4_0,5);
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u32 :16;
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//+A8
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entry(SCILV0,8);
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entry(padA8_0,8);
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u32 :16;
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//+AC
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entry(SCILV1,8);
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entry(padAC_0,8);
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u32 :16;
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//+B0
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entry(SCILV2,8);
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entry(padB0_0,8);
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u32 :16;
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//+B4
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entry(MCIEB,11);
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entry(padB4_0,5)
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u32 :16;
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//+B8
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entry(MCIPD,11);
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entry(padB8_0,5)
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u32 :16;
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//+BC
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entry(MCIRE,11);
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entry(padBC_0,5)
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u32 :16;
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//some other misc shit FAR away is here :p
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u8 pad_lot_0[0x344-4];
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//+400 , hopefully :p
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entry(AR,1);
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entry(pad400_0,7);
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entry(VREG,2);
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entry(pad400_1,6);
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u32 :16;
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//Even more
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u8 pad_lot_1[0x100-4];
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//+500 , hopefully :p
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entry(L0_r,1);
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entry(L1_r,1);
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entry(L2_r,1);
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entry(L3_r,1);
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entry(L4_r,1);
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entry(L5_r,1);
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entry(L6_r,1);
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entry(L7_r,1);
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entry(pad500_0,8);
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u32 :16;
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//+504
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entry(M0_r,1);
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entry(M1_r,1);
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entry(M2_r,1);
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entry(M3_r,1);
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entry(M4_r,1);
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entry(M5_r,1);
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entry(M6_r,1);
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entry(M7_r,1);
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entry(RP,1);
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entry(pad504_0,7);
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u32 :16;
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};
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//should be 0x15C8 in size
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struct DSPData_struct
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{
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//+0x000
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u32 COEF[128]; //15:3
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//+0x200
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u32 MADRS[64]; //15:0
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//+0x300
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u8 PAD0[0x100];
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//+0x400
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u32 MPRO[128*4]; //15:0
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//+0xC00
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u8 PAD1[0x400];
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//+0x1000
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struct
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{
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u32 l; //7:0
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u32 h; //15:0 (23:8)
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}
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TEMP[128];
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//+0x1400
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struct
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{
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u32 l; //7:0
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u32 h; //15:0 (23:8)
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}
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MEMS[32];
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//+0x1500
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struct
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{
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u32 l; //3:0
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u32 h; //15:0 (19:4)
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}
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MIXS[16];
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//+0x1580
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u32 EFREG[16]; //15:0
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//+0x15C0
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u32 EXTS[2]; //15:0
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};
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union InterruptInfo
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{
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struct
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{
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//Bit 0 (R): Requests interrupt to external interrupt input pin "INTON". (SCSI)
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entry(INTON,1);
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//Bit 1 (R): Reserved.
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entry(res_1,1);
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//Bit 2 (R): Reserved.
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entry(res_3,1);
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//Bit 3 (R): MIDI input interrupt.
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//(Interrupt request generated when input FIFO has fetched valid data. Hence, if the CPU reads FIFO data, it must read the lot once and leave the FIFO empty. When the FIFO has changed to empty status, the interrupt request is canceled automatically.)
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entry(MIDI_IN,1);
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//Bit 4 (R): DMA end interrupt
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entry(DMA_END,1);
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//Bit 5 (R/W): SCPU interrupt caused by data being written to the CPU, so only "1" can be written. (Writing "0" has no effect.) This flag can be set from either the MCPU or the SCPU.
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entry(SCPU,1);
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//Bit 6 (R): Timer A interrupt
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entry(TimerA,1);
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//Bit 7 (R): Timer B interrupt
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entry(TimerB,1);
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//Bit 8 (R): Timer C interrupt
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entry(TimerC,1);
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//Bit 9 (R): MIDI output interrupt.
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//(If the output FIFO changes to empty status, an interrupt request is generated.)
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//(If the status is no longer empty because data is written to the output FIFO, the interrupt request is canceled automatically.)
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entry(MIDI_OUT,1);
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//Bit 10 (R): Interrupt of one sample interval
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entry(SAMPLE_DONE,1);
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};
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u32 full;
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};
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extern InterruptInfo* MCIEB;
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extern InterruptInfo* MCIPD;
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extern InterruptInfo* MCIRE;
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extern InterruptInfo* SCIEB;
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extern InterruptInfo* SCIPD;
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extern InterruptInfo* SCIRE;
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#undef entry
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extern CommonData_struct* CommonData;
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extern DSPData_struct* DSPData;
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void UpdateAICA(u32 Cycles);
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void AICA_Init();
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void AICA_Term();
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//u32 ReadAicaReg(u32 reg);
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void WriteAicaReg8(u32 reg,u32 data);
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template<u32 sz>
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void WriteAicaReg(u32 reg,u32 data); |