105 lines
1.6 KiB
C++
105 lines
1.6 KiB
C++
#pragma once
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#include "types.h"
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namespace aicaarm {
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void init();
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void reset();
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void run(u32 samples);
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void enable(bool enabled);
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// Called when the arm interrupts the SH4 to make sure it has enough cycles to finish what it's doing.
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void avoidRaceCondition();
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}
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enum Arm7Reg
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{
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RN_LR = 14,
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RN_PC = 15,
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RN_CPSR = 16,
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RN_SPSR = 17,
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R13_IRQ = 18,
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R14_IRQ = 19,
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SPSR_IRQ = 20,
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R13_USR = 26,
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R14_USR = 27,
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R13_SVC = 28,
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R14_SVC = 29,
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SPSR_SVC = 30,
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R13_ABT = 31,
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R14_ABT = 32,
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SPSR_ABT = 33,
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R13_UND = 34,
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R14_UND = 35,
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SPSR_UND = 36,
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R8_FIQ = 37,
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R9_FIQ = 38,
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R10_FIQ = 39,
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R11_FIQ = 40,
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R12_FIQ = 41,
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R13_FIQ = 42,
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R14_FIQ = 43,
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SPSR_FIQ = 44,
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RN_PSR_FLAGS = 45,
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R15_ARM_NEXT = 46,
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INTR_PEND = 47,
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CYCL_CNT = 48,
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RN_SCRATCH = 49,
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RN_ARM_REG_COUNT,
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};
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typedef union
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{
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struct
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{
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u8 B0;
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u8 B1;
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u8 B2;
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u8 B3;
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} B;
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struct
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{
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u16 W0;
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u16 W1;
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} W;
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union
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{
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struct
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{
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u32 _pad0 : 28;
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u32 V : 1; //Bit 28
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u32 C : 1; //Bit 29
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u32 Z : 1; //Bit 30
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u32 N : 1; //Bit 31
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};
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struct
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{
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u32 _pad1 : 28;
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u32 NZCV : 4; //Bits [31:28]
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};
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} FLG;
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struct
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{
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u32 M : 5; //mode, PSR[4:0]
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u32 _pad0 : 1; //not used / zero
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u32 F : 1; //FIQ disable, PSR[6]
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u32 I : 1; //IRQ disable, PSR[7]
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u32 _pad1 : 20; //not used / zero
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u32 NZCV : 4; //Bits [31:28]
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} PSR;
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u32 I;
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} reg_pair;
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alignas(8) extern reg_pair arm_Reg[RN_ARM_REG_COUNT];
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#define ARM_CYCLES_PER_SAMPLE 256
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void CPUFiq();
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void CPUUpdateCPSR();
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