flycast/core/hw/sh4/interpr
Flyinghead 22dcb1ec99 sh4 ocache implementation. IC and OC address/data read/write in P4
ignore SR.RB in user mode instead of forcing it 0
add STRICT_MODE to enable ocache in interpreter
don't flush mmu table when enabling it
fix fixNan64()
2020-06-12 17:35:14 +02:00
..
sh4_fpu.cpp sh4 ocache implementation. IC and OC address/data read/write in P4 2020-06-12 17:35:14 +02:00
sh4_interpreter.cpp sh4 ocache implementation. IC and OC address/data read/write in P4 2020-06-12 17:35:14 +02:00
sh4_opcodes.cpp sh4 ocache implementation. IC and OC address/data read/write in P4 2020-06-12 17:35:14 +02:00
sh4_opcodes.h Merge branch 'androidui' 2013-12-28 22:28:50 +01:00