338 lines
6.2 KiB
C++
338 lines
6.2 KiB
C++
/*
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aica interface
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Handles RTC, Display mode reg && arm reset reg !
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arm7 is handled on a separate arm plugin now
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*/
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#include "types.h"
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#include "aica_if.h"
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#include "hw/sh4/sh4_mem.h"
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#include "hw/holly/sb.h"
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#include "types.h"
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#include "hw/holly/holly_intc.h"
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#include <time.h>
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VArray2 aica_ram;
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u32 VREG;//video reg =P
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u32 ARMRST;//arm reset reg
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u32 rtc_EN=0;
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u32 GetRTC_now()
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{
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time_t rawtime=0;
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tm timeinfo;
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timeinfo.tm_year=1998-1900;
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timeinfo.tm_mon=11-1;
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timeinfo.tm_mday=27;
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timeinfo.tm_hour=0;
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timeinfo.tm_min=0;
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timeinfo.tm_sec=0;
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rawtime=mktime( &timeinfo );
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rawtime=time (0)-rawtime;//get delta of time since the known dc date
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time_t temp=time(0);
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timeinfo=*localtime(&temp);
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if (timeinfo.tm_isdst)
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rawtime+=24*3600;//add an hour if dst (maybe rtc has a reg for that ? *watch* and add it if yes :)
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u32 RTC=0x5bfc8900 + (u32)rawtime;// add delta to known dc time
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return RTC;
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}
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u32 ReadMem_aica_rtc(u32 addr,u32 sz)
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{
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//settings.dreamcast.RTC=GetRTC_now();
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switch( addr & 0xFF )
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{
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case 0:
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return settings.dreamcast.RTC>>16;
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case 4:
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return settings.dreamcast.RTC &0xFFFF;
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case 8:
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return 0;
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}
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printf("ReadMem_aica_rtc : invalid address\n");
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return 0;
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}
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void WriteMem_aica_rtc(u32 addr,u32 data,u32 sz)
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{
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switch( addr & 0xFF )
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{
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case 0:
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if (rtc_EN)
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{
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settings.dreamcast.RTC&=0xFFFF;
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settings.dreamcast.RTC|=(data&0xFFFF)<<16;
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rtc_EN=0;
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SaveSettings();
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}
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return;
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case 4:
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if (rtc_EN)
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{
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settings.dreamcast.RTC&=0xFFFF0000;
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settings.dreamcast.RTC|= data&0xFFFF;
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//TODO: Clean the internal timer ?
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}
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return;
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case 8:
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rtc_EN=data&1;
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return;
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}
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return;
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}
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u32 ReadMem_aica_reg(u32 addr,u32 sz)
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{
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addr&=0x7FFF;
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if (sz==1)
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{
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if (addr==0x2C01)
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{
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return VREG;
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}
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else if (addr==0x2C00)
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{
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return ARMRST;
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}
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else
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{
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return libAICA_ReadReg(addr, sz);
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}
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}
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else
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{
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if (addr==0x2C00)
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{
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return (VREG<<8) | ARMRST;
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}
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else
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{
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return libAICA_ReadReg(addr, sz);
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}
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}
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}
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void ArmSetRST()
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{
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ARMRST&=1;
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libARM_SetResetState(ARMRST);
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}
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void WriteMem_aica_reg(u32 addr,u32 data,u32 sz)
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{
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addr&=0x7FFF;
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if (sz==1)
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{
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if (addr==0x2C01)
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{
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VREG=data;
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printf("VREG = %02X\n",VREG);
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}
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else if (addr==0x2C00)
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{
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ARMRST=data;
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printf("ARMRST = %02X\n",ARMRST);
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ArmSetRST();
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}
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else
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{
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libAICA_WriteReg(addr,data,sz);
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}
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}
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else
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{
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if (addr==0x2C00)
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{
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VREG=(data>>8)&0xFF;
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ARMRST=data&0xFF;
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printf("VREG = %02X ARMRST %02X\n",VREG,ARMRST);
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ArmSetRST();
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}
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else
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{
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libAICA_WriteReg(addr,data,sz);
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}
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}
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}
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//Init/res/term
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void aica_Init()
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{
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//mmnnn ? gotta fill it w/ something
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}
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void aica_Reset(bool Manual)
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{
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if (!Manual)
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{
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aica_ram.Zero();
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}
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}
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void aica_Term()
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{
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}
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s32 aica_pending_dma = 0;
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void aica_periodical(u32 cycl)
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{
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if (aica_pending_dma > 0)
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{
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verify(SB_ADST==1);
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cycl = (aica_pending_dma <= 0) ? 0 : cycl;
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aica_pending_dma-=cycl;
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if (aica_pending_dma <= 0)
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{
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//log("%u %d\n",cycl,(s32)aica_pending_dma);
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asic_RaiseInterrupt(holly_SPU_DMA);
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aica_pending_dma = 0;
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SB_ADST=0;
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}
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}
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}
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void Write_SB_ADST(u32 addr, u32 data)
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{
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//0x005F7800 SB_ADSTAG RW AICA:G2-DMA G2 start address
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//0x005F7804 SB_ADSTAR RW AICA:G2-DMA system memory start address
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//0x005F7808 SB_ADLEN RW AICA:G2-DMA length
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//0x005F780C SB_ADDIR RW AICA:G2-DMA direction
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//0x005F7810 SB_ADTSEL RW AICA:G2-DMA trigger select
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//0x005F7814 SB_ADEN RW AICA:G2-DMA enable
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//0x005F7818 SB_ADST RW AICA:G2-DMA start
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//0x005F781C SB_ADSUSP RW AICA:G2-DMA suspend
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if (data&1)
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{
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if (SB_ADEN&1)
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{
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u32 src=SB_ADSTAR;
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u32 dst=SB_ADSTAG;
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u32 len=SB_ADLEN & 0x7FFFFFFF;
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u32 total_bytes=0;
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if ((SB_ADDIR&1)==1)
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{
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//swap direction
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u32 tmp=src;
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src=dst;
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dst=tmp;
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printf("**AICA DMA : SB_ADDIR==1: Not sure this works, please report if broken/missing sound or crash\n**");
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}
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WriteMemBlock_nommu_dma(dst,src,len);
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/*
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for (u32 i=0;i<len;i+=4)
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{
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u32 data=ReadMem32_nommu(src+i);
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WriteMem32_nommu(dst+i,data);
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}
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*/
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if (SB_ADLEN & 0x80000000)
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SB_ADEN=1;//
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else
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SB_ADEN=0;//
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SB_ADSTAR+=len;
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SB_ADSTAG+=len;
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total_bytes+=len;
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SB_ADST = settings.aica.DelayInterrupt ? 1 : 0x00000000;//dma done
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SB_ADLEN = 0x00000000;
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aica_pending_dma = ((total_bytes * 200000000) / 65536) + 1;
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if (!settings.aica.DelayInterrupt)
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asic_RaiseInterruptWait(holly_SPU_DMA);
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}
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}
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}
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void Write_SB_E1ST(u32 addr, u32 data)
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{
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//0x005F7800 SB_ADSTAG RW AICA:G2-DMA G2 start address
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//0x005F7804 SB_ADSTAR RW AICA:G2-DMA system memory start address
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//0x005F7808 SB_ADLEN RW AICA:G2-DMA length
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//0x005F780C SB_ADDIR RW AICA:G2-DMA direction
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//0x005F7810 SB_ADTSEL RW AICA:G2-DMA trigger select
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//0x005F7814 SB_ADEN RW AICA:G2-DMA enable
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//0x005F7818 SB_ADST RW AICA:G2-DMA start
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//0x005F781C SB_ADSUSP RW AICA:G2-DMA suspend
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if (data&1)
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{
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if (SB_E1EN&1)
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{
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u32 src=SB_E1STAR;
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u32 dst=SB_E1STAG;
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u32 len=SB_E1LEN & 0x7FFFFFFF;
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if (SB_E1DIR==1)
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{
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u32 t=src;
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src=dst;
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dst=t;
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printf("G2-EXT1 DMA : SB_E1DIR==1 DMA Read to 0x%X from 0x%X %d bytes\n",dst,src,len);
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}
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else
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printf("G2-EXT1 DMA : SB_E1DIR==0:DMA Write to 0x%X from 0x%X %d bytes\n",dst,src,len);
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WriteMemBlock_nommu_dma(dst,src,len);
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/*
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for (u32 i=0;i<len;i+=4)
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{
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u32 data=ReadMem32_nommu(src+i);
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WriteMem32_nommu(dst+i,data);
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}*/
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if (SB_E1LEN & 0x80000000)
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SB_E1EN=1;//
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else
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SB_E1EN=0;//
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SB_E1STAR+=len;
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SB_E1STAG+=len;
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SB_E1ST = 0x00000000;//dma done
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SB_E1LEN = 0x00000000;
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asic_RaiseInterruptWait(holly_EXT_DMA1);
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}
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}
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}
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void aica_sb_Init()
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{
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//NRM
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//6
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sb_rio_register(SB_ADST_addr,RIO_WF,0,&Write_SB_ADST);
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//sb_regs[((SB_ADST_addr-SB_BASE)>>2)].flags=REG_32BIT_READWRITE | REG_READ_DATA;
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//sb_regs[((SB_ADST_addr-SB_BASE)>>2)].writeFunction=Write_SB_ADST;
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//I really need to implement G2 dma (and rest dmas actually) properly
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//THIS IS NOT AICA, its G2-EXT (BBA)
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sb_rio_register(SB_E1ST_addr,RIO_WF,0,&Write_SB_E1ST);
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//sb_regs[((SB_E1ST_addr-SB_BASE)>>2)].flags=REG_32BIT_READWRITE | REG_READ_DATA;
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//sb_regs[((SB_E1ST_addr-SB_BASE)>>2)].writeFunction=Write_SB_E1ST;
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}
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void aica_sb_Reset(bool Manual)
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{
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}
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void aica_sb_Term()
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{
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}
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