771 lines
17 KiB
C++
771 lines
17 KiB
C++
#include "mmu.h"
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#include "hw/sh4/sh4_if.h"
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#include "hw/sh4/sh4_interrupts.h"
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#include "hw/sh4/sh4_core.h"
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TLB_Entry UTLB[64];
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TLB_Entry ITLB[4];
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u32 ITLB_LRU_USE[64];
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//SQ fast remap , mainly hackish , assumes 1MB pages
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//max 64MB can be remapped on SQ
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// Used when FullMMU is off
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u32 sq_remap[64];
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#if defined(NO_MMU)
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//Sync memory mapping to MMU , suspend compiled blocks if needed.entry is a UTLB entry # , -1 is for full sync
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bool UTLB_Sync(u32 entry)
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{
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if ((UTLB[entry].Address.VPN & (0xFC000000 >> 10)) == (0xE0000000 >> 10))
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{
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u32 vpn_sq = ((UTLB[entry].Address.VPN & 0x7FFFF) >> 10) & 0x3F;//upper bits are always known [0xE0/E1/E2/E3]
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sq_remap[vpn_sq] = UTLB[entry].Data.PPN << 10;
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INFO_LOG(SH4, "SQ remap %d : 0x%X to 0x%X", entry, UTLB[entry].Address.VPN << 10, UTLB[entry].Data.PPN << 10);
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}
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else
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{
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INFO_LOG(SH4, "MEM remap %d : 0x%X to 0x%X", entry, UTLB[entry].Address.VPN << 10, UTLB[entry].Data.PPN << 10);
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}
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return true;
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}
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//Sync memory mapping to MMU, suspend compiled blocks if needed.entry is a ITLB entry # , -1 is for full sync
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void ITLB_Sync(u32 entry)
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{
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INFO_LOG(SH4, "ITLB MEM remap %d : 0x%X to 0x%X",entry,ITLB[entry].Address.VPN<<10,ITLB[entry].Data.PPN<<10);
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}
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void mmu_set_state()
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{
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}
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void MMU_init()
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{
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}
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void MMU_reset()
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{
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memset(UTLB,0,sizeof(UTLB));
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memset(ITLB,0,sizeof(ITLB));
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}
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void MMU_term()
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{
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}
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#else
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/*
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MMU support code
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This is mostly hacked-on as the core was never meant to have mmu support
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There are two modes, one with 'full' mmu emulation (for wince/bleem/wtfever)
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and a fast-hack mode for 1mb sqremaps (for katana)
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defining NO_MMU disables the full mmu emulation
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*/
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#include "mmu.h"
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#include "mmu_impl.h"
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#include "hw/sh4/sh4_if.h"
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#include "ccn.h"
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#include "hw/sh4/sh4_interrupts.h"
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#include "hw/sh4/sh4_if.h"
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#include "hw/sh4/sh4_mem.h"
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#include "hw/mem/_vmem.h"
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template<bool internal = false>
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u32 mmu_full_lookup(u32 va, u32& idx, u32& rv);
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//#define TRACE_WINCE_SYSCALLS
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#ifdef TRACE_WINCE_SYSCALLS
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#include "wince.h"
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u32 unresolved_ascii_string;
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u32 unresolved_unicode_string;
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#endif
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#define printf_mmu(...) DEBUG_LOG(SH4, __VA_ARGS__)
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extern const u32 mmu_mask[4] =
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{
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((0xFFFFFFFF) >> 10) << 10, //1 kb page
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((0xFFFFFFFF) >> 12) << 12, //4 kb page
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((0xFFFFFFFF) >> 16) << 16, //64 kb page
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((0xFFFFFFFF) >> 20) << 20 //1 MB page
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};
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extern const u32 fast_reg_lut[8] =
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{
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0, 0, 0, 0 //P0-U0
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, 1 //P1
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, 1 //P2
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, 0 //P3
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, 1 //P4
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};
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const u32 ITLB_LRU_OR[4] =
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{
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0x00,//000xxx
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0x20,//1xx00x
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0x14,//x1x1x0
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0x0B,//xx1x11
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};
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const u32 ITLB_LRU_AND[4] =
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{
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0x07,//000xxx
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0x39,//1xx00x
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0x3E,//x1x1x0
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0x3F,//xx1x11
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};
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#ifndef FAST_MMU
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//sync mem mapping to mmu , suspend compiled blocks if needed.entry is a UTLB entry # , -1 is for full sync
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bool UTLB_Sync(u32 entry)
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{
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printf_mmu("UTLB MEM remap %d : 0x%X to 0x%X : %d asid %d size %d", entry, UTLB[entry].Address.VPN << 10, UTLB[entry].Data.PPN << 10, UTLB[entry].Data.V,
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UTLB[entry].Address.ASID, UTLB[entry].Data.SZ0 + UTLB[entry].Data.SZ1 * 2);
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if (UTLB[entry].Data.V == 0)
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return true;
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if ((UTLB[entry].Address.VPN & (0xFC000000 >> 10)) == (0xE0000000 >> 10))
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{
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// Used when FullMMU is off
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u32 vpn_sq = ((UTLB[entry].Address.VPN & 0x7FFFF) >> 10) & 0x3F;//upper bits are always known [0xE0/E1/E2/E3]
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sq_remap[vpn_sq] = UTLB[entry].Data.PPN << 10;
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return true;
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}
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else
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{
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return false;
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}
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}
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//sync mem mapping to mmu , suspend compiled blocks if needed.entry is a ITLB entry # , -1 is for full sync
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void ITLB_Sync(u32 entry)
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{
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printf_mmu("ITLB MEM remap %d : 0x%X to 0x%X : %d", entry, ITLB[entry].Address.VPN << 10, ITLB[entry].Data.PPN << 10, ITLB[entry].Data.V);
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}
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#endif
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void RaiseException(u32 expEvnt, u32 callVect) {
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#if !defined(NO_MMU)
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SH4ThrownException ex = { next_pc - 2, expEvnt, callVect };
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throw ex;
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#else
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msgboxf("Can't raise exceptions yet", MBX_ICONERROR);
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#endif
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}
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void mmu_raise_exception(u32 mmu_error, u32 address, u32 am)
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{
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printf_mmu("mmu_raise_exception -> pc = 0x%X : ", next_pc);
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CCN_TEA = address;
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CCN_PTEH.VPN = address >> 10;
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switch (mmu_error)
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{
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//No error
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case MMU_ERROR_NONE:
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die("Error : mmu_raise_exception(MMU_ERROR_NONE)");
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break;
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//TLB miss
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case MMU_ERROR_TLB_MISS:
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printf_mmu("MMU_ERROR_UTLB_MISS 0x%X, handled", address);
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if (am == MMU_TT_DWRITE) //WTLBMISS - Write Data TLB Miss Exception
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RaiseException(0x60, 0x400);
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else if (am == MMU_TT_DREAD) //RTLBMISS - Read Data TLB Miss Exception
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RaiseException(0x40, 0x400);
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else //ITLBMISS - Instruction TLB Miss Exception
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RaiseException(0x40, 0x400);
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return;
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//TLB Multihit
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case MMU_ERROR_TLB_MHIT:
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INFO_LOG(SH4, "MMU_ERROR_TLB_MHIT @ 0x%X", address);
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break;
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//Mem is read/write protected (depends on translation type)
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case MMU_ERROR_PROTECTED:
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printf_mmu("MMU_ERROR_PROTECTED 0x%X, handled", address);
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if (am == MMU_TT_DWRITE) //WRITEPROT - Write Data TLB Protection Violation Exception
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RaiseException(0xC0, 0x100);
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else if (am == MMU_TT_DREAD) //READPROT - Data TLB Protection Violation Exception
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RaiseException(0xA0, 0x100);
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else //READPROT - Instr TLB Protection Violation Exception
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RaiseException(0xA0, 0x100);
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return;
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//Mem is write protected , firstwrite
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case MMU_ERROR_FIRSTWRITE:
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printf_mmu("MMU_ERROR_FIRSTWRITE");
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verify(am == MMU_TT_DWRITE);
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//FIRSTWRITE - Initial Page Write Exception
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RaiseException(0x80, 0x100);
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return;
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//data read/write missasligned
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case MMU_ERROR_BADADDR:
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if (am == MMU_TT_DWRITE) //WADDERR - Write Data Address Error
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{
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printf_mmu("MMU_ERROR_BADADDR(dw) 0x%X", address);
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RaiseException(0x100, 0x100);
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}
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else if (am == MMU_TT_DREAD) //RADDERR - Read Data Address Error
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{
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printf_mmu("MMU_ERROR_BADADDR(dr) 0x%X", address);
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RaiseException(0xE0, 0x100);
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}
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else //IADDERR - Instruction Address Error
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{
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#ifdef TRACE_WINCE_SYSCALLS
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if (!print_wince_syscall(address))
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#endif
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printf_mmu("MMU_ERROR_BADADDR(i) 0x%X", address);
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RaiseException(0xE0, 0x100);
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}
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return;
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//Can't Execute
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case MMU_ERROR_EXECPROT:
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INFO_LOG(SH4, "MMU_ERROR_EXECPROT 0x%X", address);
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//EXECPROT - Instruction TLB Protection Violation Exception
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RaiseException(0xA0, 0x100);
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return;
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}
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die("Unknown mmu_error");
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}
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void DoMMUException(u32 address, u32 mmu_error, u32 access_type)
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{
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printf_mmu("DoMMUException -> pc = 0x%X : %d ", next_pc, access_type);
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CCN_TEA = address;
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CCN_PTEH.VPN = address >> 10;
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switch (mmu_error)
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{
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//No error
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case MMU_ERROR_NONE:
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die("Error : mmu_raise_exception(MMU_ERROR_NONE)");
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break;
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//TLB miss
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case MMU_ERROR_TLB_MISS:
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printf_mmu("MMU_ERROR_UTLB_MISS 0x%X, handled", address);
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if (access_type == MMU_TT_DWRITE) //WTLBMISS - Write Data TLB Miss Exception
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Do_Exception(next_pc, 0x60, 0x400);
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else if (access_type == MMU_TT_DREAD) //RTLBMISS - Read Data TLB Miss Exception
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Do_Exception(next_pc, 0x40, 0x400);
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else //ITLBMISS - Instruction TLB Miss Exception
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Do_Exception(next_pc, 0x40, 0x400);
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return;
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break;
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//TLB Multihit
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case MMU_ERROR_TLB_MHIT:
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INFO_LOG(SH4, "MMU_ERROR_TLB_MHIT @ 0x%X", address);
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break;
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//Mem is read/write protected (depends on translation type)
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case MMU_ERROR_PROTECTED:
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printf_mmu("MMU_ERROR_PROTECTED 0x%X, handled", address);
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if (access_type == MMU_TT_DWRITE) //WRITEPROT - Write Data TLB Protection Violation Exception
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Do_Exception(next_pc, 0xC0, 0x100);
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else if (access_type == MMU_TT_DREAD) //READPROT - Data TLB Protection Violation Exception
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Do_Exception(next_pc, 0xA0, 0x100);
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else
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{
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verify(false);
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}
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return;
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break;
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//Mem is write protected , firstwrite
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case MMU_ERROR_FIRSTWRITE:
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printf_mmu("MMU_ERROR_FIRSTWRITE");
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verify(access_type == MMU_TT_DWRITE);
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//FIRSTWRITE - Initial Page Write Exception
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Do_Exception(next_pc, 0x80, 0x100);
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return;
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break;
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//data read/write missasligned
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case MMU_ERROR_BADADDR:
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if (access_type == MMU_TT_DWRITE) //WADDERR - Write Data Address Error
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Do_Exception(next_pc, 0x100, 0x100);
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else if (access_type == MMU_TT_DREAD) //RADDERR - Read Data Address Error
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Do_Exception(next_pc, 0xE0, 0x100);
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else //IADDERR - Instruction Address Error
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{
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#ifdef TRACE_WINCE_SYSCALLS
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if (!print_wince_syscall(address))
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#endif
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printf_mmu("MMU_ERROR_BADADDR(i) 0x%X", address);
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Do_Exception(next_pc, 0xE0, 0x100);
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return;
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}
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printf_mmu("MMU_ERROR_BADADDR(d) 0x%X, handled", address);
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return;
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break;
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//Can't Execute
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case MMU_ERROR_EXECPROT:
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INFO_LOG(SH4, "MMU_ERROR_EXECPROT 0x%X", address);
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//EXECPROT - Instruction TLB Protection Violation Exception
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Do_Exception(next_pc, 0xA0, 0x100);
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return;
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break;
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}
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die("Unknown mmu_error");
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}
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bool mmu_match(u32 va, CCN_PTEH_type Address, CCN_PTEL_type Data)
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{
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if (Data.V == 0)
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return false;
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u32 sz = Data.SZ1 * 2 + Data.SZ0;
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u32 mask = mmu_mask[sz];
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if ((((Address.VPN << 10)&mask) == (va&mask)))
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{
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bool asid_match = (Data.SH == 0) && ((sr.MD == 0) || (CCN_MMUCR.SV == 0));
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if ((asid_match == false) || (Address.ASID == CCN_PTEH.ASID))
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{
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return true;
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}
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}
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return false;
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}
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#ifndef FAST_MMU
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//Do a full lookup on the UTLB entry's
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template<bool internal>
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u32 mmu_full_lookup(u32 va, const TLB_Entry** tlb_entry_ret, u32& rv)
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{
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if (!internal)
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{
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CCN_MMUCR.URC++;
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if (CCN_MMUCR.URB == CCN_MMUCR.URC)
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CCN_MMUCR.URC = 0;
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}
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u32 entry = -1;
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u32 nom = 0;
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for (u32 i = 0; i<64; i++)
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{
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//verify(sz!=0);
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TLB_Entry *tlb_entry = &UTLB[i];
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if (mmu_match(va, tlb_entry->Address, tlb_entry->Data))
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{
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entry = i;
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nom++;
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u32 sz = tlb_entry->Data.SZ1 * 2 + tlb_entry->Data.SZ0;
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u32 mask = mmu_mask[sz];
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//VPN->PPN | low bits
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rv = ((tlb_entry->Data.PPN << 10) & mask) | (va & (~mask));
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}
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}
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if (nom != 1)
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{
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if (nom)
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{
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return MMU_ERROR_TLB_MHIT;
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}
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else
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{
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return MMU_ERROR_TLB_MISS;
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}
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}
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*tlb_entry_ret = &UTLB[entry];
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return MMU_ERROR_NONE;
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}
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#endif
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//Simple QACR translation for mmu (when AT is off)
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u32 mmu_QACR_SQ(u32 va)
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{
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u32 QACR;
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//default to sq 0
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QACR = CCN_QACR_TR[0];
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//sq1 ? if so use QACR1
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if (va & 0x20)
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QACR = CCN_QACR_TR[1];
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va &= ~0x1f;
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return QACR + va;
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}
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#ifndef FAST_MMU
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template<u32 translation_type>
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u32 mmu_full_SQ(u32 va, u32& rv)
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{
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if ((va & 3) || (CCN_MMUCR.SQMD == 1 && sr.MD == 0))
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{
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//here, or after ?
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return MMU_ERROR_BADADDR;
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}
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if (CCN_MMUCR.AT)
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{
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//Address=Dest&0xFFFFFFE0;
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const TLB_Entry *entry;
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u32 lookup = mmu_full_lookup(va, &entry, rv);
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rv &= ~31;//lower 5 bits are forced to 0
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if (lookup != MMU_ERROR_NONE)
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return lookup;
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u32 md = entry->Data.PR >> 1;
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//Priv mode protection
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if ((md == 0) && sr.MD == 0)
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{
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return MMU_ERROR_PROTECTED;
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}
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//Write Protection (Lock or FW)
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if (translation_type == MMU_TT_DWRITE)
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{
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if ((entry->Data.PR & 1) == 0)
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return MMU_ERROR_PROTECTED;
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else if (entry->Data.D == 0)
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return MMU_ERROR_FIRSTWRITE;
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}
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}
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else
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{
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rv = mmu_QACR_SQ(va);
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}
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return MMU_ERROR_NONE;
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}
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template u32 mmu_full_SQ<MMU_TT_DREAD>(u32 va, u32& rv);
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template u32 mmu_full_SQ<MMU_TT_DWRITE>(u32 va, u32& rv);
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template<u32 translation_type, typename T>
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u32 mmu_data_translation(u32 va, u32& rv)
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{
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if (va & (sizeof(T) - 1))
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return MMU_ERROR_BADADDR;
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if (translation_type == MMU_TT_DWRITE)
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{
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if ((va & 0xFC000000) == 0xE0000000)
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{
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u32 lookup = mmu_full_SQ<translation_type>(va, rv);
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if (lookup != MMU_ERROR_NONE)
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return lookup;
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rv = va; //SQ writes are not translated, only write backs are.
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return MMU_ERROR_NONE;
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}
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}
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if ((sr.MD == 0) && (va & 0x80000000) != 0)
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{
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//if on kernel, and not SQ addr -> error
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return MMU_ERROR_BADADDR;
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}
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if (sr.MD == 1 && ((va & 0xFC000000) == 0x7C000000))
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{
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// 7C000000 to 7FFFFFFF in P0 not translated in supervisor mode
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rv = va;
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return MMU_ERROR_NONE;
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}
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if (fast_reg_lut[va >> 29] != 0)
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{
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// P1, P2 and P4 aren't translated
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rv = va;
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return MMU_ERROR_NONE;
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}
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const TLB_Entry *entry;
|
|
u32 lookup = mmu_full_lookup(va, &entry, rv);
|
|
|
|
if (lookup != MMU_ERROR_NONE)
|
|
return lookup;
|
|
|
|
#ifdef TRACE_WINCE_SYSCALLS
|
|
if (unresolved_unicode_string != 0)
|
|
{
|
|
if (va == unresolved_unicode_string)
|
|
{
|
|
unresolved_unicode_string = 0;
|
|
INFO_LOG(SH4, "RESOLVED %s", get_unicode_string(va).c_str());
|
|
}
|
|
}
|
|
#endif
|
|
|
|
u32 md = entry->Data.PR >> 1;
|
|
|
|
//0X & User mode-> protection violation
|
|
//Priv mode protection
|
|
if ((md == 0) && sr.MD == 0)
|
|
{
|
|
return MMU_ERROR_PROTECTED;
|
|
}
|
|
|
|
//X0 -> read olny
|
|
//X1 -> read/write , can be FW
|
|
|
|
//Write Protection (Lock or FW)
|
|
if (translation_type == MMU_TT_DWRITE)
|
|
{
|
|
if ((entry->Data.PR & 1) == 0)
|
|
return MMU_ERROR_PROTECTED;
|
|
else if (entry->Data.D == 0)
|
|
return MMU_ERROR_FIRSTWRITE;
|
|
}
|
|
return MMU_ERROR_NONE;
|
|
}
|
|
template u32 mmu_data_translation<MMU_TT_DREAD, u8>(u32 va, u32& rv);
|
|
template u32 mmu_data_translation<MMU_TT_DREAD, u16>(u32 va, u32& rv);
|
|
template u32 mmu_data_translation<MMU_TT_DREAD, u32>(u32 va, u32& rv);
|
|
template u32 mmu_data_translation<MMU_TT_DREAD, u64>(u32 va, u32& rv);
|
|
|
|
template u32 mmu_data_translation<MMU_TT_DWRITE, u8>(u32 va, u32& rv);
|
|
template u32 mmu_data_translation<MMU_TT_DWRITE, u16>(u32 va, u32& rv);
|
|
template u32 mmu_data_translation<MMU_TT_DWRITE, u32>(u32 va, u32& rv);
|
|
template u32 mmu_data_translation<MMU_TT_DWRITE, u64>(u32 va, u32& rv);
|
|
|
|
u32 mmu_instruction_translation(u32 va, u32& rv)
|
|
{
|
|
if (va & 1)
|
|
{
|
|
return MMU_ERROR_BADADDR;
|
|
}
|
|
if ((sr.MD == 0) && (va & 0x80000000) != 0)
|
|
{
|
|
//if SQ disabled , or if if SQ on but out of SQ mem then BAD ADDR ;)
|
|
if (va >= 0xE0000000)
|
|
return MMU_ERROR_BADADDR;
|
|
}
|
|
|
|
if ((CCN_MMUCR.AT == 0) || (fast_reg_lut[va >> 29] != 0))
|
|
{
|
|
rv = va;
|
|
return MMU_ERROR_NONE;
|
|
}
|
|
|
|
const TLB_Entry *entry;
|
|
u32 lookup = mmu_instruction_lookup(va, &entry, rv);
|
|
if (lookup != MMU_ERROR_NONE)
|
|
return lookup;
|
|
|
|
u32 md = entry->Data.PR >> 1;
|
|
|
|
//0X & User mode-> protection violation
|
|
//Priv mode protection
|
|
if (md == 0 && sr.MD == 0)
|
|
return MMU_ERROR_PROTECTED;
|
|
|
|
return MMU_ERROR_NONE;
|
|
}
|
|
#endif
|
|
|
|
u32 mmu_instruction_lookup(u32 va, const TLB_Entry** tlb_entry_ret, u32& rv)
|
|
{
|
|
bool mmach = false;
|
|
retry_ITLB_Match:
|
|
u32 entry = 4;
|
|
u32 nom = 0;
|
|
for (u32 i = 0; i<4; i++)
|
|
{
|
|
if (ITLB[i].Data.V == 0)
|
|
continue;
|
|
u32 sz = ITLB[i].Data.SZ1 * 2 + ITLB[i].Data.SZ0;
|
|
u32 mask = mmu_mask[sz];
|
|
|
|
if ((((ITLB[i].Address.VPN << 10)&mask) == (va&mask)))
|
|
{
|
|
bool asid_match = (ITLB[i].Data.SH == 0) && ((sr.MD == 0) || (CCN_MMUCR.SV == 0));
|
|
|
|
if ((asid_match == false) || (ITLB[i].Address.ASID == CCN_PTEH.ASID))
|
|
{
|
|
//verify(sz!=0);
|
|
entry = i;
|
|
nom++;
|
|
//VPN->PPN | low bits
|
|
rv = ((ITLB[i].Data.PPN << 10)&mask) | (va&(~mask));
|
|
}
|
|
}
|
|
}
|
|
|
|
if (entry == 4)
|
|
{
|
|
verify(mmach == false);
|
|
const TLB_Entry *tlb_entry;
|
|
u32 lookup = mmu_full_lookup(va, &tlb_entry, rv);
|
|
|
|
if (lookup != MMU_ERROR_NONE)
|
|
return lookup;
|
|
|
|
u32 replace_index = ITLB_LRU_USE[CCN_MMUCR.LRUI];
|
|
verify(replace_index != 0xFFFFFFFF);
|
|
ITLB[replace_index] = *tlb_entry;
|
|
entry = replace_index;
|
|
ITLB_Sync(entry);
|
|
mmach = true;
|
|
goto retry_ITLB_Match;
|
|
}
|
|
else if (nom != 1)
|
|
{
|
|
if (nom)
|
|
{
|
|
return MMU_ERROR_TLB_MHIT;
|
|
}
|
|
else
|
|
{
|
|
return MMU_ERROR_TLB_MISS;
|
|
}
|
|
}
|
|
|
|
CCN_MMUCR.LRUI &= ITLB_LRU_AND[entry];
|
|
CCN_MMUCR.LRUI |= ITLB_LRU_OR[entry];
|
|
*tlb_entry_ret = &ITLB[entry];
|
|
|
|
return MMU_ERROR_NONE;
|
|
}
|
|
|
|
void mmu_set_state()
|
|
{
|
|
if (CCN_MMUCR.AT == 1 && settings.dreamcast.FullMMU)
|
|
{
|
|
NOTICE_LOG(SH4, "Enabling Full MMU support");
|
|
_vmem_enable_mmu(true);
|
|
}
|
|
else
|
|
_vmem_enable_mmu(false);
|
|
|
|
SetMemoryHandlers();
|
|
}
|
|
|
|
void MMU_init()
|
|
{
|
|
memset(ITLB_LRU_USE, 0xFF, sizeof(ITLB_LRU_USE));
|
|
for (u32 e = 0; e<4; e++)
|
|
{
|
|
u32 match_key = ((~ITLB_LRU_AND[e]) & 0x3F);
|
|
u32 match_mask = match_key | ITLB_LRU_OR[e];
|
|
for (u32 i = 0; i<64; i++)
|
|
{
|
|
if ((i & match_mask) == match_key)
|
|
{
|
|
verify(ITLB_LRU_USE[i] == 0xFFFFFFFF);
|
|
ITLB_LRU_USE[i] = e;
|
|
}
|
|
}
|
|
}
|
|
mmu_set_state();
|
|
}
|
|
|
|
|
|
void MMU_reset()
|
|
{
|
|
memset(UTLB, 0, sizeof(UTLB));
|
|
memset(ITLB, 0, sizeof(ITLB));
|
|
mmu_set_state();
|
|
mmu_flush_table();
|
|
}
|
|
|
|
void MMU_term()
|
|
{
|
|
}
|
|
|
|
#ifndef FAST_MMU
|
|
void mmu_flush_table()
|
|
{
|
|
//printf("MMU tables flushed\n");
|
|
|
|
ITLB[0].Data.V = 0;
|
|
ITLB[1].Data.V = 0;
|
|
ITLB[2].Data.V = 0;
|
|
ITLB[3].Data.V = 0;
|
|
|
|
for (u32 i = 0; i < 64; i++)
|
|
UTLB[i].Data.V = 0;
|
|
}
|
|
#endif
|
|
|
|
template<typename T>
|
|
T DYNACALL mmu_ReadMem(u32 adr)
|
|
{
|
|
u32 addr;
|
|
u32 rv = mmu_data_translation<MMU_TT_DREAD, T>(adr, addr);
|
|
if (rv != MMU_ERROR_NONE)
|
|
mmu_raise_exception(rv, adr, MMU_TT_DREAD);
|
|
return _vmem_readt<T, T>(addr);
|
|
}
|
|
template u8 mmu_ReadMem(u32 adr);
|
|
template u16 mmu_ReadMem(u32 adr);
|
|
template u32 mmu_ReadMem(u32 adr);
|
|
template u64 mmu_ReadMem(u32 adr);
|
|
|
|
u16 DYNACALL mmu_IReadMem16(u32 vaddr)
|
|
{
|
|
u32 addr;
|
|
u32 rv = mmu_instruction_translation(vaddr, addr);
|
|
if (rv != MMU_ERROR_NONE)
|
|
mmu_raise_exception(rv, vaddr, MMU_TT_IREAD);
|
|
return _vmem_ReadMem16(addr);
|
|
}
|
|
|
|
template<typename T>
|
|
void DYNACALL mmu_WriteMem(u32 adr, T data)
|
|
{
|
|
u32 addr;
|
|
u32 rv = mmu_data_translation<MMU_TT_DWRITE, T>(adr, addr);
|
|
if (rv != MMU_ERROR_NONE)
|
|
mmu_raise_exception(rv, adr, MMU_TT_DWRITE);
|
|
_vmem_writet<T>(addr, data);
|
|
}
|
|
template void mmu_WriteMem(u32 adr, u8 data);
|
|
template void mmu_WriteMem(u32 adr, u16 data);
|
|
template void mmu_WriteMem(u32 adr, u32 data);
|
|
template void mmu_WriteMem(u32 adr, u64 data);
|
|
|
|
bool mmu_TranslateSQW(u32 adr, u32* out)
|
|
{
|
|
if (!settings.dreamcast.FullMMU)
|
|
{
|
|
//This will only work for 1 mb pages .. hopefully nothing else is used
|
|
//*FIXME* to work for all page sizes ?
|
|
|
|
*out = sq_remap[(adr >> 20) & 0x3F] | (adr & 0xFFFE0);
|
|
}
|
|
else
|
|
{
|
|
u32 addr;
|
|
u32 tv = mmu_full_SQ<MMU_TT_DREAD>(adr, addr);
|
|
if (tv != MMU_ERROR_NONE)
|
|
{
|
|
mmu_raise_exception(tv, adr, MMU_TT_DREAD);
|
|
return false;
|
|
}
|
|
|
|
*out = addr;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
#endif
|