77 lines
1.6 KiB
C++
77 lines
1.6 KiB
C++
/*
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SH4/mod/intc
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Implements the register interface of the sh4 interrupt controller.
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For the actual implementation of interrupt caching/handling logic, look at sh4_interrupts.cpp
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--
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*/
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#include "types.h"
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#include "../sh4_interrupts.h"
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#include "../sh4_mmr.h"
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//Register writes need interrupt re-testing !
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void write_INTC_IPRA(u32 addr, u32 data)
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{
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if (INTC_IPRA.reg_data!=(u16)data)
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{
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INTC_IPRA.reg_data=(u16)data;
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SIIDRebuild(); //we need to rebuild the table
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}
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}
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void write_INTC_IPRB(u32 addr, u32 data)
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{
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if (INTC_IPRB.reg_data!=(u16)data)
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{
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INTC_IPRB.reg_data=(u16)data;
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SIIDRebuild(); //we need to rebuild the table
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}
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}
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void write_INTC_IPRC(u32 addr, u32 data)
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{
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if (INTC_IPRC.reg_data!=(u16)data)
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{
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INTC_IPRC.reg_data=(u16)data;
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SIIDRebuild(); //we need to rebuild the table
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}
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}
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//Init/Res/Term
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void intc_init()
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{
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//INTC ICR 0xFFD00000 0x1FD00000 16 0x0000 0x0000 Held Held Pclk
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sh4_rio_reg(INTC,INTC_ICR_addr,RIO_DATA,16);
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//INTC IPRA 0xFFD00004 0x1FD00004 16 0x0000 0x0000 Held Held Pclk
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sh4_rio_reg(INTC,INTC_IPRA_addr,RIO_WF,16,0,&write_INTC_IPRA);
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//INTC IPRB 0xFFD00008 0x1FD00008 16 0x0000 0x0000 Held Held Pclk
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sh4_rio_reg(INTC,INTC_IPRB_addr,RIO_WF,16,0,&write_INTC_IPRB);
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//INTC IPRC 0xFFD0000C 0x1FD0000C 16 0x0000 0x0000 Held Held Pclk
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sh4_rio_reg(INTC,INTC_IPRC_addr,RIO_WF,16,0,&write_INTC_IPRC);
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interrupts_init();
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}
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void intc_reset()
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{
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INTC_ICR.reg_data = 0x0;
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INTC_IPRA.reg_data = 0x0;
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INTC_IPRB.reg_data = 0x0;
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INTC_IPRC.reg_data = 0x0;
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SIIDRebuild(); //rebuild the interrupts table
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interrupts_reset();
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}
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void intc_term()
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{
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interrupts_term();
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}
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