718 lines
15 KiB
C++
718 lines
15 KiB
C++
#include "mmu.h"
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#include "hw/sh4/sh4_if.h"
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#include "hw/sh4/sh4_interrupts.h"
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#include "hw/sh4/sh4_core.h"
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#include "types.h"
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#include "hw/mem/_vmem.h"
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TLB_Entry UTLB[64];
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TLB_Entry ITLB[4];
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#if defined(NO_MMU)
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//SQ fast remap , mainly hackish , assumes 1MB pages
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//max 64MB can be remapped on SQ
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u32 sq_remap[64];
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//Sync memory mapping to MMU , suspend compiled blocks if needed.entry is a UTLB entry # , -1 is for full sync
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bool UTLB_Sync(u32 entry)
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{
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if ((UTLB[entry].Address.VPN & (0xFC000000 >> 10)) == (0xE0000000 >> 10))
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{
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u32 vpn_sq = ((UTLB[entry].Address.VPN & 0x7FFFF) >> 10) & 0x3F;//upper bits are always known [0xE0/E1/E2/E3]
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sq_remap[vpn_sq] = UTLB[entry].Data.PPN << 10;
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printf("SQ remap %d : 0x%X to 0x%X\n", entry, UTLB[entry].Address.VPN << 10, UTLB[entry].Data.PPN << 10);
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}
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else
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{
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printf("MEM remap %d : 0x%X to 0x%X\n", entry, UTLB[entry].Address.VPN << 10, UTLB[entry].Data.PPN << 10);
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}
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return true;
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}
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//Sync memory mapping to MMU, suspend compiled blocks if needed.entry is a ITLB entry # , -1 is for full sync
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void ITLB_Sync(u32 entry)
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{
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printf("ITLB MEM remap %d : 0x%X to 0x%X\n",entry,ITLB[entry].Address.VPN<<10,ITLB[entry].Data.PPN<<10);
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}
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void MMU_init()
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{
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}
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void MMU_reset()
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{
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memset(UTLB,0,sizeof(UTLB));
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memset(ITLB,0,sizeof(ITLB));
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}
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void MMU_term()
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{
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}
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#else
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/*
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MMU support code
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This is mostly hacked-on as the core was never meant to have mmu support
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There are two modes, one with 'full' mmu emulation (for wince/bleem/wtfever)
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and a fast-hack mode for 1mb sqremaps (for katana)
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defining NO_MMU disables the full mmu emulation
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*/
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#include "mmu.h"
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#include "mmu_impl.h"
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#include "hw/sh4/sh4_if.h"
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#include "ccn.h"
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#include "hw/sh4/sh4_interrupts.h"
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#include "hw/sh4/sh4_if.h"
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#include "hw/mem/_vmem.h"
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#define printf_mmu(...)
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#define printf_win32(...)
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//SQ fast remap , mailny hackish , assumes 1 mb pages
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//max 64 mb can be remapped on SQ
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const u32 mmu_mask[4] =
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{
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((0xFFFFFFFF) >> 10) << 10, //1 kb page
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((0xFFFFFFFF) >> 12) << 12, //4 kb page
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((0xFFFFFFFF) >> 16) << 16, //64 kb page
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((0xFFFFFFFF) >> 20) << 20 //1 MB page
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};
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const u32 fast_reg_lut[8] =
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{
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0, 0, 0, 0 //P0-U0
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, 1 //P1
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, 1 //P2
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, 0 //P3
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, 1 //P4
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};
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const u32 ITLB_LRU_OR[4] =
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{
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0x00,//000xxx
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0x20,//1xx00x
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0x14,//x1x1x0
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0x0B,//xx1x11
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};
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const u32 ITLB_LRU_AND[4] =
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{
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0x07,//000xxx
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0x39,//1xx00x
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0x3E,//x1x1x0
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0x3F,//xx1x11
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};
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u32 ITLB_LRU_USE[64];
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//sync mem mapping to mmu , suspend compiled blocks if needed.entry is a UTLB entry # , -1 is for full sync
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bool UTLB_Sync(u32 entry)
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{
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printf_mmu("UTLB MEM remap %d : 0x%X to 0x%X : %d\n", entry, UTLB[entry].Address.VPN << 10, UTLB[entry].Data.PPN << 10, UTLB[entry].Data.V);
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if (UTLB[entry].Data.V == 0)
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return true;
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if ((UTLB[entry].Address.VPN & (0xFC000000 >> 10)) == (0xE0000000 >> 10))
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{
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#ifdef NO_MMU
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u32 vpn_sq = ((UTLB[entry].Address.VPN & (0x3FFFFFF >> 10)) >> 10) & 0x3F;//upper bits are allways known [0xE0/E1/E2/E3]
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sq_remap[vpn_sq] = UTLB[entry].Data.PPN << 10;
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log("SQ remap %d : 0x%X to 0x%X\n", entry, UTLB[entry].Address.VPN << 10, UTLB[entry].Data.PPN << 10);
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#endif
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return true;
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}
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else
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{
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#ifdef NO_MMU
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if ((UTLB[entry].Address.VPN&(0x1FFFFFFF >> 10)) == (UTLB[entry].Data.PPN&(0x1FFFFFFF >> 10)))
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{
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log("Static remap %d : 0x%X to 0x%X\n", entry, UTLB[entry].Address.VPN << 10, UTLB[entry].Data.PPN << 10);
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return true;
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}
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log("Dynamic remap %d : 0x%X to 0x%X\n", entry, UTLB[entry].Address.VPN << 10, UTLB[entry].Data.PPN << 10);
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#endif
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return false;//log("MEM remap %d : 0x%X to 0x%X\n",entry,UTLB[entry].Address.VPN<<10,UTLB[entry].Data.PPN<<10);
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}
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}
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//sync mem mapping to mmu , suspend compiled blocks if needed.entry is a ITLB entry # , -1 is for full sync
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void ITLB_Sync(u32 entry)
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{
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printf_mmu("ITLB MEM remap %d : 0x%X to 0x%X : %d\n", entry, ITLB[entry].Address.VPN << 10, ITLB[entry].Data.PPN << 10, ITLB[entry].Data.V);
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}
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void RaiseException(u32 expEvnt, u32 callVect) {
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#if !defined(NO_MMU)
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SH4ThrownException ex = { next_pc - 2, expEvnt, callVect };
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throw ex;
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#else
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msgboxf("Can't raise exceptions yet", MBX_ICONERROR);
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#endif
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}
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u32 mmu_error_TT;
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void mmu_raise_exeption(u32 mmu_error, u32 address, u32 am)
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{
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printf_mmu("mmu_raise_exeption -> pc = 0x%X : ", next_pc);
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CCN_TEA = address;
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CCN_PTEH.VPN = address >> 10;
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//save translation type error :)
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mmu_error_TT = am;
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switch (mmu_error)
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{
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//No error
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case MMU_ERROR_NONE:
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printf("Error : mmu_raise_exeption(MMU_ERROR_NONE)\n");
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getc(stdin);
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break;
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//TLB miss
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case MMU_ERROR_TLB_MISS:
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printf_mmu("MMU_ERROR_UTLB_MISS 0x%X, handled\n", address);
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if (am == MMU_TT_DWRITE) //WTLBMISS - Write Data TLB Miss Exception
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RaiseException(0x60, 0x400);
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else if (am == MMU_TT_DREAD) //RTLBMISS - Read Data TLB Miss Exception
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RaiseException(0x40, 0x400);
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else //ITLBMISS - Instruction TLB Miss Exception
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RaiseException(0x40, 0x400);
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return;
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break;
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//TLB Multyhit
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case MMU_ERROR_TLB_MHIT:
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printf("MMU_ERROR_TLB_MHIT @ 0x%X\n", address);
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break;
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//Mem is read/write protected (depends on translation type)
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case MMU_ERROR_PROTECTED:
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printf_mmu("MMU_ERROR_PROTECTED 0x%X, handled\n", address);
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if (am == MMU_TT_DWRITE) //WRITEPROT - Write Data TLB Protection Violation Exception
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RaiseException(0xC0, 0x100);
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else if (am == MMU_TT_DREAD) //READPROT - Data TLB Protection Violation Exception
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RaiseException(0xA0, 0x100);
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else
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{
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verify(false);
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}
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return;
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break;
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//Mem is write protected , firstwrite
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case MMU_ERROR_FIRSTWRITE:
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printf_mmu("MMU_ERROR_FIRSTWRITE\n");
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verify(am == MMU_TT_DWRITE);
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//FIRSTWRITE - Initial Page Write Exception
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RaiseException(0x80, 0x100);
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return;
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break;
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//data read/write missasligned
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case MMU_ERROR_BADADDR:
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if (am == MMU_TT_DWRITE) //WADDERR - Write Data Address Error
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RaiseException(0x100, 0x100);
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else if (am == MMU_TT_DREAD) //RADDERR - Read Data Address Error
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RaiseException(0xE0, 0x100);
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else //IADDERR - Instruction Address Error
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{
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printf_mmu("MMU_ERROR_BADADDR(i) 0x%X\n", address);
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RaiseException(0xE0, 0x100);
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return;
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}
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printf_mmu("MMU_ERROR_BADADDR(d) 0x%X, handled\n", address);
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return;
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break;
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//Can't Execute
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case MMU_ERROR_EXECPROT:
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printf("MMU_ERROR_EXECPROT 0x%X\n", address);
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//EXECPROT - Instruction TLB Protection Violation Exception
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RaiseException(0xA0, 0x100);
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return;
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break;
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}
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__debugbreak();
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}
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bool mmu_match(u32 va, CCN_PTEH_type Address, CCN_PTEL_type Data)
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{
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if (Data.V == 0)
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return false;
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u32 sz = Data.SZ1 * 2 + Data.SZ0;
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u32 mask = mmu_mask[sz];
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if ((((Address.VPN << 10)&mask) == (va&mask)))
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{
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bool asid_match = (Data.SH == 0) && ((sr.MD == 0) || (CCN_MMUCR.SV == 0));
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if ((asid_match == false) || (Address.ASID == CCN_PTEH.ASID))
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{
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return true;
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}
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}
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return false;
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}
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//Do a full lookup on the UTLB entry's
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u32 mmu_full_lookup(u32 va, u32& idx, u32& rv)
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{
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CCN_MMUCR.URC++;
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if (CCN_MMUCR.URB == CCN_MMUCR.URC)
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CCN_MMUCR.URC = 0;
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u32 entry = 0;
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u32 nom = 0;
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for (u32 i = 0; i<64; i++)
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{
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//verify(sz!=0);
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if (mmu_match(va, UTLB[i].Address, UTLB[i].Data))
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{
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entry = i;
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nom++;
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u32 sz = UTLB[i].Data.SZ1 * 2 + UTLB[i].Data.SZ0;
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u32 mask = mmu_mask[sz];
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//VPN->PPN | low bits
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rv = ((UTLB[i].Data.PPN << 10)&mask) | (va&(~mask));
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}
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}
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if (nom != 1)
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{
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if (nom)
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{
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return MMU_ERROR_TLB_MHIT;
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}
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else
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{
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return MMU_ERROR_TLB_MISS;
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}
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}
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idx = entry;
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return MMU_ERROR_NONE;
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}
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//Simple QACR translation for mmu (when AT is off)
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u32 mmu_QACR_SQ(u32 va)
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{
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u32 QACR;
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//default to sq 0
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QACR = CCN_QACR_TR[0];
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//sq1 ? if so use QACR1
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if (va & 0x20)
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QACR = CCN_QACR_TR[1];
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va &= ~0x1f;
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return QACR + va;
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}
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template<u32 translation_type>
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u32 mmu_full_SQ(u32 va, u32& rv)
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{
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if ((va & 3) || (CCN_MMUCR.SQMD == 1 && sr.MD == 0))
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{
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//here, or after ?
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return MMU_ERROR_BADADDR;
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}
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if (CCN_MMUCR.AT)
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{
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//Address=Dest&0xFFFFFFE0;
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u32 entry;
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u32 lookup = mmu_full_lookup(va, entry, rv);
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rv &= ~31;//lower 5 bits are forced to 0
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if (lookup != MMU_ERROR_NONE)
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return lookup;
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u32 md = UTLB[entry].Data.PR >> 1;
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//Priv mode protection
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if ((md == 0) && sr.MD == 0)
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{
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return MMU_ERROR_PROTECTED;
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}
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//Write Protection (Lock or FW)
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if (translation_type == MMU_TT_DWRITE)
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{
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if ((UTLB[entry].Data.PR & 1) == 0)
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return MMU_ERROR_PROTECTED;
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else if (UTLB[entry].Data.D == 0)
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return MMU_ERROR_FIRSTWRITE;
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}
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}
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else
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{
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rv = mmu_QACR_SQ(va);
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}
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return MMU_ERROR_NONE;
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}
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template<u32 translation_type>
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u32 mmu_data_translation(u32 va, u32& rv)
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{
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//*opt notice* this could be only checked for writes, as reads are invalid
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if ((va & 0xFC000000) == 0xE0000000)
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{
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u32 lookup = mmu_full_SQ<translation_type>(va, rv);
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if (lookup != MMU_ERROR_NONE)
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return lookup;
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rv = va; //SQ writes are not translated, only write backs are.
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return MMU_ERROR_NONE;
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}
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if ((sr.MD == 0) && (va & 0x80000000) != 0)
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{
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//if on kernel, and not SQ addr -> error
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return MMU_ERROR_BADADDR;
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}
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if (sr.MD == 1 && ((va & 0xFC000000) == 0x7C000000))
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{
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rv = va;
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return MMU_ERROR_NONE;
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}
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if ((CCN_MMUCR.AT == 0) || (fast_reg_lut[va >> 29] != 0))
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{
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rv = va;
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return MMU_ERROR_NONE;
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}
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/*
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if ( CCN_CCR.ORA && ((va&0xFC000000)==0x7C000000))
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{
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verify(false);
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return va;
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}
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*/
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u32 entry;
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u32 lookup = mmu_full_lookup(va, entry, rv);
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if (lookup != MMU_ERROR_NONE)
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return lookup;
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u32 md = UTLB[entry].Data.PR >> 1;
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//0X & User mode-> protection violation
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//Priv mode protection
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if ((md == 0) && sr.MD == 0)
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{
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return MMU_ERROR_PROTECTED;
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}
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//X0 -> read olny
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//X1 -> read/write , can be FW
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//Write Protection (Lock or FW)
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if (translation_type == MMU_TT_DWRITE)
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{
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if ((UTLB[entry].Data.PR & 1) == 0)
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return MMU_ERROR_PROTECTED;
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else if (UTLB[entry].Data.D == 0)
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return MMU_ERROR_FIRSTWRITE;
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}
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return MMU_ERROR_NONE;
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}
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u32 mmu_instruction_translation(u32 va, u32& rv)
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{
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if ((sr.MD == 0) && (va & 0x80000000) != 0)
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{
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//if SQ disabled , or if if SQ on but out of SQ mem then BAD ADDR ;)
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if (va >= 0xE0000000)
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return MMU_ERROR_BADADDR;
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}
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if ((CCN_MMUCR.AT == 0) || (fast_reg_lut[va >> 29] != 0))
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{
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rv = va;
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return MMU_ERROR_NONE;
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}
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bool mmach = false;
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retry_ITLB_Match:
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u32 entry = 4;
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u32 nom = 0;
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for (u32 i = 0; i<4; i++)
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{
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if (ITLB[i].Data.V == 0)
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continue;
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u32 sz = ITLB[i].Data.SZ1 * 2 + ITLB[i].Data.SZ0;
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u32 mask = mmu_mask[sz];
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if ((((ITLB[i].Address.VPN << 10)&mask) == (va&mask)))
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{
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bool asid_match = (ITLB[i].Data.SH == 0) && ((sr.MD == 0) || (CCN_MMUCR.SV == 0));
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if ((asid_match == false) || (ITLB[i].Address.ASID == CCN_PTEH.ASID))
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{
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//verify(sz!=0);
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entry = i;
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nom++;
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//VPN->PPN | low bits
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rv = ((ITLB[i].Data.PPN << 10)&mask) | (va&(~mask));
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}
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}
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}
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if (entry == 4)
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{
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verify(mmach == false);
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u32 lookup = mmu_full_lookup(va, entry, rv);
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if (lookup != MMU_ERROR_NONE)
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return lookup;
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u32 replace_index = ITLB_LRU_USE[CCN_MMUCR.LRUI];
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verify(replace_index != 0xFFFFFFFF);
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ITLB[replace_index] = UTLB[entry];
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entry = replace_index;
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ITLB_Sync(entry);
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mmach = true;
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goto retry_ITLB_Match;
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}
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else if (nom != 1)
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{
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if (nom)
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{
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return MMU_ERROR_TLB_MHIT;
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}
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else
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{
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return MMU_ERROR_TLB_MISS;
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}
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}
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CCN_MMUCR.LRUI &= ITLB_LRU_AND[entry];
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CCN_MMUCR.LRUI |= ITLB_LRU_OR[entry];
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u32 md = ITLB[entry].Data.PR >> 1;
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//0X & User mode-> protection violation
|
|
//Priv mode protection
|
|
if ((md == 0) && sr.MD == 0)
|
|
{
|
|
return MMU_ERROR_PROTECTED;
|
|
}
|
|
|
|
return MMU_ERROR_NONE;
|
|
}
|
|
void MMU_init()
|
|
{
|
|
memset(ITLB_LRU_USE, 0xFF, sizeof(ITLB_LRU_USE));
|
|
for (u32 e = 0; e<4; e++)
|
|
{
|
|
u32 match_key = ((~ITLB_LRU_AND[e]) & 0x3F);
|
|
u32 match_mask = match_key | ITLB_LRU_OR[e];
|
|
for (u32 i = 0; i<64; i++)
|
|
{
|
|
if ((i & match_mask) == match_key)
|
|
{
|
|
verify(ITLB_LRU_USE[i] == 0xFFFFFFFF);
|
|
ITLB_LRU_USE[i] = e;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
void MMU_reset()
|
|
{
|
|
memset(UTLB, 0, sizeof(UTLB));
|
|
memset(ITLB, 0, sizeof(ITLB));
|
|
}
|
|
|
|
void MMU_term()
|
|
{
|
|
}
|
|
|
|
u8 DYNACALL mmu_ReadMem8(u32 adr)
|
|
{
|
|
u32 addr;
|
|
u32 tv = mmu_data_translation<MMU_TT_DREAD>(adr, addr);
|
|
if (tv == 0)
|
|
return _vmem_ReadMem8(addr);
|
|
else
|
|
mmu_raise_exeption(tv, adr, MMU_TT_DREAD);
|
|
|
|
return 0;
|
|
}
|
|
|
|
u16 DYNACALL mmu_ReadMem16(u32 adr)
|
|
{
|
|
if (adr & 1)
|
|
{
|
|
mmu_raise_exeption(MMU_ERROR_BADADDR, adr, MMU_TT_DREAD);
|
|
return 0;
|
|
}
|
|
u32 addr;
|
|
u32 tv = mmu_data_translation<MMU_TT_DREAD>(adr, addr);
|
|
if (tv == 0)
|
|
return _vmem_ReadMem16(addr);
|
|
else
|
|
mmu_raise_exeption(tv, adr, MMU_TT_DREAD);
|
|
|
|
return 0;
|
|
}
|
|
u16 DYNACALL mmu_IReadMem16(u32 adr)
|
|
{
|
|
if (adr & 1)
|
|
{
|
|
mmu_raise_exeption(MMU_ERROR_BADADDR, adr, MMU_TT_IREAD);
|
|
return 0;
|
|
}
|
|
u32 addr;
|
|
u32 tv = mmu_instruction_translation(adr, addr);
|
|
if (tv == 0)
|
|
return _vmem_ReadMem16(addr);
|
|
else
|
|
mmu_raise_exeption(tv, adr, MMU_TT_IREAD);
|
|
|
|
return 0;
|
|
}
|
|
|
|
u32 DYNACALL mmu_ReadMem32(u32 adr)
|
|
{
|
|
if (adr & 3)
|
|
{
|
|
mmu_raise_exeption(MMU_ERROR_BADADDR, adr, MMU_TT_DREAD);
|
|
return 0;
|
|
}
|
|
u32 addr;
|
|
u32 tv = mmu_data_translation<MMU_TT_DREAD>(adr, addr);
|
|
if (tv == 0)
|
|
return _vmem_ReadMem32(addr);
|
|
else
|
|
mmu_raise_exeption(tv, adr, MMU_TT_DREAD);
|
|
|
|
return 0;
|
|
}
|
|
u64 DYNACALL mmu_ReadMem64(u32 adr)
|
|
{
|
|
if (adr & 7)
|
|
{
|
|
mmu_raise_exeption(MMU_ERROR_BADADDR, adr, MMU_TT_DREAD);
|
|
return 0;
|
|
}
|
|
u32 addr;
|
|
u32 tv = mmu_data_translation<MMU_TT_DREAD>(adr, addr);
|
|
if (tv == 0)
|
|
{
|
|
return _vmem_ReadMem64(addr);
|
|
}
|
|
else
|
|
mmu_raise_exeption(tv, adr, MMU_TT_DREAD);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void DYNACALL mmu_WriteMem8(u32 adr, u8 data)
|
|
{
|
|
u32 addr;
|
|
u32 tv = mmu_data_translation<MMU_TT_DWRITE>(adr, addr);
|
|
if (tv == 0)
|
|
{
|
|
_vmem_WriteMem8(addr, data);
|
|
return;
|
|
}
|
|
else
|
|
mmu_raise_exeption(tv, adr, MMU_TT_DWRITE);
|
|
}
|
|
|
|
void DYNACALL mmu_WriteMem16(u32 adr, u16 data)
|
|
{
|
|
if (adr & 1)
|
|
{
|
|
mmu_raise_exeption(MMU_ERROR_BADADDR, adr, MMU_TT_DWRITE);
|
|
return;
|
|
}
|
|
u32 addr;
|
|
u32 tv = mmu_data_translation<MMU_TT_DWRITE>(adr, addr);
|
|
if (tv == 0)
|
|
{
|
|
_vmem_WriteMem16(addr, data);
|
|
return;
|
|
}
|
|
else
|
|
mmu_raise_exeption(tv, adr, MMU_TT_DWRITE);
|
|
}
|
|
void DYNACALL mmu_WriteMem32(u32 adr, u32 data)
|
|
{
|
|
if (adr & 3)
|
|
{
|
|
mmu_raise_exeption(MMU_ERROR_BADADDR, adr, MMU_TT_DWRITE);
|
|
return;
|
|
}
|
|
u32 addr;
|
|
u32 tv = mmu_data_translation<MMU_TT_DWRITE>(adr, addr);
|
|
if (tv == 0)
|
|
{
|
|
_vmem_WriteMem32(addr, data);
|
|
return;
|
|
}
|
|
else
|
|
mmu_raise_exeption(tv, adr, MMU_TT_DWRITE);
|
|
}
|
|
void DYNACALL mmu_WriteMem64(u32 adr, u64 data)
|
|
{
|
|
if (adr & 7)
|
|
{
|
|
mmu_raise_exeption(MMU_ERROR_BADADDR, adr, MMU_TT_DWRITE);
|
|
return;
|
|
}
|
|
u32 addr;
|
|
u32 tv = mmu_data_translation<MMU_TT_DWRITE>(adr, addr);
|
|
if (tv == 0)
|
|
{
|
|
_vmem_WriteMem64(addr, data);
|
|
return;
|
|
}
|
|
else
|
|
mmu_raise_exeption(tv, adr, MMU_TT_DWRITE);
|
|
}
|
|
|
|
bool mmu_TranslateSQW(u32 adr, u32* out)
|
|
{
|
|
#ifndef NO_MMU
|
|
|
|
u32 addr;
|
|
u32 tv = mmu_full_SQ<MMU_TT_DREAD>(adr, addr);
|
|
if (tv != 0)
|
|
{
|
|
mmu_raise_exeption(tv, adr, MMU_TT_DREAD);
|
|
return false;
|
|
}
|
|
|
|
*out = addr;
|
|
#else
|
|
//This will olny work for 1 mb pages .. hopefully nothing else is used
|
|
//*FIXME* to work for all page sizes ?
|
|
|
|
if (CCN_MMUCR.AT == 0)
|
|
{ //simple translation
|
|
*out = mmu_QACR_SQ(adr);
|
|
}
|
|
else
|
|
{ //remap table
|
|
*out = sq_remap[(adr >> 20) & 0x3F] | (adr & 0xFFFE0);
|
|
}
|
|
#endif
|
|
return true;
|
|
}
|
|
#endif
|