902 lines
17 KiB
C++
902 lines
17 KiB
C++
/*
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Sh4 internal register routing (P4 & 'area 7')
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*/
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#include <array>
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#include "types.h"
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#include "sh4_mmr.h"
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#include "hw/mem/_vmem.h"
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#include "modules/mmu.h"
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#include "modules/ccn.h"
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#include "modules/modules.h"
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#include "sh4_cache.h"
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//64bytes of sq // now on context ~
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std::array<u8, OnChipRAM_SIZE> OnChipRAM;
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//All registers are 4 byte aligned
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RegisterStruct CCN[18];
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RegisterStruct UBC[9];
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RegisterStruct BSC[19];
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RegisterStruct DMAC[17];
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RegisterStruct CPG[5];
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RegisterStruct RTC[16];
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RegisterStruct INTC[5];
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RegisterStruct TMU[12];
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RegisterStruct SCI[8];
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RegisterStruct SCIF[10];
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static u32 sh4io_read_noacc(u32 addr)
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{
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INFO_LOG(SH4, "sh4io: Invalid read access @ %08X", addr);
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return 0;
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}
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static void sh4io_write_noacc(u32 addr, u32 data)
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{
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INFO_LOG(SH4, "sh4io: Invalid write access @ %08X %08X", addr, data);
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}
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static void sh4io_write_const(u32 addr, u32 data)
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{
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INFO_LOG(SH4, "sh4io: Const write ignored @ %08X <- %08X", addr, data);
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}
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void sh4_rio_reg(RegisterStruct *arr, u32 addr, RegIO flags, RegReadAddrFP* rf, RegWriteAddrFP* wf)
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{
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u32 idx = (addr & 255) / 4;
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arr[idx].flags = flags;
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if (flags == RIO_NO_ACCESS)
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{
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arr[idx].readFunctionAddr = sh4io_read_noacc;
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arr[idx].writeFunctionAddr = sh4io_write_noacc;
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}
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else if (flags == RIO_RO)
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{
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arr[idx].writeFunctionAddr = sh4io_write_const;
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arr[idx].data32 = 0;
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}
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else
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{
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if (flags & REG_RF)
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arr[idx].readFunctionAddr = rf;
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else
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arr[idx].data32 = 0;
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if (flags & REG_WF)
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arr[idx].writeFunctionAddr = wf == nullptr ? &sh4io_write_noacc : wf;
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}
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}
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template<typename T>
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T sh4_rio_read(RegisterStruct *regs, u32 addr)
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{
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u32 offset = addr & 255;
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#ifdef TRACE
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if (offset & 3) //4 is min align size
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{
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WARN_LOG(SH4, "Unaligned System Bus register read @ %x", addr);
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}
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#endif
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offset >>= 2;
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if (!(regs[offset].flags & REG_RF))
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return (T)regs[offset].data32;
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else
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return (T)regs[offset].readFunctionAddr(addr);
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}
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template<typename T>
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void sh4_rio_write(RegisterStruct *regs, u32 addr, T data)
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{
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u32 offset = addr & 255;
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#ifdef TRACE
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if (offset & 3) //4 is min align size
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{
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WARN_LOG(SH4, "Unaligned System bus register write @ %x", addr);
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}
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#endif
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offset >>= 2;
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if (!(regs[offset].flags & REG_WF))
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regs[offset].data32 = data;
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else
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regs[offset].writeFunctionAddr(addr, data);
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}
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#define SH4_REG_NAME(r) { r##_addr, #r },
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const std::map<u32, const char *> sh4_reg_names = {
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SH4_REG_NAME(CCN_PTEH)
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SH4_REG_NAME(CCN_PTEL)
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SH4_REG_NAME(CCN_TTB)
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SH4_REG_NAME(CCN_TEA)
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SH4_REG_NAME(CCN_CCR)
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SH4_REG_NAME(CCN_TRA)
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SH4_REG_NAME(CCN_EXPEVT)
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SH4_REG_NAME(CCN_INTEVT)
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SH4_REG_NAME(CPU_VERSION)
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SH4_REG_NAME(CCN_PTEA)
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SH4_REG_NAME(CCN_QACR0)
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SH4_REG_NAME(CCN_QACR1)
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SH4_REG_NAME(CCN_PRR)
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SH4_REG_NAME(UBC_BARA)
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SH4_REG_NAME(UBC_BAMRA)
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SH4_REG_NAME(UBC_BBRA)
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SH4_REG_NAME(UBC_BARB)
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SH4_REG_NAME(UBC_BAMRB)
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SH4_REG_NAME(UBC_BBRB)
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SH4_REG_NAME(UBC_BDRB)
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SH4_REG_NAME(UBC_BDMRB)
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SH4_REG_NAME(UBC_BRCR)
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SH4_REG_NAME(BSC_BCR1)
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SH4_REG_NAME(BSC_BCR2)
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SH4_REG_NAME(BSC_WCR1)
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SH4_REG_NAME(BSC_WCR2)
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SH4_REG_NAME(BSC_WCR3)
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SH4_REG_NAME(BSC_MCR)
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SH4_REG_NAME(BSC_PCR)
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SH4_REG_NAME(BSC_RTCSR)
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SH4_REG_NAME(BSC_RTCNT)
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SH4_REG_NAME(BSC_RTCOR)
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SH4_REG_NAME(BSC_RFCR)
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SH4_REG_NAME(BSC_PCTRA)
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SH4_REG_NAME(BSC_PDTRA)
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SH4_REG_NAME(BSC_PCTRB)
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SH4_REG_NAME(BSC_PDTRB)
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SH4_REG_NAME(BSC_GPIOIC)
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SH4_REG_NAME(BSC_SDMR2)
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SH4_REG_NAME(BSC_SDMR3)
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SH4_REG_NAME(DMAC_SAR0)
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SH4_REG_NAME(DMAC_DAR0)
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SH4_REG_NAME(DMAC_DMATCR0)
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SH4_REG_NAME(DMAC_CHCR0)
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SH4_REG_NAME(DMAC_SAR1)
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SH4_REG_NAME(DMAC_DAR1)
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SH4_REG_NAME(DMAC_DMATCR1)
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SH4_REG_NAME(DMAC_CHCR1)
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SH4_REG_NAME(DMAC_SAR2)
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SH4_REG_NAME(DMAC_DAR2)
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SH4_REG_NAME(DMAC_DMATCR2)
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SH4_REG_NAME(DMAC_CHCR2)
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SH4_REG_NAME(DMAC_SAR3)
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SH4_REG_NAME(DMAC_DAR3)
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SH4_REG_NAME(DMAC_DMATCR3)
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SH4_REG_NAME(DMAC_CHCR3)
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SH4_REG_NAME(DMAC_DMAOR)
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SH4_REG_NAME(CPG_FRQCR)
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SH4_REG_NAME(CPG_STBCR)
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SH4_REG_NAME(CPG_WTCNT)
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SH4_REG_NAME(CPG_WTCSR)
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SH4_REG_NAME(CPG_STBCR2)
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SH4_REG_NAME(RTC_R64CNT)
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SH4_REG_NAME(RTC_RSECCNT)
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SH4_REG_NAME(RTC_RMINCNT)
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SH4_REG_NAME(RTC_RHRCNT)
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SH4_REG_NAME(RTC_RWKCNT)
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SH4_REG_NAME(RTC_RDAYCNT)
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SH4_REG_NAME(RTC_RMONCNT)
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SH4_REG_NAME(RTC_RYRCNT)
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SH4_REG_NAME(RTC_RSECAR)
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SH4_REG_NAME(RTC_RMINAR)
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SH4_REG_NAME(RTC_RHRAR)
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SH4_REG_NAME(RTC_RWKAR)
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SH4_REG_NAME(RTC_RDAYAR)
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SH4_REG_NAME(RTC_RMONAR)
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SH4_REG_NAME(RTC_RCR1)
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SH4_REG_NAME(RTC_RCR2)
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SH4_REG_NAME(INTC_ICR)
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SH4_REG_NAME(INTC_IPRA)
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SH4_REG_NAME(INTC_IPRB)
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SH4_REG_NAME(INTC_IPRC)
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SH4_REG_NAME(INTC_IPRD)
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SH4_REG_NAME(TMU_TOCR)
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SH4_REG_NAME(TMU_TSTR)
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SH4_REG_NAME(TMU_TCOR0)
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SH4_REG_NAME(TMU_TCNT0)
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SH4_REG_NAME(TMU_TCR0)
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SH4_REG_NAME(TMU_TCOR1)
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SH4_REG_NAME(TMU_TCNT1)
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SH4_REG_NAME(TMU_TCR1)
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SH4_REG_NAME(TMU_TCOR2)
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SH4_REG_NAME(TMU_TCNT2)
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SH4_REG_NAME(TMU_TCR2)
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SH4_REG_NAME(TMU_TCPR2)
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SH4_REG_NAME(SCI_SCSMR1)
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SH4_REG_NAME(SCI_SCBRR1)
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SH4_REG_NAME(SCI_SCSCR1)
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SH4_REG_NAME(SCI_SCTDR1)
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SH4_REG_NAME(SCI_SCSSR1)
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SH4_REG_NAME(SCI_SCRDR1)
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SH4_REG_NAME(SCI_SCSCMR1)
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SH4_REG_NAME(SCI_SCSPTR1)
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SH4_REG_NAME(SCIF_SCSMR2)
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SH4_REG_NAME(SCIF_SCBRR2)
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SH4_REG_NAME(SCIF_SCSCR2)
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SH4_REG_NAME(SCIF_SCFTDR2)
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SH4_REG_NAME(SCIF_SCFSR2)
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SH4_REG_NAME(SCIF_SCFRDR2)
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SH4_REG_NAME(SCIF_SCFCR2)
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SH4_REG_NAME(SCIF_SCFDR2)
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SH4_REG_NAME(SCIF_SCSPTR2)
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SH4_REG_NAME(SCIF_SCLSR2)
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SH4_REG_NAME(UDI_SDIR)
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SH4_REG_NAME(UDI_SDDR)
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};
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#undef SH4_REG_NAME
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static const char *regName(u32 paddr)
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{
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u32 addr = paddr & 0x1fffffff;
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static char regName[32];
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auto it = sh4_reg_names.find(addr);
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if (it == sh4_reg_names.end()) {
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sprintf(regName, "?%08x", paddr);
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return regName;
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}
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else
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return it->second;
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}
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//Region P4
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//Read P4
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template <class T>
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T DYNACALL ReadMem_P4(u32 addr)
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{
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constexpr size_t sz = sizeof(T);
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switch ((addr >> 24) & 0xFF)
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{
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case 0xE0:
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case 0xE1:
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case 0xE2:
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case 0xE3:
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INFO_LOG(SH4, "Unhandled p4 read [Store queue] 0x%x", addr);
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return 0;
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case 0xF0:
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DEBUG_LOG(SH4, "IC Address read %08x", addr);
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if (sz == 4)
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return icache.ReadAddressArray(addr);
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else
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return 0;
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case 0xF1:
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DEBUG_LOG(SH4, "IC Data read %08x", addr);
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if (sz == 4)
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return icache.ReadDataArray(addr);
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else
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return 0;
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case 0xF2:
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{
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u32 entry = (addr >> 8) & 3;
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return ITLB[entry].Address.reg_data | (ITLB[entry].Data.V << 8);
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}
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case 0xF3:
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{
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u32 entry = (addr >> 8) & 3;
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return ITLB[entry].Data.reg_data;
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}
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case 0xF4:
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DEBUG_LOG(SH4, "OC Address read %08x", addr);
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if (sz == 4)
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return ocache.ReadAddressArray(addr);
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else
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return 0;
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case 0xF5:
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DEBUG_LOG(SH4, "OC Data read %08x", addr);
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if (sz == 4)
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return ocache.ReadDataArray(addr);
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else
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return 0;
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case 0xF6:
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{
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u32 entry = (addr >> 8) & 63;
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u32 rv = UTLB[entry].Address.reg_data;
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rv |= UTLB[entry].Data.D << 9;
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rv |= UTLB[entry].Data.V << 8;
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return rv;
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}
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case 0xF7:
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{
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u32 entry = (addr >> 8) & 63;
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return UTLB[entry].Data.reg_data;
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}
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case 0xFF:
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INFO_LOG(SH4, "Unhandled p4 read [area7] 0x%x", addr);
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break;
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default:
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INFO_LOG(SH4, "Unhandled p4 read [Reserved] 0x%x", addr);
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break;
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}
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return 0;
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}
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//Write P4
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template <class T>
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void DYNACALL WriteMem_P4(u32 addr,T data)
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{
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constexpr size_t sz = sizeof(T);
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switch ((addr >> 24) & 0xFF)
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{
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case 0xE0:
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case 0xE1:
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case 0xE2:
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case 0xE3:
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INFO_LOG(SH4, "Unhandled p4 Write [Store queue] 0x%x", addr);
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break;
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case 0xF0:
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DEBUG_LOG(SH4, "IC Address write %08x = %x", addr, data);
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if (sz == 4)
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icache.WriteAddressArray(addr, data);
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return;
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case 0xF1:
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DEBUG_LOG(SH4, "IC Data write %08x = %x", addr, data);
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if (sz == 4)
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icache.WriteDataArray(addr, data);
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return;
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case 0xF2:
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{
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u32 entry = (addr >> 8) & 3;
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ITLB[entry].Address.reg_data = data & 0xFFFFFCFF;
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ITLB[entry].Data.V = (data >> 8) & 1;
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ITLB_Sync(entry);
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}
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return;
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case 0xF3:
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{
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u32 entry = (addr >> 8) & 3;
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if (addr & 0x800000)
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ITLB[entry].Assistance.reg_data = data & 0xf;
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else
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ITLB[entry].Data.reg_data=data;
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ITLB_Sync(entry);
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}
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return;
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case 0xF4:
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// DEBUG_LOG(SH4, "OC Address write %08x = %x", addr, data);
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if (sz == 4)
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ocache.WriteAddressArray(addr, data);
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return;
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case 0xF5:
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DEBUG_LOG(SH4, "OC Data write %08x = %x", addr, data);
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if (sz == 4)
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ocache.WriteDataArray(addr, data);
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return;
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case 0xF6:
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if (addr & 0x80)
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{
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CCN_PTEH_type t;
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t.reg_data = data;
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u32 va = t.VPN << 10;
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for (int i = 0; i < 64; i++)
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{
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if (mmu_match(va, UTLB[i].Address, UTLB[i].Data))
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{
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UTLB[i].Data.V = ((u32)data >> 8) & 1;
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UTLB[i].Data.D = ((u32)data >> 9) & 1;
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UTLB_Sync(i);
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}
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}
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for (int i = 0; i < 4; i++)
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{
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if (mmu_match(va, ITLB[i].Address, ITLB[i].Data))
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{
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ITLB[i].Data.V = ((u32)data >> 8) & 1;
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ITLB[i].Data.D = ((u32)data >> 9) & 1;
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ITLB_Sync(i);
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}
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}
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}
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else
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{
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u32 entry = (addr >> 8) & 63;
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UTLB[entry].Address.reg_data = data & 0xFFFFFCFF;
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UTLB[entry].Data.D = (data >> 9) & 1;
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UTLB[entry].Data.V = (data >> 8) & 1;
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UTLB_Sync(entry);
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}
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return;
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case 0xF7:
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{
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u32 entry = (addr >> 8) & 63;
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if (addr & 0x800000)
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UTLB[entry].Assistance.reg_data = data & 0xf;
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else
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UTLB[entry].Data.reg_data = data;
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UTLB_Sync(entry);
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}
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return;
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case 0xFF:
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INFO_LOG(SH4, "Unhandled p4 Write [area7] 0x%x = %x", addr, data);
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break;
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default:
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INFO_LOG(SH4, "Unhandled p4 Write [Reserved] 0x%x", addr);
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break;
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}
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}
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//***********
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//**Area 7**
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//***********
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#define OUT_OF_RANGE(reg) INFO_LOG(SH4, "Out of range on register %s index %x", reg, addr)
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#define A7_REG_HASH(addr) (((addr) >> 16) & 0x1FFF)
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//Read P4 memory-mapped registers
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template <class T>
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T DYNACALL ReadMem_p4mmr(u32 addr)
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{
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DEBUG_LOG(SH4, "read %s", regName(addr));
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/*
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if (likely(addr == 0xffd80024))
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return TMU_TCNT(2);
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if (likely(addr == 0xFFD8000C))
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return TMU_TCNT(0);
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*/
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if (likely(addr == 0xFF000028))
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return (T)CCN_INTEVT;
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if (likely(addr == 0xFFA0002C))
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return (T)DMAC_CHCR(2).full;
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addr &= 0x1FFFFFFF;
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u32 map_base = addr >> 16;
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switch (expected(map_base, A7_REG_HASH(TMU_BASE_addr)))
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{
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case A7_REG_HASH(CCN_BASE_addr):
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if (addr <= 0x1F000044)
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{
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return sh4_rio_read<T>(CCN, addr);
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}
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else
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{
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OUT_OF_RANGE("CCN");
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return 0;
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}
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break;
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case A7_REG_HASH(UBC_BASE_addr):
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if (addr <= 0x1F200020)
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{
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return sh4_rio_read<T>(UBC, addr);
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}
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else
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{
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OUT_OF_RANGE("UBC");
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return 0;
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}
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break;
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|
case A7_REG_HASH(BSC_BASE_addr):
|
|
if (addr <= 0x1F800048)
|
|
{
|
|
return sh4_rio_read<T>(BSC, addr);
|
|
}
|
|
else
|
|
{
|
|
OUT_OF_RANGE("BSC");
|
|
return 0;
|
|
}
|
|
break;
|
|
|
|
case A7_REG_HASH(BSC_SDMR2_addr):
|
|
//dram settings 2 / write only
|
|
INFO_LOG(SH4, "Read from write-only registers [dram settings 2]");
|
|
return 0;
|
|
case A7_REG_HASH(BSC_SDMR3_addr):
|
|
//dram settings 3 / write only
|
|
INFO_LOG(SH4, "Read from write-only registers [dram settings 3]");
|
|
return 0;
|
|
|
|
case A7_REG_HASH(DMAC_BASE_addr):
|
|
if (addr <= 0x1FA00040)
|
|
{
|
|
return sh4_rio_read<T>(DMAC, addr);
|
|
}
|
|
else
|
|
{
|
|
OUT_OF_RANGE("DMAC");
|
|
return 0;
|
|
}
|
|
break;
|
|
|
|
case A7_REG_HASH(CPG_BASE_addr):
|
|
if (addr <= 0x1FC00010)
|
|
{
|
|
return sh4_rio_read<T>(CPG, addr);
|
|
}
|
|
else
|
|
{
|
|
OUT_OF_RANGE("CPG");
|
|
return 0;
|
|
}
|
|
break;
|
|
|
|
case A7_REG_HASH(RTC_BASE_addr):
|
|
if (addr <= 0x1FC8003C)
|
|
{
|
|
return sh4_rio_read<T>(RTC, addr);
|
|
}
|
|
else
|
|
{
|
|
OUT_OF_RANGE("RTC");
|
|
return 0;
|
|
}
|
|
break;
|
|
|
|
case A7_REG_HASH(INTC_BASE_addr):
|
|
if (addr <= 0x1FD00010)
|
|
{
|
|
return sh4_rio_read<T>(INTC, addr);
|
|
}
|
|
else
|
|
{
|
|
OUT_OF_RANGE("INTC");
|
|
return 0;
|
|
}
|
|
break;
|
|
|
|
case A7_REG_HASH(TMU_BASE_addr):
|
|
if (addr <= 0x1FD8002C)
|
|
{
|
|
return sh4_rio_read<T>(TMU, addr);
|
|
}
|
|
else
|
|
{
|
|
OUT_OF_RANGE("TMU");
|
|
return 0;
|
|
}
|
|
break;
|
|
|
|
case A7_REG_HASH(SCI_BASE_addr):
|
|
if (addr <= 0x1FE0001C)
|
|
{
|
|
return sh4_rio_read<T>(SCI, addr);
|
|
}
|
|
else
|
|
{
|
|
OUT_OF_RANGE("SCI");
|
|
return 0;
|
|
}
|
|
break;
|
|
|
|
case A7_REG_HASH(SCIF_BASE_addr):
|
|
if (addr <= 0x1FE80024)
|
|
{
|
|
return sh4_rio_read<T>(SCIF, addr);
|
|
}
|
|
else
|
|
{
|
|
OUT_OF_RANGE("SCIF");
|
|
return 0;
|
|
}
|
|
break;
|
|
|
|
// Who really cares about ht-UDI? it's not existent on the Dreamcast IIRC
|
|
case A7_REG_HASH(UDI_BASE_addr):
|
|
switch(addr)
|
|
{
|
|
//UDI SDIR 0x1FF00000 0x1FF00000 16 0xFFFF Held Held Held Pclk
|
|
case UDI_SDIR_addr :
|
|
break;
|
|
|
|
|
|
//UDI SDDR 0x1FF00008 0x1FF00008 32 Held Held Held Held Pclk
|
|
case UDI_SDDR_addr :
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
|
|
INFO_LOG(SH4, "Unknown Read from P4 mmr - addr=%x", addr);
|
|
return 0;
|
|
}
|
|
|
|
//Write P4 memory-mapped registers
|
|
template <class T>
|
|
void DYNACALL WriteMem_p4mmr(u32 addr, T data)
|
|
{
|
|
DEBUG_LOG(SH4, "write %s = %x", regName(addr), (int)data);
|
|
|
|
if (likely(addr == 0xFF000038))
|
|
{
|
|
CCN_QACR_write<0>(addr, data);
|
|
return;
|
|
}
|
|
if (likely(addr == 0xFF00003C))
|
|
{
|
|
CCN_QACR_write<1>(addr, data);
|
|
return;
|
|
}
|
|
|
|
addr &= 0x1FFFFFFF;
|
|
u32 map_base = addr >> 16;
|
|
switch (map_base)
|
|
{
|
|
|
|
case A7_REG_HASH(CCN_BASE_addr):
|
|
if (addr <= 0x1F00003C)
|
|
sh4_rio_write(CCN, addr, data);
|
|
else
|
|
OUT_OF_RANGE("CCN");
|
|
return;
|
|
|
|
case A7_REG_HASH(UBC_BASE_addr):
|
|
if (addr <= 0x1F200020)
|
|
sh4_rio_write(UBC, addr, data);
|
|
else
|
|
OUT_OF_RANGE("UBC");
|
|
return;
|
|
|
|
case A7_REG_HASH(BSC_BASE_addr):
|
|
if (addr <= 0x1F800048)
|
|
sh4_rio_write(BSC, addr, data);
|
|
else
|
|
OUT_OF_RANGE("BSC");
|
|
return;
|
|
case A7_REG_HASH(BSC_SDMR2_addr):
|
|
//dram settings 2 / write only
|
|
return;
|
|
|
|
case A7_REG_HASH(BSC_SDMR3_addr):
|
|
//dram settings 3 / write only
|
|
return;
|
|
|
|
case A7_REG_HASH(DMAC_BASE_addr):
|
|
if (addr <= 0x1FA00040)
|
|
sh4_rio_write(DMAC, addr, data);
|
|
else
|
|
OUT_OF_RANGE("DMAC");
|
|
return;
|
|
|
|
case A7_REG_HASH(CPG_BASE_addr):
|
|
if (addr <= 0x1FC00010)
|
|
sh4_rio_write(CPG, addr, data);
|
|
else
|
|
OUT_OF_RANGE("CPG");
|
|
return;
|
|
|
|
case A7_REG_HASH(RTC_BASE_addr):
|
|
if (addr <= 0x1FC8003C)
|
|
sh4_rio_write(RTC, addr, data);
|
|
else
|
|
OUT_OF_RANGE("RTC");
|
|
return;
|
|
|
|
case A7_REG_HASH(INTC_BASE_addr):
|
|
if (addr <= 0x1FD00010)
|
|
sh4_rio_write(INTC, addr, data);
|
|
else
|
|
OUT_OF_RANGE("INTC");
|
|
return;
|
|
|
|
case A7_REG_HASH(TMU_BASE_addr):
|
|
if (addr <= 0x1FD8002C)
|
|
sh4_rio_write(TMU, addr, data);
|
|
else
|
|
OUT_OF_RANGE("TMU");
|
|
return;
|
|
|
|
case A7_REG_HASH(SCI_BASE_addr):
|
|
if (addr <= 0x1FE0001C)
|
|
sh4_rio_write(SCI, addr, data);
|
|
else
|
|
OUT_OF_RANGE("SCI");
|
|
return;
|
|
|
|
case A7_REG_HASH(SCIF_BASE_addr):
|
|
if (addr <= 0x1FE80024)
|
|
sh4_rio_write(SCIF, addr, data);
|
|
else
|
|
OUT_OF_RANGE("SCIF");
|
|
return;
|
|
|
|
//who really cares about ht-udi ? it's not existent on dc iirc ..
|
|
case A7_REG_HASH(UDI_BASE_addr):
|
|
switch(addr)
|
|
{
|
|
//UDI SDIR 0xFFF00000 0x1FF00000 16 0xFFFF Held Held Held Pclk
|
|
case UDI_SDIR_addr :
|
|
break;
|
|
|
|
|
|
//UDI SDDR 0xFFF00008 0x1FF00008 32 Held Held Held Held Pclk
|
|
case UDI_SDDR_addr :
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
|
|
INFO_LOG(SH4, "Write to P4 mmr not implemented, addr=%x, data=%x", addr, data);
|
|
}
|
|
|
|
|
|
//***********
|
|
//On Chip Ram
|
|
//***********
|
|
template <class T>
|
|
T DYNACALL ReadMem_area7_OCR(u32 addr)
|
|
{
|
|
if (CCN_CCR.ORA == 1)
|
|
return *(T *)&OnChipRAM[addr & OnChipRAM_MASK];
|
|
|
|
INFO_LOG(SH4, "On Chip Ram Read, but OCR is disabled. addr %x", addr);
|
|
return 0;
|
|
}
|
|
|
|
template <class T>
|
|
void DYNACALL WriteMem_area7_OCR(u32 addr, T data)
|
|
{
|
|
if (CCN_CCR.ORA == 1)
|
|
*(T *)&OnChipRAM[addr & OnChipRAM_MASK] = data;
|
|
else
|
|
INFO_LOG(SH4, "On Chip Ram Write, but OCR is disabled. addr %x", addr);
|
|
}
|
|
|
|
template <class T>
|
|
static void init_regs(T& regs)
|
|
{
|
|
for (auto& reg : regs)
|
|
{
|
|
reg.flags = RIO_NO_ACCESS;
|
|
reg.readFunctionAddr = &sh4io_read_noacc;
|
|
reg.writeFunctionAddr = &sh4io_write_noacc;
|
|
}
|
|
}
|
|
|
|
//Init/Res/Term
|
|
void sh4_mmr_init()
|
|
{
|
|
init_regs(CCN);
|
|
init_regs(UBC);
|
|
init_regs(BSC);
|
|
init_regs(DMAC);
|
|
init_regs(CPG);
|
|
init_regs(RTC);
|
|
init_regs(INTC);
|
|
init_regs(TMU);
|
|
init_regs(SCI);
|
|
init_regs(SCIF);
|
|
|
|
//initialise Register structs
|
|
bsc_init();
|
|
ccn_init();
|
|
cpg_init();
|
|
dmac_init();
|
|
intc_init();
|
|
rtc_init();
|
|
serial_init();
|
|
tmu_init();
|
|
ubc_init();
|
|
|
|
MMU_init();
|
|
}
|
|
|
|
void sh4_mmr_reset(bool hard)
|
|
{
|
|
for (auto& reg : CCN)
|
|
reg.reset();
|
|
for (auto& reg : UBC)
|
|
reg.reset();
|
|
for (auto& reg : BSC)
|
|
reg.reset();
|
|
for (auto& reg : DMAC)
|
|
reg.reset();
|
|
for (auto& reg : CPG)
|
|
reg.reset();
|
|
for (auto& reg : RTC)
|
|
reg.reset();
|
|
for (auto& reg : INTC)
|
|
reg.reset();
|
|
for (auto& reg : TMU)
|
|
reg.reset();
|
|
for (auto& reg : SCI)
|
|
reg.reset();
|
|
for (auto& reg : SCIF)
|
|
reg.reset();
|
|
|
|
OnChipRAM = {};
|
|
//Reset register values
|
|
bsc_reset(true);
|
|
ccn_reset(true);
|
|
cpg_reset();
|
|
dmac_reset();
|
|
intc_reset();
|
|
rtc_reset();
|
|
serial_reset(hard);
|
|
tmu_reset(true);
|
|
ubc_reset();
|
|
|
|
MMU_reset();
|
|
}
|
|
|
|
void sh4_mmr_term()
|
|
{
|
|
MMU_term();
|
|
|
|
ubc_term();
|
|
tmu_term();
|
|
serial_term();
|
|
rtc_term();
|
|
intc_term();
|
|
dmac_term();
|
|
cpg_term();
|
|
ccn_term();
|
|
bsc_term();
|
|
}
|
|
|
|
// AREA 7--Sh4 Regs
|
|
static _vmem_handler p4mmr_handler;
|
|
static _vmem_handler area7_ocr_handler;
|
|
|
|
void map_area7_init()
|
|
{
|
|
p4mmr_handler = _vmem_register_handler_Template(ReadMem_p4mmr, WriteMem_p4mmr);
|
|
area7_ocr_handler = _vmem_register_handler_Template(ReadMem_area7_OCR, WriteMem_area7_OCR);
|
|
}
|
|
|
|
void map_area7(u32 base)
|
|
{
|
|
// on-chip RAM: 7C000000-7FFFFFFF
|
|
if (base == 0x60)
|
|
_vmem_map_handler(area7_ocr_handler, 0x7C, 0x7F);
|
|
}
|
|
|
|
//P4
|
|
void map_p4()
|
|
{
|
|
//P4 Region :
|
|
_vmem_handler p4_handler = _vmem_register_handler_Template(ReadMem_P4, WriteMem_P4);
|
|
|
|
//register this before mmr and SQ so they overwrite it and handle em
|
|
//default P4 handler
|
|
//0xE0000000-0xFFFFFFFF
|
|
_vmem_map_handler(p4_handler, 0xE0, 0xFF);
|
|
|
|
//Store Queues -- Write only 32bit
|
|
_vmem_map_block(sq_both, 0xE0, 0xE0, 63);
|
|
_vmem_map_block(sq_both, 0xE1, 0xE1, 63);
|
|
_vmem_map_block(sq_both, 0xE2, 0xE2, 63);
|
|
_vmem_map_block(sq_both, 0xE3, 0xE3, 63);
|
|
|
|
_vmem_map_handler(p4mmr_handler, 0xFF, 0xFF);
|
|
}
|