252 lines
6.3 KiB
C++
252 lines
6.3 KiB
C++
/*
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Interrupt list caching and handling
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SH4 has a very flexible interrupt controller. In order to handle it efficiently, a sorted
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interrupt bitfield is build from the set interrupt priorities. Higher priorities get allocated
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into higher bits, and a simple mask is kept. In order to check for pending interrupts a simple
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!=0 test works, and to identify the pending interrupt bsr(pend) will give the sorted id. As
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this is a single cycle operation on most platforms, the interrupt checking/identification
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is very fast !
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*/
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#include "types.h"
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#include "sh4_interrupts.h"
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#include "sh4_core.h"
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#include "sh4_mmr.h"
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#include "oslib/oslib.h"
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#include "debug/gdb_server.h"
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//these are fixed
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const u16 IRLPriority = 0x0246;
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#define IRLP9 &IRLPriority,0
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#define IRLP11 &IRLPriority,4
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#define IRLP13 &IRLPriority,8
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#define GIPA(p) &INTC_IPRA.reg_data,4*p
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#define GIPB(p) &INTC_IPRB.reg_data,4*p
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#define GIPC(p) &INTC_IPRC.reg_data,4*p
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struct InterptSourceList_Entry
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{
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const u16* PrioReg;
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u32 Shift;
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u32 IntEvnCode;
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u32 GetPrLvl() const { return ((*PrioReg)>>Shift)&0xF; }
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};
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static const InterptSourceList_Entry InterruptSourceList[28] =
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{
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//IRL
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{IRLP9,0x320},//sh4_IRL_9 = KMIID(sh4_int,0x320,0),
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{IRLP11,0x360},//sh4_IRL_11 = KMIID(sh4_int,0x360,1),
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{IRLP13,0x3A0},//sh4_IRL_13 = KMIID(sh4_int,0x3A0,2),
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//HUDI
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{GIPC(0),0x600},//sh4_HUDI_HUDI = KMIID(sh4_int,0x600,3), /* H-UDI underflow */
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//GPIO (missing on dc ?)
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{GIPC(3),0x620},//sh4_GPIO_GPIOI = KMIID(sh4_int,0x620,4),
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//DMAC
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{GIPC(2),0x640},//sh4_DMAC_DMTE0 = KMIID(sh4_int,0x640,5),
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{GIPC(2),0x660},//sh4_DMAC_DMTE1 = KMIID(sh4_int,0x660,6),
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{GIPC(2),0x680},//sh4_DMAC_DMTE2 = KMIID(sh4_int,0x680,7),
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{GIPC(2),0x6A0},//sh4_DMAC_DMTE3 = KMIID(sh4_int,0x6A0,8),
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{GIPC(2),0x6C0},//sh4_DMAC_DMAE = KMIID(sh4_int,0x6C0,9),
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//TMU
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{GIPA(3),0x400},//sh4_TMU0_TUNI0 = KMIID(sh4_int,0x400,10), /* TMU0 underflow */
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{GIPA(2),0x420},//sh4_TMU1_TUNI1 = KMIID(sh4_int,0x420,11), /* TMU1 underflow */
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{GIPA(1),0x440},//sh4_TMU2_TUNI2 = KMIID(sh4_int,0x440,12), /* TMU2 underflow */
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{GIPA(1),0x460},//sh4_TMU2_TICPI2 = KMIID(sh4_int,0x460,13),
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//RTC
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{GIPA(0),0x480},//sh4_RTC_ATI = KMIID(sh4_int,0x480,14),
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{GIPA(0),0x4A0},//sh4_RTC_PRI = KMIID(sh4_int,0x4A0,15),
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{GIPA(0),0x4C0},//sh4_RTC_CUI = KMIID(sh4_int,0x4C0,16),
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//SCI
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{GIPB(1),0x4E0},//sh4_SCI1_ERI = KMIID(sh4_int,0x4E0,17),
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{GIPB(1),0x500},//sh4_SCI1_RXI = KMIID(sh4_int,0x500,18),
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{GIPB(1),0x520},//sh4_SCI1_TXI = KMIID(sh4_int,0x520,19),
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{GIPB(1),0x540},//sh4_SCI1_TEI = KMIID(sh4_int,0x540,29),
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//SCIF
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{GIPC(1),0x700},//sh4_SCIF_ERI = KMIID(sh4_int,0x700,21),
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{GIPC(1),0x720},//sh4_SCIF_RXI = KMIID(sh4_int,0x720,22),
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{GIPC(1),0x740},//sh4_SCIF_BRI = KMIID(sh4_int,0x740,23),
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{GIPC(1),0x760},//sh4_SCIF_TXI = KMIID(sh4_int,0x760,24),
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//WDT
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{GIPB(3),0x560},//sh4_WDT_ITI = KMIID(sh4_int,0x560,25),
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//REF
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{GIPB(2),0x580},//sh4_REF_RCMI = KMIID(sh4_int,0x580,26),
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{GIPA(2),0x5A0},//sh4_REF_ROVI = KMIID(sh4_int,0x5A0,27),
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};
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//Maps siid -> EventID
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alignas(64) u16 InterruptEnvId[32] = { 0 };
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//Maps piid -> 1<<siid
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alignas(64) u32 InterruptBit[32] = { 0 };
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//Maps sh4 interrupt level to inclusive bitfield
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alignas(64) u32 InterruptLevelBit[16] = { 0 };
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static bool Do_Interrupt(u32 intEvn);
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u32 interrupt_vpend; // Vector of pending interrupts
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u32 interrupt_vmask; // Vector of masked interrupts (-1 inhibits all interrupts)
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u32 decoded_srimask; // Vector of interrupts allowed by SR.IMSK (-1 inhibits all interrupts)
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//bit 0 ~ 27 : interrupt source 27:0. 0 = lowest level, 27 = highest level.
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static void recalc_pending_itrs()
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{
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Sh4cntx.interrupt_pend=interrupt_vpend&interrupt_vmask&decoded_srimask;
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}
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//Rebuild sorted interrupt id table (priorities were updated)
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void SIIDRebuild()
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{
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u32 cnt=0;
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u32 vpend=interrupt_vpend;
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u32 vmask=interrupt_vmask;
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interrupt_vpend=0;
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interrupt_vmask=0x00000000;
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//rebuild interrupt table
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for (u32 ilevel=0;ilevel<16;ilevel++)
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{
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for (u32 isrc=0;isrc<28;isrc++)
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{
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if (InterruptSourceList[isrc].GetPrLvl()==ilevel)
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{
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InterruptEnvId[cnt]=InterruptSourceList[isrc].IntEvnCode;
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u32 p=InterruptBit[isrc]&vpend;
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u32 m=InterruptBit[isrc]&vmask;
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InterruptBit[isrc]=1<<cnt;
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if (p)
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interrupt_vpend|=InterruptBit[isrc];
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if (m)
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interrupt_vmask|=InterruptBit[isrc];
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cnt++;
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}
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}
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InterruptLevelBit[ilevel]=(1<<cnt)-1;
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}
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SRdecode();
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}
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//Decode SR.IMSK into a interrupt mask, update and return the interrupt state
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bool SRdecode()
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{
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if (sr.BL)
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decoded_srimask=~0xFFFFFFFF;
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else
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decoded_srimask=~InterruptLevelBit[sr.IMASK];
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recalc_pending_itrs();
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return Sh4cntx.interrupt_pend;
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}
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int UpdateINTC()
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{
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if (!Sh4cntx.interrupt_pend)
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return 0;
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return Do_Interrupt(InterruptEnvId[bitscanrev(Sh4cntx.interrupt_pend)]);
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}
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void SetInterruptPend(InterruptID intr)
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{
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u32 piid= intr & InterruptPIIDMask;
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interrupt_vpend|=InterruptBit[piid];
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recalc_pending_itrs();
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}
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void ResetInterruptPend(InterruptID intr)
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{
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u32 piid= intr & InterruptPIIDMask;
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interrupt_vpend&=~InterruptBit[piid];
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recalc_pending_itrs();
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}
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void SetInterruptMask(InterruptID intr)
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{
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u32 piid= intr & InterruptPIIDMask;
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interrupt_vmask|=InterruptBit[piid];
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recalc_pending_itrs();
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}
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void ResetInterruptMask(InterruptID intr)
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{
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u32 piid= intr & InterruptPIIDMask;
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interrupt_vmask&=~InterruptBit[piid];
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recalc_pending_itrs();
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}
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static bool Do_Interrupt(u32 intEvn)
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{
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CCN_INTEVT = intEvn;
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ssr = sh4_sr_GetFull();
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spc = next_pc;
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sgr = r[15];
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sr.BL = 1;
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sr.MD = 1;
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sr.RB = 1;
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UpdateSR();
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next_pc = vbr + 0x600;
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debugger::subroutineCall();
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return true;
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}
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bool Do_Exception(u32 epc, u32 expEvn, u32 CallVect)
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{
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if (sr.BL != 0)
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throw FlycastException("Fatal: SH4 exception when blocked");
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CCN_EXPEVT = expEvn;
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ssr = sh4_sr_GetFull();
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spc = epc;
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sgr = r[15];
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sr.BL = 1;
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sr.MD = 1;
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sr.RB = 1;
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UpdateSR();
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next_pc = vbr + CallVect;
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debugger::subroutineCall();
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//printf("RaiseException: from %08X , pc errh %08X, %08X vect\n", spc, epc, next_pc);
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return true;
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}
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//Init/Res/Term
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void interrupts_init()
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{
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}
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void interrupts_reset()
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{
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//reset interrupts cache
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interrupt_vpend=0x00000000;
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interrupt_vmask=0xFFFFFFFF;
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decoded_srimask=0;
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for (u32 i=0;i<28;i++)
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InterruptBit[i]=1<<i;
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//rebuild the interrupts table
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SIIDRebuild();
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}
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void interrupts_term()
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{
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}
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