393 lines
8.6 KiB
C++
393 lines
8.6 KiB
C++
/*
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Copyright 2021 flyinghead
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This file is part of flycast.
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flycast is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 2 of the License, or
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(at your option) any later version.
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flycast is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with flycast. If not, see <https://www.gnu.org/licenses/>.
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*/
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#include "build.h"
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#if HOST_CPU == CPU_X86 && FEAT_DSPREC != DYNAREC_NONE
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#include <xbyak/xbyak.h>
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#include "dsp.h"
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#include "aica.h"
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#include "aica_if.h"
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#include "hw/mem/_vmem.h"
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namespace dsp
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{
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alignas(4096) static u8 CodeBuffer[32 * 1024]
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#if defined(_WIN32)
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;
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#elif defined(__unix__)
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__attribute__((section(".text")));
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#elif defined(__APPLE__)
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__attribute__((section("__TEXT,.text")));
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#else
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#error CodeBuffer code section unknown
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#endif
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static u8 *pCodeBuffer;
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class X86DSPAssembler : public Xbyak::CodeGenerator
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{
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public:
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X86DSPAssembler(u8 *code_buffer, size_t size) : Xbyak::CodeGenerator(size, code_buffer) {}
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void Compile(DSPState *DSP)
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{
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this->DSP = DSP;
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DEBUG_LOG(AICA_ARM, "X86DSPAssembler::Compile recompiling for x86 at %p", this->getCode());
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push(esi);
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push(edi);
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push(ebp);
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push(ebx);
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#ifndef _WIN32
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// 16-byte alignment
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sub(esp, 12);
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#endif
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const Xbyak::Reg32 INPUTS = esi; // 24 bits
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const Xbyak::Reg32 ACC = edi; // 26 bits - saved
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const Xbyak::Reg32 X = ebp; // 24 bits
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const Xbyak::Reg32 Y = ebx; // 13 bits
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xor_(ACC, ACC);
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mov(dword[&DSP->FRC_REG], 0);
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mov(dword[&DSP->Y_REG], 0);
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mov(dword[&DSP->ADRS_REG], 0);
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for (int step = 0; step < 128; ++step)
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{
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u32 *mpro = &DSPData->MPRO[step * 4];
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Instruction op;
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DecodeInst(mpro, &op);
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const u32 COEF = step;
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if (op.XSEL || op.YRL || (op.ADRL && op.SHIFT != 3))
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{
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if (op.IRA <= 0x1f)
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//INPUTS = DSP->MEMS[op.IRA];
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mov(INPUTS, dword[&DSP->MEMS[op.IRA]]);
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else if (op.IRA <= 0x2F)
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{
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//INPUTS = DSP->MIXS[op.IRA - 0x20] << 4; // MIXS is 20 bit
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mov(INPUTS, dword[&DSP->MIXS[op.IRA - 0x20]]);
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shl(INPUTS, 4);
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}
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else if (op.IRA <= 0x31)
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{
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//INPUTS = DSPData->EXTS[op.IRA - 0x30] << 8; // EXTS is 16 bits
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mov(INPUTS, dword[&DSPData->EXTS[op.IRA - 0x30]]);
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shl(INPUTS, 8);
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}
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else
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{
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xor_(INPUTS, INPUTS);
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}
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}
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if (op.IWT)
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{
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//DSP->MEMS[op.IWA] = MEMVAL[step & 3]; // MEMVAL was selected in previous MRD
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mov(eax, dword[&DSP->MEMVAL[step & 3]]);
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mov(dword[&DSP->MEMS[op.IWA]], eax);
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}
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// Operand sel
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// B
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if (!op.ZERO)
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{
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if (op.BSEL)
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//B = ACC;
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mov(dword[&DSP->B], ACC);
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else
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{
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//B = DSP->TEMP[(TRA + DSP->MDEC_CT) & 0x7F];
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mov(eax, dword[&DSP->MDEC_CT]);
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if (op.TRA)
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add(eax, op.TRA);
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and_(eax, 0x7f);
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mov(eax, dword[(size_t)&DSP->TEMP + eax * 4]);
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mov(dword[&DSP->B], eax);
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}
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if (op.NEGB)
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//B = 0 - B;
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neg(dword[&DSP->B]);
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}
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// X
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Xbyak::Reg32 X_alias = X;
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if (op.XSEL)
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//X = INPUTS;
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X_alias = INPUTS;
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else
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{
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//X = DSP->TEMP[(TRA + DSP->MDEC_CT) & 0x7F];
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if (!op.ZERO && !op.BSEL && !op.NEGB)
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mov(X, dword[&DSP->B]);
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else
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{
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mov(eax, dword[&DSP->MDEC_CT]);
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if (op.TRA)
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add(eax, op.TRA);
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and_(eax, 0x7f);
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mov(X, dword[(size_t)&DSP->TEMP + eax * 4]);
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}
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}
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// Y
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if (op.YSEL == 0)
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{
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//Y = FRC_REG;
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mov(Y, dword[&DSP->FRC_REG]);
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}
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else if (op.YSEL == 1)
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{
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//Y = DSPData->COEF[COEF] >> 3; //COEF is 16 bits
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movsx(Y, word[&DSPData->COEF[COEF]]);
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sar(Y, 3);
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}
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else if (op.YSEL == 2)
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{
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//Y = Y_REG >> 11;
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mov(Y, dword[&DSP->Y_REG]);
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sar(Y, 11);
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}
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else if (op.YSEL == 3)
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{
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//Y = (Y_REG >> 4) & 0x0FFF;
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mov(Y, dword[&DSP->Y_REG]);
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sar(Y, 4);
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and_(Y, 0x0fff);
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}
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if (op.YRL)
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//Y_REG = INPUTS;
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mov(dword[&DSP->Y_REG], INPUTS);
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if (op.TWT || op.FRCL || op.MWT || (op.ADRL && op.SHIFT == 3) || op.EWT)
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{
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// Shifter
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// There's a 1-step delay at the output of the X*Y + B adder. So we use the ACC value from the previous step.
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if (op.SHIFT == 0)
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{
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// SHIFTED = clamp(ACC, -0x80000, 0x7FFFF)
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cmp(ACC, 0xFF800000);
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mov(ecx, 0xFF800000);
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mov(eax, 0x007FFFFF);
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cmovge(ecx, ACC);
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cmp(ecx, 0x007FFFFF);
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cmovg(ecx, eax);
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}
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else if (op.SHIFT == 1)
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{
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//SHIFTED = ACC << 1; // x2 scale
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mov(edx, ACC);
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shl(edx, 1);
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// SHIFTED = clamp(SHIFTED, -0x80000, 0x7FFFF)
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cmp(edx, 0xFF800000);
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mov(ecx, 0xFF800000);
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mov(eax, 0x007FFFFF);
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cmovge(ecx, edx);
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cmp(ecx, 0x007FFFFF);
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cmovg(ecx, eax);
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}
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else if (op.SHIFT == 2)
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{
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//SHIFTED = ACC << 1; // x2 scale
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mov(ecx, ACC);
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shl(ecx, 1);
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}
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else if (op.SHIFT == 3)
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{
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//SHIFTED = ACC;
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mov(ecx, ACC);
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}
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// ecx contains SHIFTED
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}
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// ACCUM
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//ACC = (((s64)X * (s64)Y) >> 12) + B;
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mov(eax, X_alias);
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imul(Y);
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shl(edx, 20);
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shr(eax, 12);
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or_(eax, edx);
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mov(ACC, eax);
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if (!op.ZERO)
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add(ACC, dword[&DSP->B]);
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if (op.TWT)
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{
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//DSP->TEMP[(op.TWA + DSP->MDEC_CT) & 0x7F] = SHIFTED;
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mov(edx, dword[&DSP->MDEC_CT]);
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if (op.TWA)
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add(edx, op.TWA);
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and_(edx, 0x7f);
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mov(dword[(size_t)&DSP->TEMP + edx * 4], ecx);
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}
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if (op.FRCL)
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{
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mov(edx, ecx);
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if (op.SHIFT == 3)
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//FRC_REG = SHIFTED & 0x0FFF;
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and_(edx, 0xFFF);
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else
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//FRC_REG = SHIFTED >> 11;
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sar(edx, 11);
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mov(dword[&DSP->FRC_REG], edx);
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}
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if (step & 1)
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{
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if (op.MRD || op.MWT)
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{
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if ((op.ADRL && op.SHIFT == 3) || op.EWT)
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push(ecx);
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}
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const Xbyak::Reg32 ADDR = Y;
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if (op.MWT)
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{
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// *(u16 *)&aica_ram[ADDR & ARAM_MASK] = PACK(SHIFTED);
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// SHIFTED is in ecx
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call((const void *)PACK);
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CalculateADDR(ADDR, op);
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mov(ecx, (uintptr_t)&aica_ram[0]);
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mov(word[ecx + ADDR], ax);
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}
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if (op.MRD) // memory only allowed on odd. DoA inserts NOPs on even
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{
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//MEMVAL[(step + 2) & 3] = UNPACK(*(u16 *)&aica_ram[ADDR & ARAM_MASK]);
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CalculateADDR(ADDR, op);
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mov(ecx, (uintptr_t)&aica_ram[0]);
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movzx(ecx, word[ecx + ADDR]);
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call((const void *)UNPACK);
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mov(dword[&DSP->MEMVAL[(step + 2) & 3]], eax);
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}
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if (op.MRD || op.MWT)
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{
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if ((op.ADRL && op.SHIFT == 3) || op.EWT)
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pop(ecx);
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}
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}
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if (op.ADRL)
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{
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if (op.SHIFT == 3)
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{
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//ADRS_REG = SHIFTED >> 12;
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mov(dword[&DSP->ADRS_REG], ecx); // SHIFTED
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sar(dword[&DSP->ADRS_REG], 12);
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}
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else
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{
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//ADRS_REG = INPUTS >> 16;
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mov(dword[&DSP->ADRS_REG], INPUTS);
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sar(dword[&DSP->ADRS_REG], 16);
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}
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}
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if (op.EWT)
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{
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//DSPData->EFREG[op.EWA] = SHIFTED >> 8;
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sar(ecx, 8); // SHIFTED
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mov(dword[&DSPData->EFREG[op.EWA]], ecx);
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}
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}
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// DSP->MDEC_CT--
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mov(eax, DSP->RBL + 1);
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mov(ecx, dword[&DSP->MDEC_CT]);
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sub(ecx, 1);
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//if (dsp.MDEC_CT == 0)
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// dsp.MDEC_CT = dsp.RBL + 1; // RBL is ring buffer length - 1
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cmove(ecx, eax);
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mov(dword[&DSP->MDEC_CT], ecx);
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#ifndef _WIN32
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// 16-byte alignment
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add(esp, 12);
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#endif
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pop(ebx);
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pop(ebp);
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pop(edi);
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pop(esi);
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ret();
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ready();
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}
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private:
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void CalculateADDR(const Xbyak::Reg32 ADDR, const Instruction& op)
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{
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//u32 ADDR = DSPData->MADRS[op.MASA];
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mov(ADDR, dword[&DSPData->MADRS[op.MASA]]);
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if (op.ADREB)
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{
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//ADDR += ADRS_REG & 0x0FFF;
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mov(ecx, dword[&DSP->ADRS_REG]);
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and_(ecx, 0x0FFF);
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add(ADDR, ecx);
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}
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if (op.NXADR)
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//ADDR++;
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add(ADDR, 1);
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if (!op.TABLE)
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{
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//ADDR += DSP->MDEC_CT;
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add(ADDR, dword[&DSP->MDEC_CT]);
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//ADDR &= DSP->RBL;
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// RBL is constant for this program
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and_(ADDR, DSP->RBL);
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}
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else
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//ADDR &= 0xFFFF;
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and_(ADDR, 0xFFFF);
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//ADDR <<= 1; // Word -> byte address
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shl(ADDR, 1);
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//ADDR += DSP->RBP; // RBP is already a byte address
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// RBP is constant for this program
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add(ADDR, DSP->RBP);
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// ADDR & ARAM_MASK
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and_(ADDR, ARAM_MASK);
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}
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DSPState *DSP = nullptr;
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};
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void recompile()
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{
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X86DSPAssembler assembler(pCodeBuffer, sizeof(CodeBuffer));
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assembler.Compile(&state);
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}
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void recInit()
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{
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if (!vmem_platform_prepare_jit_block(CodeBuffer, sizeof(CodeBuffer), (void**)&pCodeBuffer))
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die("mprotect failed in x86 dsp");
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}
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void runStep()
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{
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((void (*)())&CodeBuffer[0])();
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}
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}
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#endif
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