698 lines
14 KiB
C++
698 lines
14 KiB
C++
/*
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This file is a mix of my code, Zezu's, and duno wtf-else (most likely ElSemi's ?)
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*/
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#include "types.h"
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#include "cfg/cfg.h"
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#include "hw/holly/sb.h"
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#include "hw/sh4/sh4_mem.h"
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#include "hw/holly/holly_intc.h"
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#include "hw/maple/maple_cfg.h"
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#include "naomi.h"
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#include "naomi_cart.h"
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#include "naomi_regs.h"
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u32 naomi_updates;
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//#define NAOMI_COMM
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static const u32 BoardID=0x980055AA;
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u32 GSerialBuffer=0,BSerialBuffer=0;
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int GBufPos=0,BBufPos=0;
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int GState=0,BState=0;
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int GOldClk=0,BOldClk=0;
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int BControl=0,BCmd=0,BLastCmd=0;
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int GControl=0,GCmd=0,GLastCmd=0;
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int SerStep=0,SerStep2=0;
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#ifdef NAOMI_COMM
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u32 CommOffset;
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u32* CommSharedMem;
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HANDLE CommMapFile=INVALID_HANDLE_VALUE;
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#endif
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/*
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El numero de serie solo puede contener:
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0-9 (0x30-0x39)
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A-H (0x41-0x48)
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J-N (0x4A-0x4E)
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P-Z (0x50-0x5A)
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*/
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unsigned char BSerial[]="\xB7"/*CRC1*/"\x19"/*CRC2*/"0123234437897584372973927387463782196719782697849162342198671923649";
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unsigned char GSerial[]="\xB7"/*CRC1*/"\x19"/*CRC2*/"0123234437897584372973927387463782196719782697849162342198671923649";
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unsigned int ShiftCRC(unsigned int CRC,unsigned int rounds)
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{
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const unsigned int Magic=0x10210000;
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unsigned int i;
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for(i=0;i<rounds;++i)
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{
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if(CRC&0x80000000)
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CRC=(CRC<<1)+Magic;
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else
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CRC=(CRC<<1);
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}
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return CRC;
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}
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unsigned short CRCSerial(unsigned char *Serial,unsigned int len)
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{
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unsigned int CRC=0xDEBDEB00;
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unsigned int i;
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for(i=0;i<len;++i)
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{
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unsigned char c=Serial[i];
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//CRC&=0xFFFFFF00;
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CRC|=c;
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CRC=ShiftCRC(CRC,8);
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}
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CRC=ShiftCRC(CRC,8);
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return (u16)(CRC>>16);
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}
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void NaomiInit()
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{
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u16 CRC;
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CRC=CRCSerial(BSerial+2,0x2E);
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BSerial[0]=(u8)(CRC>>8);
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BSerial[1]=(u8)(CRC);
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CRC=CRCSerial(GSerial+2,0x2E);
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GSerial[0]=(u8)(CRC>>8);
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GSerial[1]=(u8)(CRC);
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}
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void NaomiBoardIDWrite(const u16 Data)
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{
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int Dat=Data&8;
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int Clk=Data&4;
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int Rst=Data&0x20;
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int Sta=Data&0x10;
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if(Rst)
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{
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BState=0;
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BBufPos=0;
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}
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if(Clk!=BOldClk && !Clk) //Falling Edge clock
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{
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//State change
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if(BState==0 && Sta)
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BState=1;
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if(BState==1 && !Sta)
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BState=2;
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if((BControl&0xfff)==0xFF0) //Command mode
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{
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BCmd<<=1;
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if(Dat)
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BCmd|=1;
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else
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BCmd&=0xfffffffe;
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}
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//State processing
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if(BState==1) //LoadBoardID
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{
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BSerialBuffer=BoardID;
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BBufPos=0; //??
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}
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if(BState==2) //ShiftBoardID
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{
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BBufPos++;
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}
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}
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BOldClk=Clk;
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}
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u16 NaomiBoardIDRead()
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{
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if((BControl&0xff)==0xFE)
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return 0xffff;
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return (BSerialBuffer&(1<<(31-BBufPos)))?8:0;
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}
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static u32 AdaptByte(u8 val)
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{
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return val<<24;
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}
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void NaomiBoardIDWriteControl(const u16 Data)
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{
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if((Data&0xfff)==0xF30 && BCmd!=BLastCmd)
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{
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if((BCmd&0x81)==0x81)
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{
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SerStep2=(BCmd>>1)&0x3f;
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BSerialBuffer=0x00000000; //First block contains CRC
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BBufPos=0;
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}
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if((BCmd&0xff)==0x55) //Load Offset 0
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{
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BState=2;
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BBufPos=0;
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BSerialBuffer=AdaptByte(BSerial[8*SerStep2])>>1;
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}
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if((BCmd&0xff)==0xAA) //Load Offset 1
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{
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BState=2;
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BBufPos=0;
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BSerialBuffer=AdaptByte(BSerial[8*SerStep2+1]);
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}
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if((BCmd&0xff)==0x54)
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{
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BState=2;
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BBufPos=0;
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BSerialBuffer=AdaptByte(BSerial[8*SerStep2+2]);
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}
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if((BCmd&0xff)==0xA8)
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{
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BState=2;
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BBufPos=0;
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BSerialBuffer=AdaptByte(BSerial[8*SerStep2+3]);
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}
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if((BCmd&0xff)==0x50)
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{
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BState=2;
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BBufPos=0;
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BSerialBuffer=AdaptByte(BSerial[8*SerStep2+4]);
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}
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if((BCmd&0xff)==0xA0)
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{
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BState=2;
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BBufPos=0;
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BSerialBuffer=AdaptByte(BSerial[8*SerStep2+5]);
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}
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if((BCmd&0xff)==0x40)
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{
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BState=2;
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BBufPos=0;
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BSerialBuffer=AdaptByte(BSerial[8*SerStep2+6]);
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}
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if((BCmd&0xff)==0x80)
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{
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BState=2;
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BBufPos=0;
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BSerialBuffer=AdaptByte(BSerial[8*SerStep2+7]);
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}
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BLastCmd=BCmd;
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}
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BControl=Data;
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}
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void NaomiGameIDProcessCmd()
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{
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if(GCmd!=GLastCmd)
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{
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if((GCmd&0x81)==0x81)
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{
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SerStep=(GCmd>>1)&0x3f;
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GSerialBuffer=0x00000000; //First block contains CRC
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GBufPos=0;
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}
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if((GCmd&0xff)==0x55) //Load Offset 0
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{
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GState=2;
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GBufPos=0;
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GSerialBuffer=AdaptByte(GSerial[8*SerStep])>>0;
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}
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if((GCmd&0xff)==0xAA) //Load Offset 1
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{
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GState=2;
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GBufPos=0;
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GSerialBuffer=AdaptByte(GSerial[8*SerStep+1]);
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}
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if((GCmd&0xff)==0x54)
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{
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GState=2;
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GBufPos=0;
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GSerialBuffer=AdaptByte(GSerial[8*SerStep+2]);
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}
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if((GCmd&0xff)==0xA8)
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{
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GState=2;
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GBufPos=0;
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GSerialBuffer=AdaptByte(GSerial[8*SerStep+3]);
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}
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if((GCmd&0xff)==0x50)
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{
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GState=2;
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GBufPos=0;
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GSerialBuffer=AdaptByte(GSerial[8*SerStep+4]);
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}
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if((GCmd&0xff)==0xA0)
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{
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GState=2;
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GBufPos=0;
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GSerialBuffer=AdaptByte(GSerial[8*SerStep+5]);
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}
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if((GCmd&0xff)==0x40)
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{
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GState=2;
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GBufPos=0;
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GSerialBuffer=AdaptByte(GSerial[8*SerStep+6]);
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}
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if((GCmd&0xff)==0x80)
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{
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GState=2;
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GBufPos=0;
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GSerialBuffer=AdaptByte(GSerial[8*SerStep+7]);
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}
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GLastCmd=GCmd;
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}
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}
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void NaomiGameIDWrite(const u16 Data)
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{
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int Dat=Data&0x01;
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int Clk=Data&0x02;
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int Rst=Data&0x04;
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int Sta=Data&0x08;
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int Cmd=Data&0x10;
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if(Rst)
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{
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GState=0;
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GBufPos=0;
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}
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if(Clk!=GOldClk && !Clk) //Falling Edge clock
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{
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//State change
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if(GState==0 && Sta)
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GState=1;
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if(GState==1 && !Sta)
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GState=2;
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//State processing
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if(GState==1) //LoadBoardID
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{
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GSerialBuffer=BoardID;
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GBufPos=0; //??
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}
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if(GState==2) //ShiftBoardID
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GBufPos++;
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if(GControl!=Cmd && !Cmd)
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{
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NaomiGameIDProcessCmd();
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}
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GControl=Cmd;
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}
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if(Clk!=GOldClk && Clk) //Rising Edge clock
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{
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if(Cmd) //Command mode
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{
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GCmd<<=1;
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if(Dat)
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GCmd|=1;
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else
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GCmd&=0xfffffffe;
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GControl=Cmd;
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}
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}
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GOldClk=Clk;
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}
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u16 NaomiGameIDRead()
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{
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return (GSerialBuffer&(1<<(31-GBufPos)))?1:0;
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}
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u32 _ReadMem_naomi(u32 Addr, u32 sz)
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{
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verify(sz!=1);
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EMUERROR("naomi?WTF? ReadMem: %X, %d", Addr, sz);
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return 1;
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}
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void _WriteMem_naomi(u32 Addr, u32 data, u32 sz)
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{
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EMUERROR("naomi?WTF? WriteMem: %X <= %X, %d", Addr, data, sz);
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}
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//DIMM board
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//Uses interrupt ext#3 (holly_EXT_PCI)
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//status/flags ? 0x1 is some completion/init flag(?), 0x100 is the interrupt disable flag (?)
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//n1 bios rev g (n2/epr-23605b has similar behavior of not same):
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//3c=0x1E03
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//40=0
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//44=0
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//48=0
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//read 4c
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//wait for 4c not 0
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//4c=[4c]-1
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//Naomi 2 bios epr-23609
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//read 3c
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//wait 4c to be non 0
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//
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//SO the writes to 3c/stuff are not relaced with 4c '1'
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//If the dimm board has some internal cpu/pic logic
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//4c '1' seems to be the init done bit (?)
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//n1/n2 clears it after getting a non 0 value
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//n1 bios writes the value -1, meaning it expects the bit 0 to be set
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//.//
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u32 reg_dimm_3c; //IO window ! written, 0x1E03 some flag ?
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u32 reg_dimm_40; //parameters
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u32 reg_dimm_44; //parameters
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u32 reg_dimm_48; //parameters
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u32 reg_dimm_4c=0x11; //status/control reg ?
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bool NaomiDataRead = false;
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static bool aw_ram_test_skipped = false;
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void naomi_process(u32 r3c,u32 r40,u32 r44, u32 r48)
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{
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printf("Naomi process 0x%04X 0x%04X 0x%04X 0x%04X\n",r3c,r40,r44,r48);
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printf("Possible format 0 %d 0x%02X 0x%04X\n",r3c>>15,(r3c&0x7e00)>>9,r3c&0x1FF);
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printf("Possible format 1 0x%02X 0x%02X\n",(r3c&0xFF00)>>8,r3c&0xFF);
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u32 param=(r3c&0xFF);
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if (param==0xFF)
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{
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printf("invalid opcode or smth ?");
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}
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static int opcd=0;
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//else if (param!=3)
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if (opcd<255)
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{
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reg_dimm_3c=0x8000 | (opcd%12<<9) | (0x0);
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printf("new reg is 0x%X\n",reg_dimm_3c);
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asic_RaiseInterrupt(holly_EXP_PCI);
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printf("Interrupt raised\n");
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opcd++;
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}
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}
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u32 ReadMem_naomi(u32 Addr, u32 sz)
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{
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verify(sz!=1);
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if (unlikely(CurrentCartridge == NULL))
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{
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EMUERROR("called without cartridge\n");
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return 0xFFFF;
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}
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return CurrentCartridge->ReadMem(Addr, sz);
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}
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void WriteMem_naomi(u32 Addr, u32 data, u32 sz)
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{
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if (unlikely(CurrentCartridge == NULL))
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{
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EMUERROR("called without cartridge\n");
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return;
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}
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CurrentCartridge->WriteMem(Addr, data, sz);
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}
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//Dma Start
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void Naomi_DmaStart(u32 addr, u32 data)
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{
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if (SB_GDEN==0)
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{
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printf("Invalid (NAOMI)GD-DMA start, SB_GDEN=0.Ingoring it.\n");
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return;
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}
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NaomiDataRead = true;
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SB_GDST|=data&1;
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if (SB_GDST==1)
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{
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verify(1 == SB_GDDIR );
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SB_GDSTARD=SB_GDSTAR+SB_GDLEN;
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SB_GDLEND=SB_GDLEN;
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SB_GDST=0;
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if (CurrentCartridge != NULL)
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{
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u32 len = SB_GDLEN;
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u32 offset = 0;
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while (len > 0)
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{
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u32 block_len = len;
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void* ptr = CurrentCartridge->GetDmaPtr(block_len);
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WriteMemBlock_nommu_ptr(SB_GDSTAR + offset, (u32*)ptr, block_len);
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CurrentCartridge->AdvancePtr(block_len);
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len -= block_len;
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offset += block_len;
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}
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}
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asic_RaiseInterrupt(holly_GDROM_DMA);
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}
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}
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void Naomi_DmaEnable(u32 addr, u32 data)
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{
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SB_GDEN=data&1;
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if (SB_GDEN==0 && SB_GDST==1)
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{
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printf("(NAOMI)GD-DMA aborted\n");
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SB_GDST=0;
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}
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}
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void naomi_reg_Init()
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{
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#ifdef NAOMI_COMM
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CommMapFile = CreateFileMapping(
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INVALID_HANDLE_VALUE, // use paging file
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NULL, // default security
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PAGE_READWRITE, // read/write access
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0, // max. object size
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0x1000*4, // buffer size
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L"Global\\nullDC_103_naomi_comm"); // name of mapping object
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if (CommMapFile == NULL || CommMapFile==INVALID_HANDLE_VALUE)
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{
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_tprintf(TEXT("Could not create file mapping object (%d).\nTrying to open existing one\n"), GetLastError());
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CommMapFile=OpenFileMapping(
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FILE_MAP_ALL_ACCESS, // read/write access
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FALSE, // do not inherit the name
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L"Global\\nullDC_103_naomi_comm"); // name of mapping object
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}
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if (CommMapFile == NULL || CommMapFile==INVALID_HANDLE_VALUE)
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{
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_tprintf(TEXT("Could not open existing file either\n"), GetLastError());
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CommMapFile=INVALID_HANDLE_VALUE;
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}
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else
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{
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printf("NAOMI: Created \"Global\\nullDC_103_naomi_comm\"\n");
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CommSharedMem = (u32*) MapViewOfFile(CommMapFile, // handle to map object
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FILE_MAP_ALL_ACCESS, // read/write permission
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0,
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0,
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0x1000*4);
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if (CommSharedMem == NULL)
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{
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_tprintf(TEXT("Could not map view of file (%d).\n"),
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GetLastError());
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CloseHandle(CommMapFile);
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CommMapFile=INVALID_HANDLE_VALUE;
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}
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else
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printf("NAOMI: Mapped CommSharedMem\n");
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}
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#endif
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NaomiInit();
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sb_rio_register(SB_GDST_addr, RIO_WF, 0, &Naomi_DmaStart);
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sb_rio_register(SB_GDEN_addr, RIO_WF, 0, &Naomi_DmaEnable);
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}
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void naomi_reg_Term()
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{
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#ifdef NAOMI_COMM
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if (CommSharedMem)
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{
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UnmapViewOfFile(CommSharedMem);
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}
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if (CommMapFile!=INVALID_HANDLE_VALUE)
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{
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CloseHandle(CommMapFile);
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}
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#endif
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}
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void naomi_reg_Reset(bool Manual)
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{
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NaomiDataRead = false;
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aw_ram_test_skipped = false;
|
|
BLastCmd = 0;
|
|
}
|
|
|
|
void Update_naomi()
|
|
{
|
|
/*
|
|
if (naomi_updates>1)
|
|
{
|
|
naomi_updates--;
|
|
}
|
|
else if (naomi_updates==1)
|
|
{
|
|
naomi_updates=0;
|
|
asic_RaiseInterrupt(holly_EXP_PCI);
|
|
}*/
|
|
#if 0
|
|
if(!(SB_GDST&1) || !(SB_GDEN &1))
|
|
return;
|
|
|
|
//SB_GDST=0;
|
|
|
|
//TODO : Fix dmaor
|
|
u32 dmaor = DMAC_DMAOR.full;
|
|
|
|
u32 src = SB_GDSTARD,
|
|
len = SB_GDLEN-SB_GDLEND ;
|
|
|
|
//len=min(len,(u32)32);
|
|
// do we need to do this for gdrom dma ?
|
|
if(0x8201 != (dmaor &DMAOR_MASK)) {
|
|
printf("\n!\tGDROM: DMAOR has invalid settings (%X) !\n", dmaor);
|
|
//return;
|
|
}
|
|
if(len & 0x1F) {
|
|
printf("\n!\tGDROM: SB_GDLEN has invalid size (%X) !\n", len);
|
|
return;
|
|
}
|
|
|
|
if(0 == len)
|
|
{
|
|
printf("\n!\tGDROM: Len: %X, Abnormal Termination !\n", len);
|
|
}
|
|
u32 len_backup=len;
|
|
if( 1 == SB_GDDIR )
|
|
{
|
|
WriteMemBlock_nommu_ptr(dst,NaomiRom+(DmaOffset&0x7ffffff),size);
|
|
|
|
DmaCount=0xffff;
|
|
}
|
|
else
|
|
msgboxf(L"GDROM: SB_GDDIR %X (TO AICA WAVE MEM?)",MBX_ICONERROR, SB_GDDIR);
|
|
|
|
//SB_GDLEN = 0x00000000; //13/5/2k7 -> acording to docs these regs are not updated by hardware
|
|
//SB_GDSTAR = (src + len_backup);
|
|
|
|
SB_GDLEND+= len_backup;
|
|
SB_GDSTARD+= len_backup;//(src + len_backup)&0x1FFFFFFF;
|
|
|
|
if (SB_GDLEND==SB_GDLEN)
|
|
{
|
|
//printf("Streamed GDMA end - %d bytes trasnfered\n",SB_GDLEND);
|
|
SB_GDST=0;//done
|
|
// The DMA end interrupt flag
|
|
asic_RaiseInterrupt(holly_GDROM_DMA);
|
|
}
|
|
//Readed ALL sectors
|
|
if (read_params.remaining_sectors==0)
|
|
{
|
|
u32 buff_size =read_buff.cache_size - read_buff.cache_index;
|
|
//And all buffer :p
|
|
if (buff_size==0)
|
|
{
|
|
verify(!SB_GDST&1)
|
|
gd_set_state(gds_procpacketdone);
|
|
}
|
|
}
|
|
#endif
|
|
}
|
|
|
|
static u8 aw_maple_devs;
|
|
|
|
u32 libExtDevice_ReadMem_A0_006(u32 addr,u32 size) {
|
|
addr &= 0x7ff;
|
|
//printf("libExtDevice_ReadMem_A0_006 %d@%08x: %x\n", size, addr, mem600[addr]);
|
|
switch (addr)
|
|
{
|
|
case 0x280:
|
|
// 0x00600280 r 0000dcba
|
|
// a/b - 1P/2P coin inputs (JAMMA), active low
|
|
// c/d - 3P/4P coin inputs (EX. IO board), active low
|
|
//
|
|
// (ab == 0) -> BIOS skip RAM test
|
|
if (!aw_ram_test_skipped)
|
|
{
|
|
// Skip RAM test at startup
|
|
aw_ram_test_skipped = true;
|
|
return 0;
|
|
}
|
|
{
|
|
u8 coin_input = 0xF;
|
|
for (int slot = 0; slot < 4; slot++)
|
|
if (maple_atomiswave_coin_chute(slot))
|
|
coin_input &= ~(1 << slot);
|
|
return coin_input;
|
|
}
|
|
|
|
case 0x284: // Atomiswave maple devices
|
|
// ddcc0000 where cc/dd are the types of devices on maple bus 2 and 3:
|
|
// 0: regular AtomisWave controller
|
|
// 1: light gun
|
|
// 2,3: mouse/trackball
|
|
//printf("NAOMI 600284 read %x\n", aw_maple_devs);
|
|
return aw_maple_devs;
|
|
case 0x288:
|
|
// ??? Dolphin Blue
|
|
return 0;
|
|
|
|
}
|
|
EMUERROR("Unhandled read @ %x sz %d", addr, size);
|
|
return 0xFF;
|
|
}
|
|
|
|
void libExtDevice_WriteMem_A0_006(u32 addr,u32 data,u32 size) {
|
|
addr &= 0x7ff;
|
|
//printf("libExtDevice_WriteMem_A0_006 %d@%08x: %x\n", size, addr, data);
|
|
switch (addr)
|
|
{
|
|
case 0x284: // Atomiswave maple devices
|
|
printf("NAOMI 600284 write %x\n", data);
|
|
aw_maple_devs = data & 0xF0;
|
|
return;
|
|
case 0x288:
|
|
// ??? Dolphin Blue
|
|
return;
|
|
//case 0x28C: // Wheel force feedback?
|
|
default:
|
|
break;
|
|
}
|
|
EMUERROR("Unhandled write @ %x (%d): %x", addr, size, data);
|
|
}
|