151 lines
2.6 KiB
C++
151 lines
2.6 KiB
C++
/*
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* E_Extend.h
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*
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There are six basic instructions:
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XTAB16 Extend bits[23:16] and bits[7:0] of one register to 16 bits, and add corresponding halfwordsto the values in another register.
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XTAB Extend bits[ 7: 0] of one register to 32 bits, and add to the value in another register.
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XTAH Extend bits[15: 0] of one register to 32 bits, and add to the value in another register.
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XTB16 Extend bits[23:16] and bits[7:0] to 16 bits each.
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XTB Extend bits[ 7: 0] to 32 bits.
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XTH Extend bits[15: 0] to 32 bits.
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Each of the six instructions is available in the following variations, indicated by the prefixes shown:
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S Sign extension, with or without addition modulo 216 or 232.
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U Zero (unsigned) extension, with or without addition modulo 216 or 232.
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*/
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#pragma once
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namespace ARM
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{
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EAPI SXTAB16(eReg Rd, eReg Rn, eReg Rm, ConditionCode CC=AL)
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{
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DECL_Id(0x06800070);
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SET_CC;
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I |= (Rn&15)<<16;
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I |= (Rd&15)<<12;
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I |= (Rm&15);
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EMIT_I;
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}
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EAPI SXTAB(eReg Rd, eReg Rn, eReg Rm, ConditionCode CC=AL)
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{
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DECL_Id(0x06A00070);
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SET_CC;
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I |= (Rn&15)<<16;
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I |= (Rd&15)<<12;
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I |= (Rm&15);
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EMIT_I;
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}
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EAPI SXTAH(eReg Rd, eReg Rn, eReg Rm, ConditionCode CC=AL)
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{
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DECL_Id(0x06B00070);
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SET_CC;
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I |= (Rn&15)<<16;
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I |= (Rd&15)<<12;
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I |= (Rm&15);
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EMIT_I;
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}
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EAPI SXTB16(eReg Rd, eReg Rm, ConditionCode CC=AL)
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{
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DECL_Id(0x068F0070);
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SET_CC;
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I |= (Rd&15)<<12;
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I |= (Rm&15);
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EMIT_I;
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}
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EAPI SXTB(eReg Rd, eReg Rm, ConditionCode CC=AL)
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{
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DECL_Id(0x06AF0070);
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SET_CC;
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I |= (Rd&15)<<12;
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I |= (Rm&15);
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EMIT_I;
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}
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EAPI SXTH(eReg Rd, eReg Rm, ConditionCode CC=AL)
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{
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DECL_Id(0x06BF0070);
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SET_CC;
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I |= (Rd&15)<<12;
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I |= (Rm&15);
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EMIT_I;
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}
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EAPI UXTAB16(eReg Rd, eReg Rn, eReg Rm, ConditionCode CC=AL)
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{
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DECL_Id(0x06C00070);
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SET_CC;
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I |= (Rn&15)<<16;
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I |= (Rd&15)<<12;
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I |= (Rm&15);
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EMIT_I;
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}
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EAPI UXTAB(eReg Rd, eReg Rn, eReg Rm, ConditionCode CC=AL)
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{
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DECL_Id(0x06E00070);
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SET_CC;
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I |= (Rn&15)<<16;
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I |= (Rd&15)<<12;
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I |= (Rm&15);
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EMIT_I;
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}
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EAPI UXTAH(eReg Rd, eReg Rn, eReg Rm, ConditionCode CC=AL)
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{
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DECL_Id(0x06F00070);
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SET_CC;
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I |= (Rn&15)<<16;
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I |= (Rd&15)<<12;
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I |= (Rm&15);
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EMIT_I;
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}
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EAPI UXTB16(eReg Rd, eReg Rm, ConditionCode CC=AL)
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{
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DECL_Id(0x06CF0070);
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SET_CC;
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I |= (Rd&15)<<12;
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I |= (Rm&15);
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EMIT_I;
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}
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EAPI UXTB(eReg Rd, eReg Rm, ConditionCode CC=AL)
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{
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DECL_Id(0x06EF0070);
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SET_CC;
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I |= (Rd&15)<<12;
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I |= (Rm&15);
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EMIT_I;
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}
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EAPI UXTH(eReg Rd, eReg Rm, ConditionCode CC=AL)
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{
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DECL_Id(0x06FF0070);
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SET_CC;
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I |= (Rd&15)<<12;
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I |= (Rm&15);
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EMIT_I;
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}
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}; |