326 lines
9.2 KiB
C++
326 lines
9.2 KiB
C++
/*
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Dreamcast 'area 0' emulation
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Pretty much all peripheral registers are mapped here
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Routing is mostly handled here, as well as flash/SRAM emulation
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*/
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#include "types.h"
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#include "hw/sh4/sh4_mem.h"
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#include "sb_mem.h"
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#include "sb.h"
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#include "hw/pvr/pvr_mem.h"
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#include "hw/gdrom/gdrom_if.h"
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#include "hw/aica/aica_if.h"
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#include "hw/naomi/naomi.h"
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#include "hw/modem/modem.h"
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#include "hw/flashrom/flashrom.h"
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#include "reios/reios.h"
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RomChip sys_rom(BIOS_SIZE);
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#ifdef FLASH_SIZE
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DCFlashChip sys_nvmem(FLASH_SIZE);
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#endif
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#ifdef BBSRAM_SIZE
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SRamChip sys_nvmem(BBSRAM_SIZE);
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#endif
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bool LoadRomFiles(const string& root)
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{
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if (!sys_rom.Load(root, ROM_PREFIX, "%boot.bin;%boot.bin.bin;%bios.bin;%bios.bin.bin" ROM_NAMES, "bootrom"))
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{
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msgboxf("Unable to find bios in \n%s\nExiting...", MBX_ICONERROR, root.c_str());
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return false;
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}
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if (!sys_nvmem.Load(root, ROM_PREFIX, "%nvmem.bin;%flash_wb.bin;%flash.bin;%flash.bin.bin", "nvram"))
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{
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if (NVR_OPTIONAL)
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{
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printf("flash/nvmem is missing, will create new file...");
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}
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else
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{
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msgboxf("Unable to find flash/nvmem in \n%s\nExiting...", MBX_ICONERROR, root.c_str());
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return false;
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}
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}
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return true;
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}
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void SaveRomFiles(const string& root)
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{
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sys_nvmem.Save(root, ROM_PREFIX, "nvmem.bin", "nvmem");
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}
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bool LoadHle(const string& root) {
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if (!sys_nvmem.Load(root, ROM_PREFIX, "%nvmem.bin;%flash_wb.bin;%flash.bin;%flash.bin.bin", "nvram")) {
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printf("No nvmem loaded\n");
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}
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return reios_init(sys_rom.data, sys_nvmem.data);
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}
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#if (DC_PLATFORM == DC_PLATFORM_DREAMCAST) || (DC_PLATFORM == DC_PLATFORM_DEV_UNIT) || (DC_PLATFORM == DC_PLATFORM_NAOMI) || (DC_PLATFORM == DC_PLATFORM_NAOMI2)
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u32 ReadBios(u32 addr,u32 sz) { return sys_rom.Read(addr,sz); }
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void WriteBios(u32 addr,u32 data,u32 sz) { EMUERROR4("Write to [Boot ROM] is not possible, addr=%x,data=%x,size=%d",addr,data,sz); }
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u32 ReadFlash(u32 addr,u32 sz) { return sys_nvmem.Read(addr,sz); }
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void WriteFlash(u32 addr,u32 data,u32 sz) { sys_nvmem.Write(addr,data,sz); }
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#elif (DC_PLATFORM == DC_PLATFORM_ATOMISWAVE)
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u32 ReadFlash(u32 addr,u32 sz) { EMUERROR3("Read from [Flash ROM] is not possible, addr=%x,size=%d",addr,sz); return 0; }
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void WriteFlash(u32 addr,u32 data,u32 sz) { EMUERROR4("Write to [Flash ROM] is not possible, addr=%x,data=%x,size=%d",addr,data,sz); }
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u32 ReadBios(u32 addr,u32 sz)
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{
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if (!(addr&0x10000)) //upper 64 kb is flashrom
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{
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return sys_rom.Read(addr,sz);
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}
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else
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{
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return sys_nvmem.Read(addr,sz);
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}
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}
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void WriteBios(u32 addr,u32 data,u32 sz)
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{
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if (!(addr&0x10000)) //upper 64 kb is flashrom
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{
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EMUERROR4("Write to [Boot ROM] is not possible, addr=%x,data=%x,size=%d",addr,data,sz);
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}
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else
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{
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sys_nvmem.Write(addr,data,sz);
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}
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}
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#else
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#error unknown flash
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#endif
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//Area 0 mem map
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//0x00000000- 0x001FFFFF :MPX System/Boot ROM
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//0x00200000- 0x0021FFFF :Flash Memory
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//0x00400000- 0x005F67FF :Unassigned
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//0x005F6800- 0x005F69FF :System Control Reg.
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//0x005F6C00- 0x005F6CFF :Maple i/f Control Reg.
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//0x005F7000- 0x005F70FF :GD-ROM / NAOMI BD Reg.
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//0x005F7400- 0x005F74FF :G1 i/f Control Reg.
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//0x005F7800- 0x005F78FF :G2 i/f Control Reg.
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//0x005F7C00- 0x005F7CFF :PVR i/f Control Reg.
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//0x005F8000- 0x005F9FFF :TA / PVR Core Reg.
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//0x00600000- 0x006007FF :MODEM
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//0x00600800- 0x006FFFFF :G2 (Reserved)
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//0x00700000- 0x00707FFF :AICA- Sound Cntr. Reg.
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//0x00710000- 0x0071000B :AICA- RTC Cntr. Reg.
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//0x00800000- 0x00FFFFFF :AICA- Wave Memory
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//0x01000000- 0x01FFFFFF :Ext. Device
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//0x02000000- 0x03FFFFFF* :Image Area* 2MB
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//use unified size handler for registers
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//it really makes no sense to use different size handlers on em -> especially when we can use templates :p
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template<u32 sz, class T>
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T DYNACALL ReadMem_area0(u32 addr)
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{
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addr &= 0x01FFFFFF;//to get rid of non needed bits
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const u32 base=(addr>>16);
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//map 0x0000 to 0x01FF to Default handler
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//mirror 0x0200 to 0x03FF , from 0x0000 to 0x03FFF
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//map 0x0000 to 0x001F
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if (base<=0x001F)// :MPX System/Boot ROM
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{
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return ReadBios(addr,sz);
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}
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//map 0x0020 to 0x0021
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else if ((base>= 0x0020) && (base<= 0x0021)) // :Flash Memory
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{
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return ReadFlash(addr&0x1FFFF,sz);
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}
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//map 0x005F to 0x005F
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else if (likely(base==0x005F))
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{
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if ( /*&& (addr>= 0x00400000)*/ (addr<= 0x005F67FF)) // :Unassigned
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{
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EMUERROR2("Read from area0_32 not implemented [Unassigned], addr=%x",addr);
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}
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else if ((addr>= 0x005F7000) && (addr<= 0x005F70FF)) // GD-ROM
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{
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#if DC_PLATFORM == DC_PLATFORM_NAOMI
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return (T)ReadMem_naomi(addr,sz);
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#else
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return (T)ReadMem_gdrom(addr,sz);
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#endif
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}
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else if (likely((addr>= 0x005F6800) && (addr<=0x005F7CFF))) // /*:PVR i/f Control Reg.*/ -> ALL SB registers now
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{
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return (T)sb_ReadMem(addr,sz);
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}
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else if (likely((addr>= 0x005F8000) && (addr<=0x005F9FFF))) // :TA / PVR Core Reg.
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{
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if (sz != 4) return 0; // House of the Dead 2
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return (T)pvr_ReadReg(addr);
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}
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}
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//map 0x0060 to 0x0060
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else if ((base ==0x0060) /*&& (addr>= 0x00600000)*/ && (addr<= 0x006007FF)) // :MODEM
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{
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#if DC_PLATFORM == DC_PLATFORM_NAOMI || DC_PLATFORM == DC_PLATFORM_ATOMISWAVE
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return (T)libExtDevice_ReadMem_A0_006(addr, sz);
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#else
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return (T)ModemReadMem_A0_006(addr, sz);
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#endif
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}
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//map 0x0060 to 0x006F
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else if ((base >=0x0060) && (base <=0x006F) && (addr>= 0x00600800) && (addr<= 0x006FFFFF)) // :G2 (Reserved)
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{
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EMUERROR2("Read from area0_32 not implemented [G2 (Reserved)], addr=%x",addr);
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}
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//map 0x0070 to 0x0070
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else if ((base ==0x0070) /*&& (addr>= 0x00700000)*/ && (addr<=0x00707FFF)) // :AICA- Sound Cntr. Reg.
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{
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return (T) ReadMem_aica_reg(addr,sz);//libAICA_ReadReg(addr,sz);
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}
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//map 0x0071 to 0x0071
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else if ((base ==0x0071) /*&& (addr>= 0x00710000)*/ && (addr<= 0x0071000B)) // :AICA- RTC Cntr. Reg.
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{
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return (T)ReadMem_aica_rtc(addr,sz);
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}
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//map 0x0080 to 0x00FF
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else if ((base >=0x0080) && (base <=0x00FF) /*&& (addr>= 0x00800000) && (addr<=0x00FFFFFF)*/) // :AICA- Wave Memory
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{
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ReadMemArrRet(aica_ram.data,addr&ARAM_MASK,sz);
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}
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//map 0x0100 to 0x01FF
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else if ((base >=0x0100) && (base <=0x01FF) /*&& (addr>= 0x01000000) && (addr<= 0x01FFFFFF)*/) // :Ext. Device
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{
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return (T)libExtDevice_ReadMem_A0_010(addr,sz);
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}
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return 0;
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}
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template<u32 sz, class T>
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void DYNACALL WriteMem_area0(u32 addr,T data)
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{
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addr &= 0x01FFFFFF;//to get rid of non needed bits
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const u32 base=(addr>>16);
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//map 0x0000 to 0x001F
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if ((base <=0x001F) /*&& (addr<=0x001FFFFF)*/)// :MPX System/Boot ROM
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{
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WriteBios(addr,data,sz);
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}
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//map 0x0020 to 0x0021
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else if ((base >=0x0020) && (base <=0x0021) /*&& (addr>= 0x00200000) && (addr<= 0x0021FFFF)*/) // Flash Memory
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{
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WriteFlash(addr,data,sz);
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}
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//map 0x0040 to 0x005F -> actually, I'll only map 0x005F to 0x005F, b/c the rest of it is unspammed (left to default handler)
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//map 0x005F to 0x005F
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else if ( likely(base==0x005F) )
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{
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if (/*&& (addr>= 0x00400000) */ (addr<= 0x005F67FF)) // Unassigned
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{
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EMUERROR4("Write to area0_32 not implemented [Unassigned], addr=%x,data=%x,size=%d",addr,data,sz);
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}
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else if ((addr>= 0x005F7000) && (addr<= 0x005F70FF)) // GD-ROM
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{
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#if DC_PLATFORM == DC_PLATFORM_NAOMI || DC_PLATFORM == DC_PLATFORM_ATOMISWAVE
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WriteMem_naomi(addr,data,sz);
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#else
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WriteMem_gdrom(addr,data,sz);
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#endif
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}
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else if ( likely((addr>= 0x005F6800) && (addr<=0x005F7CFF)) ) // /*:PVR i/f Control Reg.*/ -> ALL SB registers
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{
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sb_WriteMem(addr,data,sz);
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}
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else if ( likely((addr>= 0x005F8000) && (addr<=0x005F9FFF)) ) // TA / PVR Core Reg.
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{
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verify(sz==4);
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pvr_WriteReg(addr,data);
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}
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}
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//map 0x0060 to 0x0060
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else if ((base ==0x0060) /*&& (addr>= 0x00600000)*/ && (addr<= 0x006007FF)) // MODEM
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{
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#if DC_PLATFORM == DC_PLATFORM_NAOMI || DC_PLATFORM == DC_PLATFORM_ATOMISWAVE
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libExtDevice_WriteMem_A0_006(addr, data, sz);
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#else
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ModemWriteMem_A0_006(addr, data, sz);
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#endif
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}
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//map 0x0060 to 0x006F
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else if ((base >=0x0060) && (base <=0x006F) && (addr>= 0x00600800) && (addr<= 0x006FFFFF)) // G2 (Reserved)
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{
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EMUERROR4("Write to area0_32 not implemented [G2 (Reserved)], addr=%x,data=%x,size=%d",addr,data,sz);
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}
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//map 0x0070 to 0x0070
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else if ((base >=0x0070) && (base <=0x0070) /*&& (addr>= 0x00700000)*/ && (addr<=0x00707FFF)) // AICA- Sound Cntr. Reg.
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{
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WriteMem_aica_reg(addr,data,sz);
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return;
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}
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//map 0x0071 to 0x0071
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else if ((base >=0x0071) && (base <=0x0071) /*&& (addr>= 0x00710000)*/ && (addr<= 0x0071000B)) // AICA- RTC Cntr. Reg.
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{
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WriteMem_aica_rtc(addr,data,sz);
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return;
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}
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//map 0x0080 to 0x00FF
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else if ((base >=0x0080) && (base <=0x00FF) /*&& (addr>= 0x00800000) && (addr<=0x00FFFFFF)*/) // AICA- Wave Memory
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{
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WriteMemArrRet(aica_ram.data,addr&ARAM_MASK,data,sz);
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return;
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}
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//map 0x0100 to 0x01FF
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else if ((base >=0x0100) && (base <=0x01FF) /*&& (addr>= 0x01000000) && (addr<= 0x01FFFFFF)*/) // Ext. Device
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{
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libExtDevice_WriteMem_A0_010(addr,data,sz);
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}
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return;
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}
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//Init/Res/Term
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void sh4_area0_Init()
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{
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sb_Init();
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}
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void sh4_area0_Reset(bool Manual)
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{
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sb_Reset(Manual);
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}
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void sh4_area0_Term()
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{
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sb_Term();
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}
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//AREA 0
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_vmem_handler area0_handler;
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void map_area0_init()
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{
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area0_handler = _vmem_register_handler_Template(ReadMem_area0,WriteMem_area0);
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}
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void map_area0(u32 base)
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{
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verify(base<0xE0);
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_vmem_map_handler(area0_handler,0x00|base,0x01|base);
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//0x0240 to 0x03FF mirrors 0x0040 to 0x01FF (no flashrom or bios)
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//0x0200 to 0x023F are unused
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_vmem_mirror_mapping(0x02|base,0x00|base,0x02);
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}
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