773 lines
13 KiB
C++
773 lines
13 KiB
C++
#include "types.h"
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#include <cmath>
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#include <cfloat>
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#include "sh4_opcodes.h"
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#include "../sh4_core.h"
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#include "../sh4_rom.h"
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#include "hw/sh4/sh4_mem.h"
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#define sh4op(str) void DYNACALL str (u32 op)
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#define GetN(str) ((str>>8) & 0xf)
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#define GetM(str) ((str>>4) & 0xf)
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#define GetImm4(str) ((str>>0) & 0xf)
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#define GetImm8(str) ((str>>0) & 0xff)
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#define GetImm12(str) ((str>>0) & 0xfff)
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#define GetDN(opc) ((op&0x0F00)>>9)
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#define GetDM(opc) ((op&0x00F0)>>5)
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#define pi (3.14159265f)
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void iNimp(const char*str);
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#define IS_DENORMAL(f) (((*(f))&0x7f800000) == 0)
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#define ReadMemU64(to,addr) to=ReadMem64(addr)
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#define ReadMemU32(to,addr) to=ReadMem32(addr)
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#define ReadMemS32(to,addr) to=(s32)ReadMem32(addr)
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#define ReadMemS16(to,addr) to=(u32)(s32)(s16)ReadMem16(addr)
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#define ReadMemS8(to,addr) to=(u32)(s32)(s8)ReadMem8(addr)
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//Base,offset format
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#define ReadMemBOU32(to,addr,offset) ReadMemU32(to,addr+offset)
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#define ReadMemBOS16(to,addr,offset) ReadMemS16(to,addr+offset)
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#define ReadMemBOS8(to,addr,offset) ReadMemS8(to,addr+offset)
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//Write Mem Macros
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#define WriteMemU64(addr,data) WriteMem64(addr,(u64)data)
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#define WriteMemU32(addr,data) WriteMem32(addr,(u32)data)
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#define WriteMemU16(addr,data) WriteMem16(addr,(u16)data)
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#define WriteMemU8(addr,data) WriteMem8(addr,(u8)data)
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//Base,offset format
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#define WriteMemBOU32(addr,offset,data) WriteMemU32(addr+offset,data)
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#define WriteMemBOU16(addr,offset,data) WriteMemU16(addr+offset,data)
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#define WriteMemBOU8(addr,offset,data) WriteMemU8(addr+offset,data)
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INLINE void Denorm32(float &value)
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{
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if (fpscr.DN)
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{
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u32* v=(u32*)&value;
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if (IS_DENORMAL(v) && (*v&0x7fFFFFFF)!=0)
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{
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*v&=0x80000000;
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//printf("Denormal ..\n");
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}
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if ((*v<=0x007FFFFF) && *v>0)
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{
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*v=0;
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INFO_LOG(INTERPRETER, "Fixed +denorm");
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}
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else if ((*v<=0x807FFFFF) && *v>0x80000000)
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{
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*v=0x80000000;
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INFO_LOG(INTERPRETER, "Fixed -denorm");
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}
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}
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}
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#define CHECK_FPU_32(v) v = fixNaN(v)
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#define CHECK_FPU_64(v)
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//fadd <FREG_M>,<FREG_N>
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sh4op(i1111_nnnn_mmmm_0000)
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{
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if (fpscr.PR == 0)
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{
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u32 n = GetN(op);
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u32 m = GetM(op);
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fr[n] += fr[m];
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CHECK_FPU_32(fr[n]);
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}
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else
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{
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u32 n = (op >> 9) & 0x07;
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u32 m = (op >> 5) & 0x07;
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double drn=GetDR(n), drm=GetDR(m);
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drn += drm;
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CHECK_FPU_64(drn);
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SetDR(n,drn);
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}
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}
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//fsub <FREG_M>,<FREG_N>
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sh4op(i1111_nnnn_mmmm_0001)
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{
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if (fpscr.PR == 0)
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{
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u32 n = GetN(op);
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u32 m = GetM(op);
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fr[n] -= fr[m];
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CHECK_FPU_32(fr[n]);
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}
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else
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{
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u32 n = (op >> 9) & 0x07;
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u32 m = (op >> 5) & 0x07;
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double drn=GetDR(n), drm=GetDR(m);
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drn-=drm;
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//dr[n] -= dr[m];
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SetDR(n,drn);
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}
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}
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//fmul <FREG_M>,<FREG_N>
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sh4op(i1111_nnnn_mmmm_0010)
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{
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if (fpscr.PR == 0)
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{
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u32 n = GetN(op);
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u32 m = GetM(op);
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fr[n] *= fr[m];
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CHECK_FPU_32(fr[n]);
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}
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else
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{
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u32 n = (op >> 9) & 0x07;
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u32 m = (op >> 5) & 0x07;
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double drn=GetDR(n), drm=GetDR(m);
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drn*=drm;
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//dr[n] *= dr[m];
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SetDR(n,drn);
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}
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}
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//fdiv <FREG_M>,<FREG_N>
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sh4op(i1111_nnnn_mmmm_0011)
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{
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if (fpscr.PR == 0)
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{
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u32 n = GetN(op);
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u32 m = GetM(op);
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fr[n] /= fr[m];
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CHECK_FPU_32(fr[n]);
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}
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else
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{
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u32 n = (op >> 9) & 0x07;
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u32 m = (op >> 5) & 0x07;
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double drn=GetDR(n), drm=GetDR(m);
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drn/=drm;
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SetDR(n,drn);
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}
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}
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//fcmp/eq <FREG_M>,<FREG_N>
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sh4op(i1111_nnnn_mmmm_0100)
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{
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if (fpscr.PR == 0)
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{
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u32 n = GetN(op);
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u32 m = GetM(op);
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sr.T = !!(fr[m] == fr[n]);
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}
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else
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{
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u32 n = (op >> 9) & 0x07;
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u32 m = (op >> 5) & 0x07;
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sr.T = !!(GetDR(m) == GetDR(n));
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}
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}
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//fcmp/gt <FREG_M>,<FREG_N>
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sh4op(i1111_nnnn_mmmm_0101)
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{
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if (fpscr.PR == 0)
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{
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u32 n = GetN(op);
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u32 m = GetM(op);
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if (fr[n] > fr[m])
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sr.T = 1;
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else
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sr.T = 0;
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}
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else
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{
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u32 n = (op >> 9) & 0x07;
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u32 m = (op >> 5) & 0x07;
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if (GetDR(n) > GetDR(m))
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sr.T = 1;
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else
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sr.T = 0;
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}
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}
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//All memory opcodes are here
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//fmov.s @(R0,<REG_M>),<FREG_N>
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sh4op(i1111_nnnn_mmmm_0110)
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{
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if (fpscr.SZ == 0)
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{
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u32 n = GetN(op);
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u32 m = GetM(op);
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ReadMemU32(fr_hex[n],r[m] + r[0]);
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}
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else
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{
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u32 n = GetN(op)>>1;
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u32 m = GetM(op);
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if (((op >> 8) & 0x1) == 0)
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{
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ReadMemU64(dr_hex[n],r[m] + r[0]);
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}
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else
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{
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ReadMemU64(xd_hex[n],r[m] + r[0]);
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}
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}
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}
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//fmov.s <FREG_M>,@(R0,<REG_N>)
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sh4op(i1111_nnnn_mmmm_0111)
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{
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if (fpscr.SZ == 0)
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{
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u32 n = GetN(op);
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u32 m = GetM(op);
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WriteMem32(r[0] + r[n], fr_hex[m]);
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}
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else
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{
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u32 n = GetN(op);
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u32 m = GetM(op)>>1;
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if (((op >> 4) & 0x1) == 0)
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{
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WriteMemU64(r[n] + r[0],dr_hex[m]);
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}
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else
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{
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WriteMemU64(r[n] + r[0],xd_hex[m]);
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}
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}
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}
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//fmov.s @<REG_M>,<FREG_N>
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sh4op(i1111_nnnn_mmmm_1000)
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{
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if (fpscr.SZ == 0)
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{
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u32 n = GetN(op);
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u32 m = GetM(op);
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ReadMemU32(fr_hex[n],r[m]);
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}
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else
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{
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u32 n = GetN(op)>>1;
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u32 m = GetM(op);
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if (((op >> 8) & 0x1) == 0)
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{
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ReadMemU64(dr_hex[n],r[m]);
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}
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else
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{
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ReadMemU64(xd_hex[n],r[m]);
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}
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}
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}
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//fmov.s @<REG_M>+,<FREG_N>
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sh4op(i1111_nnnn_mmmm_1001)
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{
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if (fpscr.SZ == 0)
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{
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u32 n = GetN(op);
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u32 m = GetM(op);
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ReadMemU32(fr_hex[n],r[m]);
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r[m] += 4;
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}
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else
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{
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u32 n = GetN(op)>>1;
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u32 m = GetM(op);
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if (((op >> 8) & 0x1) == 0)
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{
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ReadMemU64(dr_hex[n],r[m]);
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}
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else
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{
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ReadMemU64(xd_hex[n],r[m] );
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}
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r[m] += 8;
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}
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}
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//fmov.s <FREG_M>,@<REG_N>
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sh4op(i1111_nnnn_mmmm_1010)
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{
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if (fpscr.SZ == 0)
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{
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u32 n = GetN(op);
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u32 m = GetM(op);
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WriteMemU32(r[n], fr_hex[m]);
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}
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else
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{
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u32 n = GetN(op);
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u32 m = GetM(op)>>1;
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if (((op >> 4) & 0x1) == 0)
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{
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WriteMemU64(r[n], dr_hex[m]);
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}
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else
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{
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WriteMemU64(r[n], xd_hex[m]);
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}
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}
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}
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//fmov.s <FREG_M>,@-<REG_N>
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sh4op(i1111_nnnn_mmmm_1011)
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{
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if (fpscr.SZ == 0)
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{
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//iNimp("fmov.s <FREG_M>,@-<REG_N>");
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u32 n = GetN(op);
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u32 m = GetM(op);
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u32 addr = r[n] - 4;
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WriteMemU32(addr, fr_hex[m]);
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r[n] = addr;
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}
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else
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{
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u32 n = GetN(op);
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u32 m = GetM(op)>>1;
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u32 addr = r[n] - 8;
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if (((op >> 4) & 0x1) == 0)
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{
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WriteMemU64(addr, dr_hex[m]);
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}
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else
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{
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WriteMemU64(addr, xd_hex[m]);
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}
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r[n] = addr;
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}
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}
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//end of memory opcodes
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//fmov <FREG_M>,<FREG_N>
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sh4op(i1111_nnnn_mmmm_1100)
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{
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if (fpscr.SZ == 0)
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{
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u32 n = GetN(op);
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u32 m = GetM(op);
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fr[n] = fr[m];
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}
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else
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{
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u32 n = GetN(op)>>1;
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u32 m = GetM(op)>>1;
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switch ((op >> 4) & 0x11)
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{
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case 0x00:
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//dr[n] = dr[m];
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dr_hex[n] = dr_hex[m];
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break;
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case 0x01:
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//dr[n] = xd[m];
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dr_hex[n] = xd_hex[m];
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break;
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case 0x10:
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//xd[n] = dr[m];
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xd_hex[n] = dr_hex[m];
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break;
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case 0x11:
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//xd[n] = xd[m];
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xd_hex[n] = xd_hex[m];
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break;
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}
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}
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}
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//fabs <FREG_N>
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sh4op(i1111_nnnn_0101_1101)
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{
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int n=GetN(op);
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if (fpscr.PR ==0)
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fr_hex[n]&=0x7FFFFFFF;
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else
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fr_hex[(n&0xE)]&=0x7FFFFFFF;
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}
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//FSCA FPUL, DRn//F0FD//1111_nnn0_1111_1101
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sh4op(i1111_nnn0_1111_1101)
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{
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int n=GetN(op) & 0xE;
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//cosine(x) = sine(pi/2 + x).
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if (fpscr.PR==0)
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{
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u32 pi_index=fpul&0xFFFF;
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#ifdef NATIVE_FSCA
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float rads=pi_index/(65536.0f/2)*pi;
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fr[n + 0] = sinf(rads);
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fr[n + 1] = cosf(rads);
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CHECK_FPU_32(fr[n]);
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CHECK_FPU_32(fr[n+1]);
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#else
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fr[n + 0] = sin_table[pi_index].u[0];
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fr[n + 1] = sin_table[pi_index].u[1];
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#endif
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}
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else
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iNimp("FSCA : Double precision mode");
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}
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//FSRRA //1111_nnnn_0111_1101
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sh4op(i1111_nnnn_0111_1101)
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{
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// What about double precision?
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u32 n = GetN(op);
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if (fpscr.PR==0)
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{
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fr[n] = (float)(1/sqrtf(fr[n]));
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CHECK_FPU_32(fr[n]);
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}
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else
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iNimp("FSRRA : Double precision mode");
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}
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//fcnvds <DR_N>,FPUL
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sh4op(i1111_nnnn_1011_1101)
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{
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if (fpscr.PR == 1)
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{
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u32 n = (op >> 9) & 0x07;
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u32*p=&fpul;
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*((float*)p) = (float)GetDR(n);
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}
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else
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{
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iNimp("fcnvds <DR_N>,FPUL,m=0");
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}
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}
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//fcnvsd FPUL,<DR_N>
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sh4op(i1111_nnnn_1010_1101)
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{
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if (fpscr.PR == 1)
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{
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u32 n = (op >> 9) & 0x07;
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u32* p = &fpul;
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SetDR(n,(double)*((float*)p));
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}
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else
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{
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iNimp("fcnvsd FPUL,<DR_N>,m=0");
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}
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}
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//fipr <FV_M>,<FV_N>
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sh4op(i1111_nnmm_1110_1101)
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{
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int n=GetN(op)&0xC;
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int m=(GetN(op)&0x3)<<2;
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if (fpscr.PR == 0)
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{
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#if HOST_CPU == CPU_X86 || HOST_CPU == CPU_X64
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// multiplications are done with 28 bits of precision (53 - 25) and the final sum at 30 bits
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double idp = reduce_precision<25>((double)fr[n + 0] * fr[m + 0]);
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idp += reduce_precision<25>((double)fr[n + 1] * fr[m + 1]);
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idp += reduce_precision<25>((double)fr[n + 2] * fr[m + 2]);
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idp += reduce_precision<25>((double)fr[n + 3] * fr[m + 3]);
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fr[n + 3] = (float)fixNaN64(idp);
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#else
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float rv = fr[n + 0] * fr[m + 0];
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rv += fr[n + 1] * fr[m + 1];
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rv += fr[n + 2] * fr[m + 2];
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rv += fr[n + 3] * fr[m + 3];
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CHECK_FPU_32(rv);
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fr[n + 3] = rv;
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#endif
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}
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else
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{
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die("FIPR Precision=1");
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}
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}
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//fldi0 <FREG_N>
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sh4op(i1111_nnnn_1000_1101)
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{
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if (fpscr.PR!=0)
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return;
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u32 n = GetN(op);
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fr[n] = 0.0f;
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}
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//fldi1 <FREG_N>
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sh4op(i1111_nnnn_1001_1101)
|
|
{
|
|
if (fpscr.PR!=0)
|
|
return;
|
|
|
|
u32 n = GetN(op);
|
|
|
|
fr[n] = 1.0f;
|
|
}
|
|
|
|
//flds <FREG_N>,FPUL
|
|
sh4op(i1111_nnnn_0001_1101)
|
|
{
|
|
u32 n = GetN(op);
|
|
|
|
fpul = fr_hex[n];
|
|
}
|
|
|
|
//fsts FPUL,<FREG_N>
|
|
sh4op(i1111_nnnn_0000_1101)
|
|
{
|
|
u32 n = GetN(op);
|
|
fr_hex[n] = fpul;
|
|
}
|
|
|
|
//float FPUL,<FREG_N>
|
|
sh4op(i1111_nnnn_0010_1101)
|
|
{
|
|
if (fpscr.PR == 0)
|
|
{
|
|
u32 n = GetN(op);
|
|
fr[n] = (float)(int)fpul;
|
|
}
|
|
else
|
|
{
|
|
u32 n = (op >> 9) & 0x07;
|
|
SetDR(n, (double)(int)fpul);
|
|
}
|
|
}
|
|
|
|
|
|
//fneg <FREG_N>
|
|
sh4op(i1111_nnnn_0100_1101)
|
|
{
|
|
u32 n = GetN(op);
|
|
|
|
if (fpscr.PR ==0)
|
|
fr_hex[n]^=0x80000000;
|
|
else
|
|
fr_hex[(n&0xE)]^=0x80000000;
|
|
}
|
|
|
|
|
|
//frchg
|
|
sh4op(i1111_1011_1111_1101)
|
|
{
|
|
fpscr.FR = 1 - fpscr.FR;
|
|
|
|
UpdateFPSCR();
|
|
}
|
|
|
|
//fschg
|
|
sh4op(i1111_0011_1111_1101)
|
|
{
|
|
//iNimp("fschg");
|
|
fpscr.SZ = 1 - fpscr.SZ;
|
|
}
|
|
|
|
//fsqrt <FREG_N>
|
|
sh4op(i1111_nnnn_0110_1101)
|
|
{
|
|
if (fpscr.PR == 0)
|
|
{
|
|
u32 n = GetN(op);
|
|
|
|
fr[n] = sqrtf(fr[n]);
|
|
CHECK_FPU_32(fr[n]);
|
|
}
|
|
else
|
|
{
|
|
//Operation _can_ be done on sh4
|
|
u32 n = GetN(op)>>1;
|
|
|
|
SetDR(n,sqrt(GetDR(n)));
|
|
}
|
|
}
|
|
|
|
|
|
//ftrc <FREG_N>, FPUL
|
|
sh4op(i1111_nnnn_0011_1101)
|
|
{
|
|
if (fpscr.PR == 0)
|
|
{
|
|
u32 n = GetN(op);
|
|
fpul = (u32)(s32)min(fr[n], 2147483520.0f); // IEEE 754: 0x4effffff
|
|
|
|
// Intel CPUs convert out of range float numbers to 0x80000000. Manually set the correct sign
|
|
if (fpul == 0x80000000)
|
|
{
|
|
if (*(int *)&fr[n] > 0) // Using integer math to avoid issues with Inf and NaN
|
|
fpul--;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
u32 n = (op >> 9) & 0x07;
|
|
f64 f = GetDR(n);
|
|
fpul = (u32)(s32)f;
|
|
|
|
// Intel CPUs convert out of range float numbers to 0x80000000. Manually set the correct sign
|
|
if (fpul == 0x80000000)
|
|
{
|
|
if (*(s64 *)&f > 0) // Using integer math to avoid issues with Inf and NaN
|
|
fpul--;
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
//fmac <FREG_0>,<FREG_M>,<FREG_N>
|
|
sh4op(i1111_nnnn_mmmm_1110)
|
|
{
|
|
//iNimp("fmac <FREG_0>,<FREG_M>,<FREG_N>");
|
|
if (fpscr.PR==0)
|
|
{
|
|
u32 n = GetN(op);
|
|
u32 m = GetM(op);
|
|
|
|
fr[n] =(f32) ((f64)fr[n]+(f64)fr[0] * (f64)fr[m]);
|
|
CHECK_FPU_32(fr[n]);
|
|
}
|
|
else
|
|
{
|
|
iNimp("fmac <DREG_0>,<DREG_M>,<DREG_N>");
|
|
}
|
|
}
|
|
|
|
|
|
//ftrv xmtrx,<FV_N>
|
|
sh4op(i1111_nn01_1111_1101)
|
|
{
|
|
//iNimp("ftrv xmtrx,<FV_N>");
|
|
|
|
/*
|
|
XF[0] XF[4] XF[8] XF[12] FR[n] FR[n]
|
|
XF[1] XF[5] XF[9] XF[13] * FR[n+1] -> FR[n+1]
|
|
XF[2] XF[6] XF[10] XF[14] FR[n+2] FR[n+2]
|
|
XF[3] XF[7] XF[11] XF[15] FR[n+3] FR[n+3]
|
|
|
|
gota love linear algebra !
|
|
*/
|
|
|
|
u32 n=GetN(op)&0xC;
|
|
|
|
if (fpscr.PR==0)
|
|
{
|
|
#if HOST_CPU == CPU_X86 || HOST_CPU == CPU_X64
|
|
double v1 = reduce_precision<25>((double)xf[0] * fr[n + 0]) +
|
|
reduce_precision<25>((double)xf[4] * fr[n + 1]) +
|
|
reduce_precision<25>((double)xf[8] * fr[n + 2]) +
|
|
reduce_precision<25>((double)xf[12] * fr[n + 3]);
|
|
|
|
double v2 = reduce_precision<25>((double)xf[1] * fr[n + 0]) +
|
|
reduce_precision<25>((double)xf[5] * fr[n + 1]) +
|
|
reduce_precision<25>((double)xf[9] * fr[n + 2]) +
|
|
reduce_precision<25>((double)xf[13] * fr[n + 3]);
|
|
|
|
double v3 = reduce_precision<25>((double)xf[2] * fr[n + 0]) +
|
|
reduce_precision<25>((double)xf[6] * fr[n + 1]) +
|
|
reduce_precision<25>((double)xf[10] * fr[n + 2]) +
|
|
reduce_precision<25>((double)xf[14] * fr[n + 3]);
|
|
|
|
double v4 = reduce_precision<25>((double)xf[3] * fr[n + 0]) +
|
|
reduce_precision<25>((double)xf[7] * fr[n + 1]) +
|
|
reduce_precision<25>((double)xf[11] * fr[n + 2]) +
|
|
reduce_precision<25>((double)xf[15] * fr[n + 3]);
|
|
|
|
fr[n + 0] = (float)fixNaN64(v1);
|
|
fr[n + 1] = (float)fixNaN64(v2);
|
|
fr[n + 2] = (float)fixNaN64(v3);
|
|
fr[n + 3] = (float)fixNaN64(v4);
|
|
#else
|
|
float v1, v2, v3, v4;
|
|
|
|
v1 = xf[0] * fr[n + 0] +
|
|
xf[4] * fr[n + 1] +
|
|
xf[8] * fr[n + 2] +
|
|
xf[12] * fr[n + 3];
|
|
|
|
v2 = xf[1] * fr[n + 0] +
|
|
xf[5] * fr[n + 1] +
|
|
xf[9] * fr[n + 2] +
|
|
xf[13] * fr[n + 3];
|
|
|
|
v3 = xf[2] * fr[n + 0] +
|
|
xf[6] * fr[n + 1] +
|
|
xf[10] * fr[n + 2] +
|
|
xf[14] * fr[n + 3];
|
|
|
|
v4 = xf[3] * fr[n + 0] +
|
|
xf[7] * fr[n + 1] +
|
|
xf[11] * fr[n + 2] +
|
|
xf[15] * fr[n + 3];
|
|
|
|
CHECK_FPU_32(v1);
|
|
CHECK_FPU_32(v2);
|
|
CHECK_FPU_32(v3);
|
|
CHECK_FPU_32(v4);
|
|
|
|
fr[n + 0] = v1;
|
|
fr[n + 1] = v2;
|
|
fr[n + 2] = v3;
|
|
fr[n + 3] = v4;
|
|
#endif
|
|
}
|
|
else
|
|
{
|
|
iNimp("FTRV in dp mode");
|
|
}
|
|
}
|
|
|
|
|
|
void iNimp(const char*str)
|
|
{
|
|
WARN_LOG(INTERPRETER, "Unimplemented sh4 FPU instruction: %s", str);
|
|
//Sh4_int_Stop();
|
|
}
|