.. |
dyna
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cheats: don't rely on cheat count on load. Fix compile warnings
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2021-12-11 18:33:28 +01:00 |
interpr
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cheats: don't rely on cheat count on load. Fix compile warnings
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2021-12-11 18:33:28 +01:00 |
modules
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New serialize framework. Delay maple dma xfer
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2021-11-13 15:56:42 +01:00 |
fsca-table.h
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Moving code around, cleanups
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2013-12-28 22:20:08 +01:00 |
sh4_cache.h
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cheats: don't rely on cheat count on load. Fix compile warnings
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2021-12-11 18:33:28 +01:00 |
sh4_core.h
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mmu: add address cache to mem slow path. better fastmmu hashtable.
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2021-05-14 19:03:57 +02:00 |
sh4_core_regs.cpp
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arm32: replace old arm emitter with vixl
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2021-05-15 11:41:00 +02:00 |
sh4_if.h
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fix sh4 scheduler. use common cycle counter in sh4 context
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2021-10-07 16:18:32 +02:00 |
sh4_interpreter.h
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fix sh4 scheduler. use common cycle counter in sh4 context
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2021-10-07 16:18:32 +02:00 |
sh4_interrupts.cpp
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naomi: close cart on reset. sh4: replace some verify by throw
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2021-08-03 09:47:13 +02:00 |
sh4_interrupts.h
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clang-tidy: run readability-inconsistent-declaration-parameter-name and improve parameter names
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2021-03-15 19:52:54 +01:00 |
sh4_mem.cpp
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cheats: support for bit-level RA codes
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2021-10-12 17:28:01 +02:00 |
sh4_mem.h
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mmu: add address cache to mem slow path. better fastmmu hashtable.
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2021-05-14 19:03:57 +02:00 |
sh4_mmr.cpp
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cheats: support for bit-level RA codes
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2021-10-12 17:28:01 +02:00 |
sh4_mmr.h
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area 7 access to sh4 mm registers only through mmu translation
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2021-04-01 13:30:37 +02:00 |
sh4_opcode_list.cpp
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dynarec: fix CLRS and SETS ops
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2021-11-11 10:44:22 +01:00 |
sh4_opcode_list.h
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rename and clean up
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2019-08-30 23:35:10 +02:00 |
sh4_rom.cpp
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Split CFLAGS/CXXFLAGS on core.mk, warning fixes
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2014-05-12 20:53:43 +03:00 |
sh4_rom.h
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Moving code around, cleanups
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2013-12-28 22:20:08 +01:00 |
sh4_sched.cpp
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fix sh4 scheduler. use common cycle counter in sh4 context
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2021-10-07 16:18:32 +02:00 |
sh4_sched.h
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fix sh4 scheduler. use common cycle counter in sh4 context
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2021-10-07 16:18:32 +02:00 |