878 lines
16 KiB
C++
878 lines
16 KiB
C++
/*
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Sh4 internal register routing (P4 & 'area 7')
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*/
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#include "types.h"
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#include "sh4_mmr.h"
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#include "hw/mem/_vmem.h"
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#include "modules/mmu.h"
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#include "modules/ccn.h"
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#include "modules/modules.h"
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//64bytes of sq // now on context ~
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Array<u8> OnChipRAM;
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//All registers are 4 byte aligned
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Array<RegisterStruct> CCN(18,true); //CCN : 16 registers
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Array<RegisterStruct> UBC(9,true); //UBC : 9 registers
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Array<RegisterStruct> BSC(19,true); //BSC : 18 registers
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Array<RegisterStruct> DMAC(17,true); //DMAC : 17 registers
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Array<RegisterStruct> CPG(5,true); //CPG : 5 registers
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Array<RegisterStruct> RTC(16,true); //RTC : 16 registers
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Array<RegisterStruct> INTC(5,true); //INTC : 5 registers
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Array<RegisterStruct> TMU(12,true); //TMU : 12 registers
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Array<RegisterStruct> SCI(8,true); //SCI : 8 registers
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Array<RegisterStruct> SCIF(10,true); //SCIF : 10 registers
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Array<RegisterStruct> * const AllRegisters[] = { &CCN, &UBC, &BSC, &DMAC, &CPG, &RTC, &INTC, &TMU, &SCI, &SCIF };
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u32 sh4io_read_noacc(u32 addr)
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{
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INFO_LOG(SH4, "sh4io: Invalid read access @@ %08X", addr);
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return 0;
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}
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void sh4io_write_noacc(u32 addr, u32 data)
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{
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INFO_LOG(SH4, "sh4io: Invalid write access @@ %08X %08X", addr, data);
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//verify(false);
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}
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void sh4io_write_const(u32 addr, u32 data)
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{
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INFO_LOG(SH4, "sh4io: Const write ignored @@ %08X <- %08X", addr, data);
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}
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void sh4_rio_reg(Array<RegisterStruct>& arr, u32 addr, RegIO flags, u32 sz, RegReadAddrFP* rf, RegWriteAddrFP* wf)
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{
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u32 idx=(addr&255)/4;
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verify(idx<arr.Size);
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arr[idx].flags = flags | REG_ACCESS_32;
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if (flags == RIO_NO_ACCESS)
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{
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arr[idx].readFunctionAddr=&sh4io_read_noacc;
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arr[idx].writeFunctionAddr=&sh4io_write_noacc;
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}
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else if (flags == RIO_CONST)
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{
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arr[idx].writeFunctionAddr=&sh4io_write_const;
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}
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else
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{
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arr[idx].data32=0;
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if (flags & REG_RF)
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arr[idx].readFunctionAddr=rf;
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if (flags & REG_WF)
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arr[idx].writeFunctionAddr=wf==0?&sh4io_write_noacc:wf;
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}
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}
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template<u32 sz>
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u32 sh4_rio_read(Array<RegisterStruct>& sb_regs, u32 addr)
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{
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u32 offset = addr&255;
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#ifdef TRACE
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if (offset & 3/*(size-1)*/) //4 is min align size
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{
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INFO_LOG(SH4, "Unaligned System Bus register read");
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}
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#endif
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offset>>=2;
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#ifdef TRACE
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if (sb_regs[offset].flags & sz)
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{
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#endif
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if (!(sb_regs[offset].flags & REG_RF) )
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{
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if (sz==4)
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return sb_regs[offset].data32;
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else if (sz==2)
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return sb_regs[offset].data16;
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else
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return sb_regs[offset].data8;
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}
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else
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{
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return sb_regs[offset].readFunctionAddr(addr);
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}
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#ifdef TRACE
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}
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else
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{
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INFO_LOG(SH4, "ERROR [wrong size read on register]");
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}
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#endif
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return 0;
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}
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template<u32 sz>
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void sh4_rio_write(Array<RegisterStruct>& sb_regs, u32 addr, u32 data)
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{
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u32 offset = addr&255;
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#ifdef TRACE
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if (offset & 3/*(size-1)*/) //4 is min align size
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{
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INFO_LOG(SH4, "Unaligned System bus register write");
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}
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#endif
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offset>>=2;
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#ifdef TRACE
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if (sb_regs[offset].flags & sz)
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{
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#endif
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if (!(sb_regs[offset].flags & REG_WF) )
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{
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if (sz==4)
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sb_regs[offset].data32=data;
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else if (sz==2)
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sb_regs[offset].data16=(u16)data;
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else
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sb_regs[offset].data8=(u8)data;
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return;
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}
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else
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{
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//printf("RSW: %08X\n",addr);
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sb_regs[offset].writeFunctionAddr(addr,data);
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return;
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}
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#ifdef TRACE
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}
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else
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{
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INFO_LOG(SH4, "ERROR: Wrong size write on register - offset=%x, data=%x, size=%d",offset,data,sz);
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}
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#endif
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}
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//Region P4
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//Read P4
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template <class T>
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T DYNACALL ReadMem_P4(u32 addr)
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{
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switch((addr>>24)&0xFF)
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{
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case 0xE0:
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case 0xE1:
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case 0xE2:
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case 0xE3:
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INFO_LOG(SH4, "Unhandled p4 read [Store queue] 0x%x", addr);
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return 0;
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case 0xF0:
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return 0;
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case 0xF1:
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return 0;
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case 0xF2:
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{
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u32 entry=(addr>>8)&3;
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return ITLB[entry].Address.reg_data | (ITLB[entry].Data.V<<8);
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}
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case 0xF3:
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{
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u32 entry=(addr>>8)&3;
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return ITLB[entry].Data.reg_data;
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}
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case 0xF4:
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{
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//int W,Set,A;
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//W=(addr>>14)&1;
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//A=(addr>>3)&1;
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//Set=(addr>>5)&0xFF;
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//printf("Unhandled p4 read [Operand cache address array] %d:%d,%d 0x%x\n",Set,W,A,addr);
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return 0;
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}
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case 0xF5:
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return 0;
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case 0xF6:
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{
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u32 entry=(addr>>8)&63;
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u32 rv=UTLB[entry].Address.reg_data;
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rv|=UTLB[entry].Data.D<<9;
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rv|=UTLB[entry].Data.V<<8;
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return rv;
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}
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case 0xF7:
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{
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u32 entry=(addr>>8)&63;
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return UTLB[entry].Data.reg_data;
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}
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case 0xFF:
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INFO_LOG(SH4, "Unhandled p4 read [area7] 0x%x", addr);
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break;
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default:
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INFO_LOG(SH4, "Unhandled p4 read [Reserved] 0x%x", addr);
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break;
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}
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return 0;
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}
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//Write P4
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template <class T>
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void DYNACALL WriteMem_P4(u32 addr,T data)
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{
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/*if (((addr>>26)&0x7)==7)
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{
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WriteMem_area7(addr,data,sz);
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return;
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}*/
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switch((addr>>24)&0xFF)
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{
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case 0xE0:
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case 0xE1:
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case 0xE2:
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case 0xE3:
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INFO_LOG(SH4, "Unhandled p4 Write [Store queue] 0x%x", addr);
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break;
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case 0xF0:
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return;
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case 0xF1:
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return;
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case 0xF2:
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{
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u32 entry=(addr>>8)&3;
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ITLB[entry].Address.reg_data=data & 0xFFFFFCFF;
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ITLB[entry].Data.V=(data>>8) & 1;
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ITLB_Sync(entry);
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return;
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}
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case 0xF3:
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{
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u32 entry=(addr>>8)&3;
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if (addr&0x800000)
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{
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ITLB[entry].Assistance.reg_data = data & 0xf;
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}
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else
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{
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ITLB[entry].Data.reg_data=data;
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}
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ITLB_Sync(entry);
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return;
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}
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case 0xF4:
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{
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//int W,Set,A;
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//W=(addr>>14)&1;
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//A=(addr>>3)&1;
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//Set=(addr>>5)&0xFF;
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//printf("Unhandled p4 Write [Operand cache address array] %d:%d,%d 0x%x = %x\n",Set,W,A,addr,data);
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return;
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}
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case 0xF5:
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//printf("Unhandled p4 Write [Operand cache data array] 0x%x = %x\n",addr,data);
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return;
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case 0xF6:
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{
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if (addr&0x80)
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{
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#ifdef NO_MMU
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INFO_LOG(SH4, "Unhandled p4 Write [Unified TLB address array, Associative Write] 0x%x = %x", addr, data);
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#endif
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CCN_PTEH_type t;
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t.reg_data=data;
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u32 va=t.VPN<<10;
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#ifndef NO_MMU
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for (int i=0;i<64;i++)
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{
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if (mmu_match(va,UTLB[i].Address,UTLB[i].Data))
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{
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UTLB[i].Data.V=((u32)data>>8)&1;
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UTLB[i].Data.D=((u32)data>>9)&1;
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UTLB_Sync(i);
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}
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}
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for (int i=0;i<4;i++)
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{
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if (mmu_match(va,ITLB[i].Address,ITLB[i].Data))
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{
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ITLB[i].Data.V=((u32)data>>8)&1;
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ITLB[i].Data.D=((u32)data>>9)&1;
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ITLB_Sync(i);
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}
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}
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#endif
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}
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else
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{
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u32 entry=(addr>>8)&63;
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UTLB[entry].Address.reg_data=data & 0xFFFFFCFF;
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UTLB[entry].Data.D=(data>>9)&1;
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UTLB[entry].Data.V=(data>>8)&1;
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UTLB_Sync(entry);
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}
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return;
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}
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break;
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case 0xF7:
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{
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u32 entry=(addr>>8)&63;
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if (addr&0x800000)
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{
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UTLB[entry].Assistance.reg_data = data & 0xf;
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}
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else
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{
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UTLB[entry].Data.reg_data=data;
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}
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UTLB_Sync(entry);
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return;
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}
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case 0xFF:
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INFO_LOG(SH4, "Unhandled p4 Write [area7] 0x%x = %x", addr, data);
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break;
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default:
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INFO_LOG(SH4, "Unhandled p4 Write [Reserved] 0x%x", addr);
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break;
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}
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}
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//***********
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//Store Queue
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//***********
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//TODO : replace w/ mem mapped array
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//Read SQ
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template <u32 sz,class T>
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T DYNACALL ReadMem_sq(u32 addr)
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{
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if (sz!=4)
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{
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INFO_LOG(SH4, "Store Queue Error - only 4 byte read are possible[x%X]", addr);
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return 0xDE;
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}
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u32 united_offset=addr & 0x3C;
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return (T)*(u32*)&sq_both[united_offset];
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}
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//Write SQ
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template <u32 sz,class T>
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void DYNACALL WriteMem_sq(u32 addr,T data)
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{
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if (sz!=4)
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INFO_LOG(SH4, "Store Queue Error - only 4 byte writes are possible[x%X=0x%X]", addr, data);
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u32 united_offset=addr & 0x3C;
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*(u32*)&sq_both[united_offset]=data;
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}
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//***********
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//**Area 7**
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//***********
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#define OUT_OF_RANGE(reg) INFO_LOG(SH4, "Out of range on register %s index %x", reg, addr)
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//Read Area7
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template <typename T>
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T DYNACALL ReadMem_area7(u32 addr)
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{
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// TMU TCNT0 is by far the most frequently read register (x100 the second most read)
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if (likely(addr == 0xFFD8000C))
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{
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//return (T)sh4_rio_read<sizeof(T)>(TMU, 0xC);
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return (T)read_TMU_TCNTch(0);
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}
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else if (likely(addr == 0xFF000028))
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{
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return CCN_INTEVT;
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}
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u32 map_base = addr >> 16;
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addr &= 0xFF;
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switch (map_base & 0x1FFF)
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{
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case A7_REG_HASH(TMU_BASE_addr):
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if (addr <= 0x2C)
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{
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return (T)sh4_rio_read<sizeof(T)>(TMU, addr);
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}
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else
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{
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OUT_OF_RANGE("TMU");
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return 0;
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}
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break;
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case A7_REG_HASH(CCN_BASE_addr):
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if (addr <= 0x44)
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{
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return (T)sh4_rio_read<sizeof(T)>(CCN, addr);
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}
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else
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{
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OUT_OF_RANGE("CCN");
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return 0;
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}
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break;
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case A7_REG_HASH(DMAC_BASE_addr):
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if (addr <= 0x40)
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{
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return (T)sh4_rio_read<sizeof(T)>(DMAC, addr);
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}
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else
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{
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OUT_OF_RANGE("DMAC");
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return 0;
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}
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break;
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case A7_REG_HASH(INTC_BASE_addr):
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if (addr <= 0x10)
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{
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return (T)sh4_rio_read<sizeof(T)>(INTC, addr);
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}
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else
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{
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OUT_OF_RANGE("INTC");
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return 0;
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}
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break;
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case A7_REG_HASH(RTC_BASE_addr):
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if (addr <= 0x3C)
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{
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return (T)sh4_rio_read<sizeof(T)>(RTC, addr);
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}
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else
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{
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OUT_OF_RANGE("RTC");
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return 0;
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}
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break;
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case A7_REG_HASH(UBC_BASE_addr):
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if (addr <= 0x20)
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{
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return (T)sh4_rio_read<sizeof(T)>(UBC, addr);
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}
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else
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{
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OUT_OF_RANGE("UBC");
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return 0;
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}
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break;
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case A7_REG_HASH(BSC_BASE_addr):
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if (addr <= 0x48)
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{
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return (T)sh4_rio_read<sizeof(T)>(BSC, addr);
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}
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else
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{
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OUT_OF_RANGE("BSC");
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return 0;
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}
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break;
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case A7_REG_HASH(BSC_SDMR2_addr):
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//dram settings 2 / write only
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INFO_LOG(SH4, "Read from write-only registers [dram settings 2]");
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return 0;
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case A7_REG_HASH(BSC_SDMR3_addr):
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//dram settings 3 / write only
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INFO_LOG(SH4, "Read from write-only registers [dram settings 3]");
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return 0;
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case A7_REG_HASH(CPG_BASE_addr):
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if (addr <= 0x10)
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{
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return (T)sh4_rio_read<sizeof(T)>(CPG, addr);
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}
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else
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{
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OUT_OF_RANGE("CPG");
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return 0;
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}
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break;
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case A7_REG_HASH(SCI_BASE_addr):
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if (addr <= 0x1C)
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{
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return (T)sh4_rio_read<sizeof(T)>(SCI, addr);
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}
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else
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{
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OUT_OF_RANGE("SCI");
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return 0;
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}
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break;
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case A7_REG_HASH(SCIF_BASE_addr):
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if (addr <= 0x24)
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{
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return (T)sh4_rio_read<sizeof(T)>(SCIF, addr);
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}
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else
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{
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OUT_OF_RANGE("SCIF");
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return 0;
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}
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break;
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// Who really cares about ht-UDI? it's not existent on the Dreamcast IIRC
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case A7_REG_HASH(UDI_BASE_addr):
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switch(addr)
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{
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//UDI SDIR 0x1FF00000 0x1FF00000 16 0xFFFF Held Held Held Pclk
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case (UDI_SDIR_addr & 0xff):
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break;
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//UDI SDDR 0x1FF00008 0x1FF00008 32 Held Held Held Held Pclk
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case (UDI_SDDR_addr & 0xff):
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break;
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}
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break;
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}
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INFO_LOG(SH4, "Unknown Read from Area7 - addr=%x", (map_base << 16) | addr);
|
|
return 0;
|
|
}
|
|
|
|
//Write Area7
|
|
template <typename T>
|
|
void DYNACALL WriteMem_area7(u32 addr, T data)
|
|
{
|
|
if (likely(addr == 0xFF000038))
|
|
{
|
|
CCN_QACR_write<0>(addr, data);
|
|
return;
|
|
}
|
|
else if (likely(addr == 0xFF00003C))
|
|
{
|
|
CCN_QACR_write<1>(addr, data);
|
|
return;
|
|
}
|
|
|
|
u32 map_base = addr >> 16;
|
|
addr &= 0xFF;
|
|
switch (map_base & 0x1FFF)
|
|
{
|
|
case A7_REG_HASH(DMAC_BASE_addr):
|
|
if (addr <= 0x40)
|
|
{
|
|
sh4_rio_write<sizeof(T)>(DMAC, addr, data);
|
|
}
|
|
else
|
|
{
|
|
OUT_OF_RANGE("DMAC");
|
|
}
|
|
return;
|
|
|
|
case A7_REG_HASH(TMU_BASE_addr):
|
|
if (addr <= 0x2C)
|
|
{
|
|
sh4_rio_write<sizeof(T)>(TMU, addr, data);
|
|
}
|
|
else
|
|
{
|
|
OUT_OF_RANGE("TMU");
|
|
}
|
|
return;
|
|
|
|
case A7_REG_HASH(CCN_BASE_addr):
|
|
if (addr <= 0x3C)
|
|
{
|
|
sh4_rio_write<sizeof(T)>(CCN, addr, data);
|
|
}
|
|
else
|
|
{
|
|
OUT_OF_RANGE("CCN");
|
|
}
|
|
return;
|
|
|
|
case A7_REG_HASH(INTC_BASE_addr):
|
|
if (addr <= 0x0C)
|
|
{
|
|
sh4_rio_write<sizeof(T)>(INTC, addr, data);
|
|
}
|
|
else
|
|
{
|
|
OUT_OF_RANGE("INTC");
|
|
}
|
|
return;
|
|
|
|
case A7_REG_HASH(UBC_BASE_addr):
|
|
if (addr <= 0x20)
|
|
{
|
|
sh4_rio_write<sizeof(T)>(UBC, addr, data);
|
|
}
|
|
else
|
|
{
|
|
OUT_OF_RANGE("UBC");
|
|
}
|
|
return;
|
|
|
|
case A7_REG_HASH(BSC_BASE_addr):
|
|
if (addr <= 0x48)
|
|
{
|
|
sh4_rio_write<sizeof(T)>(BSC, addr, data);
|
|
}
|
|
else
|
|
{
|
|
OUT_OF_RANGE("BSC");
|
|
}
|
|
return;
|
|
case A7_REG_HASH(BSC_SDMR2_addr):
|
|
//dram settings 2 / write only
|
|
return;
|
|
|
|
case A7_REG_HASH(BSC_SDMR3_addr):
|
|
//dram settings 3 / write only
|
|
return;
|
|
|
|
case A7_REG_HASH(CPG_BASE_addr):
|
|
if (addr <= 0x10)
|
|
{
|
|
sh4_rio_write<sizeof(T)>(CPG, addr, data);
|
|
}
|
|
else
|
|
{
|
|
OUT_OF_RANGE("CPG");
|
|
}
|
|
return;
|
|
|
|
case A7_REG_HASH(RTC_BASE_addr):
|
|
if (addr <= 0x3C)
|
|
{
|
|
sh4_rio_write<sizeof(T)>(RTC, addr, data);
|
|
}
|
|
else
|
|
{
|
|
OUT_OF_RANGE("RTC");
|
|
}
|
|
return;
|
|
|
|
case A7_REG_HASH(SCI_BASE_addr):
|
|
if (addr <= 0x1C)
|
|
{
|
|
sh4_rio_write<sizeof(T)>(SCI, addr, data);
|
|
}
|
|
else
|
|
{
|
|
OUT_OF_RANGE("SCI");
|
|
}
|
|
return;
|
|
|
|
case A7_REG_HASH(SCIF_BASE_addr):
|
|
if (addr <= 0x24)
|
|
{
|
|
sh4_rio_write<sizeof(T)>(SCIF, addr, data);
|
|
}
|
|
else
|
|
{
|
|
OUT_OF_RANGE("SCIF");
|
|
}
|
|
return;
|
|
|
|
//who really cares about ht-udi ? it's not existent on dc iirc ..
|
|
case A7_REG_HASH(UDI_BASE_addr):
|
|
switch(addr)
|
|
{
|
|
//UDI SDIR 0xFFF00000 0x1FF00000 16 0xFFFF Held Held Held Pclk
|
|
case (UDI_SDIR_addr & 0xff):
|
|
break;
|
|
|
|
|
|
//UDI SDDR 0xFFF00008 0x1FF00008 32 Held Held Held Held Pclk
|
|
case (UDI_SDDR_addr & 0xff):
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
|
|
INFO_LOG(SH4, "Write to Area7 not implemented, addr=%x, data=%x", (map_base << 16) | addr, data);
|
|
}
|
|
|
|
|
|
//***********
|
|
//On Chip Ram
|
|
//***********
|
|
//Read OCR
|
|
template <typename T>
|
|
T DYNACALL ReadMem_area7_OCR_T(u32 addr)
|
|
{
|
|
if (CCN_CCR.ORA)
|
|
{
|
|
return *(T*)&OnChipRAM[addr & OnChipRAM_MASK];
|
|
}
|
|
else
|
|
{
|
|
INFO_LOG(SH4, "On Chip Ram Read, but OCR is disabled");
|
|
return 0xDE;
|
|
}
|
|
}
|
|
|
|
//Write OCR
|
|
template <typename T>
|
|
void DYNACALL WriteMem_area7_OCR_T(u32 addr, T data)
|
|
{
|
|
if (CCN_CCR.ORA)
|
|
{
|
|
*(T*)&OnChipRAM[addr & OnChipRAM_MASK] = data;
|
|
}
|
|
else
|
|
{
|
|
INFO_LOG(SH4, "On Chip Ram Write, but OCR is disabled");
|
|
}
|
|
}
|
|
|
|
|
|
//Init/Res/Term
|
|
void sh4_mmr_init()
|
|
{
|
|
OnChipRAM.Resize(OnChipRAM_SIZE,false);
|
|
|
|
for (u32 i=0;i<30;i++)
|
|
{
|
|
if (i<CCN.Size) sh4_rio_reg(CCN,CCN_BASE_addr+i*4,RIO_NO_ACCESS,32); //(16,true); //CCN : 14 registers
|
|
if (i<UBC.Size) sh4_rio_reg(UBC,UBC_BASE_addr+i*4,RIO_NO_ACCESS,32); //(9,true); //UBC : 9 registers
|
|
if (i<BSC.Size) sh4_rio_reg(BSC,BSC_BASE_addr+i*4,RIO_NO_ACCESS,32); //(19,true); //BSC : 18 registers
|
|
if (i<DMAC.Size) sh4_rio_reg(DMAC,DMAC_BASE_addr+i*4,RIO_NO_ACCESS,32); //(17,true); //DMAC : 17 registers
|
|
if (i<CPG.Size) sh4_rio_reg(CPG,CPG_BASE_addr+i*4,RIO_NO_ACCESS,32); //(5,true); //CPG : 5 registers
|
|
if (i<RTC.Size) sh4_rio_reg(RTC,RTC_BASE_addr+i*4,RIO_NO_ACCESS,32); //(16,true); //RTC : 16 registers
|
|
if (i<INTC.Size) sh4_rio_reg(INTC,INTC_BASE_addr+i*4,RIO_NO_ACCESS,32); //(4,true); //INTC : 4 registers
|
|
if (i<TMU.Size) sh4_rio_reg(TMU,TMU_BASE_addr+i*4,RIO_NO_ACCESS,32); //(12,true); //TMU : 12 registers
|
|
if (i<SCI.Size) sh4_rio_reg(SCI,SCI_BASE_addr+i*4,RIO_NO_ACCESS,32); //(8,true); //SCI : 8 registers
|
|
if (i<SCIF.Size) sh4_rio_reg(SCIF,SCIF_BASE_addr+i*4,RIO_NO_ACCESS,32); //(10,true); //SCIF : 10 registers
|
|
}
|
|
|
|
//initialise Register structs
|
|
bsc_init();
|
|
ccn_init();
|
|
cpg_init();
|
|
dmac_init();
|
|
intc_init();
|
|
rtc_init();
|
|
serial_init();
|
|
tmu_init();
|
|
ubc_init();
|
|
}
|
|
|
|
void sh4_mmr_reset(bool hard)
|
|
{
|
|
if (hard)
|
|
{
|
|
for (int i = 0; i < ARRAY_SIZE(AllRegisters); i++)
|
|
for (int j = 0; j < AllRegisters[i]->Size; j++)
|
|
(*AllRegisters[i])[j].reset();
|
|
}
|
|
OnChipRAM.Zero();
|
|
//Reset register values
|
|
bsc_reset(hard);
|
|
ccn_reset();
|
|
cpg_reset();
|
|
dmac_reset();
|
|
intc_reset();
|
|
rtc_reset();
|
|
serial_reset();
|
|
tmu_reset(hard);
|
|
ubc_reset();
|
|
}
|
|
|
|
void sh4_mmr_term()
|
|
{
|
|
//free any alloc'd resources [if any]
|
|
ubc_term();
|
|
tmu_term();
|
|
serial_term();
|
|
rtc_term();
|
|
intc_term();
|
|
dmac_term();
|
|
cpg_term();
|
|
ccn_term();
|
|
bsc_term();
|
|
OnChipRAM.Free();
|
|
}
|
|
//Mem map :)
|
|
|
|
//AREA 7--Sh4 Regs
|
|
_vmem_handler area7_handler;
|
|
|
|
_vmem_handler area7_orc_handler;
|
|
|
|
void map_area7_init()
|
|
{
|
|
//=_vmem_register_handler(ReadMem8_area7,ReadMem16_area7,ReadMem32_area7,
|
|
// WriteMem8_area7,WriteMem16_area7,WriteMem32_area7);
|
|
|
|
//default area7 handler
|
|
area7_handler= _vmem_register_handler_Template(ReadMem_area7, WriteMem_area7);
|
|
|
|
area7_orc_handler= _vmem_register_handler_Template(ReadMem_area7_OCR_T, WriteMem_area7_OCR_T);
|
|
}
|
|
void map_area7(u32 base)
|
|
{
|
|
//OCR @
|
|
//((addr>=0x7C000000) && (addr<=0x7FFFFFFF))
|
|
if (base==0x60)
|
|
_vmem_map_handler(area7_orc_handler,0x1C | base , 0x1F| base);
|
|
else
|
|
{
|
|
_vmem_map_handler(area7_handler,0x1C | base , 0x1F| base);
|
|
}
|
|
}
|
|
|
|
//P4
|
|
void map_p4()
|
|
{
|
|
//P4 Region :
|
|
_vmem_handler p4_handler = _vmem_register_handler_Template(ReadMem_P4, WriteMem_P4);
|
|
|
|
//register this before area7 and SQ , so they overwrite it and handle em :)
|
|
//default P4 handler
|
|
//0xE0000000-0xFFFFFFFF
|
|
_vmem_map_handler(p4_handler,0xE0,0xFF);
|
|
|
|
//Store Queues -- Write only 32bit
|
|
_vmem_map_block(sq_both,0xE0,0xE0,63);
|
|
_vmem_map_block(sq_both,0xE1,0xE1,63);
|
|
_vmem_map_block(sq_both,0xE2,0xE2,63);
|
|
_vmem_map_block(sq_both,0xE3,0xE3,63);
|
|
|
|
map_area7(0xE0);
|
|
}
|