527 lines
11 KiB
C++
527 lines
11 KiB
C++
/*
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Copyright 2023 flyinghead
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This file is part of Flycast.
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Flycast is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 2 of the License, or
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(at your option) any later version.
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Flycast is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Flycast. If not, see <https://www.gnu.org/licenses/>.
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*/
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#include "sh4_cycles.h"
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#include "modules/mmu.h"
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int Sh4Cycles::countCycles(u16 op)
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{
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sh4_opcodelistentry *opcode = OpDesc[op];
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int cycles = 0;
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#ifndef STRICT_MODE
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static const bool isMemOp[45] {
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false,
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false,
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true, // all mem moves, ldtlb, sts.l FPUL/FPSCR, @-Rn, lds.l @Rn+,FPUL
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true, // gbr-based load/store
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false,
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true, // tst.b #<imm8>, @(R0,GBR)
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true, // and/or/xor.b #<imm8>, @(R0,GBR)
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true, // tas.b @Rn
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false,
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false,
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false,
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false,
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true, // movca.l R0, @Rn
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false,
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false,
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false,
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false,
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true, // ldc.l @Rn+, VBR/SPC/SSR/Rn_Bank/DBR
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true, // ldc.l @Rn+, GBR/SGR
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true, // ldc.l @Rn+, SR
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false,
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false,
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true, // stc.l DBR/SR/GBR/VBR/SSR/SPC/Rn_Bank, @-Rn
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true, // stc.l SGR, @-Rn
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false,
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true, // lds.l @Rn+, PR
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false,
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true, // sts.l PR, @-Rn
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false,
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true, // lds.l @Rn+, MACH/MACL
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false,
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true, // sts.l MACH/MACL, @-Rn
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false,
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true, // lds.l @Rn+,FPSCR
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false,
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true, // mac.wl @Rm+,@Rn+
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};
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if (isMemOp[opcode->ex_type])
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{
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if (++memOps < 4)
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cycles = mmu_enabled() ? 5 : 2;
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}
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// TODO only for mem read?
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#endif
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if (lastUnit == CO
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|| opcode->unit == CO
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|| (lastUnit == opcode->unit && lastUnit != MT))
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{
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// cannot run in parallel
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lastUnit = opcode->unit;
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cycles += opcode->IssueCycles;
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}
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else
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{
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// can run in parallel
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lastUnit = CO;
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}
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return cycles * cpuRatio;
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}
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// TODO additional wait cycles depending on area?:
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// Area Wait cycles (not including external wait)
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// 0 3
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// 1 VRAM 3
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// 2 reserved 3
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// 3 SDRAM 0 CAS latency 3
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// 4 TA,YUV 1
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// 5 G2 ext 3
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// 6 reserved 3
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int Sh4Cycles::readExternalAccessCycles(u32 addr, u32 size)
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{
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if ((addr & 0xfc000000) == 0xe0000000)
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// store queues
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return 0;
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addr &= 0x1fffffff;
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switch (addr >> 26)
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{
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case 0:
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if (!settings.platform.isAtomiswave())
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{
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// Dreamcast, Naomi
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if (addr < 0x00200000)
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{
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// system rom
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switch (size)
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{
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case 1:
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return 44;
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case 2:
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return 63;
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case 4:
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return 99;
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case 32:
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default:
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return 618;
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}
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}
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if (addr < 0x00200000 + settings.platform.flash_size)
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{
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// flash
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switch (size)
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{
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case 1:
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return 41;
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case 2:
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return 55;
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case 4:
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return 83;
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case 32:
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default:
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return 489;
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}
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}
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}
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else
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{
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// Atomiswave
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if (addr < 0x00020000 || (addr >= 0x00200000 && addr < 0x00200000 + settings.platform.flash_size))
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{
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// flash
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switch (size)
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{
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case 1:
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return 41;
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case 2:
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return 55;
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case 4:
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return 83;
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case 32:
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default:
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return 489;
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}
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}
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}
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addr &= 0x01ffffff;
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if (addr >= 0x005f6800 && addr <= 0x005f69ff)
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{
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// holly system control regs
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if (size != 4)
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INFO_LOG(SH4, "holly system reg: Invalid read size %d @ %07x", size, addr);
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return 5;
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}
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if (addr >= 0x005f6c00 && addr <= 0x005f6cff)
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{
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// maple regs
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if (size != 4)
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INFO_LOG(SH4, "maple reg: Invalid read size %d @ %07x", size, addr);
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return 22;
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}
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if (addr >= 0x005f7000 && addr <= 0x005f70ff)
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{
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if (settings.platform.isArcade())
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// naomi/aw cart
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return 20; // ???
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else
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{
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// gd-rom
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if (size > 2)
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INFO_LOG(SH4, "gd-rom: Invalid read size %d @ %07x", size, addr);
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return 39;
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}
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}
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if (addr >= 0x005f7400 && addr <= 0x005f74ff)
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{
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// G1 I/F control regs
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if (settings.platform.isConsole())
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{
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if (size != 4) // unknown for aw/naomi
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INFO_LOG(SH4, "G1 I/F: Invalid read size %d @ %07x", size, addr);
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}
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else
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{
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// unknown for aw/naomi. seeing size 1 and 4 at least
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}
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return 24;
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}
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if (addr >= 0x005f7800 && addr <= 0x005f78ff)
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{
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// G2 I/F control regs
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if (size != 4)
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INFO_LOG(SH4, "G2 I/F: Invalid read size %d @ %07x", size, addr);
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return 38;
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}
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if (addr >= 0x005f7c00 && addr <= 0x005f7cff)
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{
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// PVR I/F control regs
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if (size != 4)
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INFO_LOG(SH4, "PVR I/F: Invalid read size %d @ %07x", size, addr);
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return 24;
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}
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if (addr >= 0x005f8000 && addr <= 0x005f9fff)
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{
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// TA/PVR core control regs, Palette RAM, fog table
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if (size != 4)
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// TODO 32-byte access allowed for palette and fog tables?
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INFO_LOG(SH4, "PVR/TA core: Invalid read size %d @ %07x", size, addr);
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return 34;
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}
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if (addr >= 0x00600000 && addr <= 0x006007ff)
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{
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if (settings.platform.isConsole())
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// AW registers
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return 20; // ???
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else
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{
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// modem
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if (size != 1)
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INFO_LOG(SH4, "modem: Invalid read size %d @ %07x", size, addr);
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return 67;
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}
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}
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if (addr >= 0x00700000 && addr <= 0x00ffffff)
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{
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// aica regs and ram
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if (size < 4)
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INFO_LOG(SH4, "aica: Invalid read size %d @ %07x", size, addr);
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return 40 * size / 4; // undocumented
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}
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if (addr >= 0x01000000 && addr <= 0x01ffffff)
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{
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// G2 external area
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switch (size)
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{
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case 1:
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case 2:
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return 56;
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case 4:
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return 60;
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case 32:
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default:
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return 84;
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}
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}
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break;
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case 1:
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// VRAM
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switch (size)
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{
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case 1:
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INFO_LOG(SH4, "vram: Invalid read size 1 @ %07x", addr);
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return 41;
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case 2:
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case 4:
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return 41;
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case 32:
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default:
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return 61;
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}
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case 2:
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// Area 2
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INFO_LOG(SH4, "Invalid read from area 2 @ %07x", addr);
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return 60;
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case 3:
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// System RAM
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return 7; // or 12 if row miss TODO average?
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case 4:
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// TA FIFO
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if (size != 32)
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INFO_LOG(SH4, "Invalid read size %d from area 4 (TA FIFO) @ %07x", size, addr);
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if ((addr >= 0x11000000 && addr <= 0x11ffffff) || (addr >= 0x13000000 && addr <= 0x13ffffff))
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// VRAM (64 bits)
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return 61; // undocumented
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break;
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case 5:
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// Ext device
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switch (size)
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{
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case 1:
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case 2:
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return 56;
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case 4:
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return 60;
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case 32:
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default:
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return 84;
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}
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case 6:
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// Area 6
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INFO_LOG(SH4, "Invalid read from area 6 @ %07x", addr);
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return 60;
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case 7:
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// SH4 registers
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return 0;
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}
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INFO_LOG(SH4, "Unmapped read @ %08x", addr);
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return 60;
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}
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int Sh4Cycles::writeExternalAccessCycles(u32 addr, u32 size)
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{
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if ((addr & 0xfc000000) == 0xe0000000)
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// store queues
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return 0;
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addr &= 0x1fffffff;
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switch (addr >> 26)
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{
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case 0:
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if (!settings.platform.isAtomiswave())
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{
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if (addr < 0x00200000)
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{
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// system rom
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INFO_LOG(SH4, "Invalid write to rom @ %07x", addr);
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return 99;
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}
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if (addr < 0x00200000 + settings.platform.flash_size)
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{
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// flash
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if (size != 1)
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INFO_LOG(SH4, "flashrom: Invalid write size %d @ %07x", size, addr);
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return 28;
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}
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}
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else
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{
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if (addr < 0x00020000)
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{
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// flash
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if (size != 1)
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INFO_LOG(SH4, "flashrom: Invalid write size %d @ %07x", size, addr);
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return 28;
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}
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if (addr >= 0x00200000 && addr < 0x00200000 + settings.platform.flash_size)
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{
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// nvmem
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return 14; // ????
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}
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}
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addr &= 0x01ffffff;
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if (addr >= 0x005f6800 && addr <= 0x005f69ff)
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{
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// holly system control regs
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if (size != 4)
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INFO_LOG(SH4, "holly system reg: Invalid write size %d @ %07x", size, addr);
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return 5;
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}
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if (addr >= 0x005f6c00 && addr <= 0x005f6cff)
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{
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// maple regs
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if (size != 4)
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INFO_LOG(SH4, "maple reg: Invalid write size %d @ %07x", size, addr);
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return 12;
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}
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if (addr >= 0x005f7000 && addr <= 0x005f70ff)
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{
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if (settings.platform.isArcade())
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// naomi/aw cart
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return 14; // ???
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else
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{
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// gd-rom
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if (size > 2)
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INFO_LOG(SH4, "gd-rom: Invalid write size %d @ %07x", size, addr);
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return 28;
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}
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}
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if (addr >= 0x005f7400 && addr <= 0x005f74ff)
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{
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// G1 I/F control regs
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if (size != 4)
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INFO_LOG(SH4, "G1 I/F: Invalid write size %d @ %07x", size, addr);
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return 12;
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}
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if (addr >= 0x005f7800 && addr <= 0x005f78ff)
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{
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// G2 I/F control regs
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if (size != 4)
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INFO_LOG(SH4, "G2 I/F: Invalid write size %d @ %07x", size, addr);
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return 12;
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}
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if (addr >= 0x005f7c00 && addr <= 0x005f7cff)
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{
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// PVR I/F control regs
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if (size != 4)
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INFO_LOG(SH4, "PVR I/F: Invalid write size %d @ %07x", size, addr);
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return 12;
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}
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if (addr >= 0x005f8000 && addr <= 0x005f9fff)
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{
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// TA/PVR core control regs, Palette RAM, fog table
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if (size != 4)
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// TODO 32-byte access allowed for palette and fog tables?
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INFO_LOG(SH4, "PVR/TA core: Invalid write size %d @ %07x", size, addr);
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return 14;
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}
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if (addr >= 0x00600000 && addr <= 0x006007ff)
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{
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if (settings.platform.isAtomiswave())
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// AW registers
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return 14; // ???
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else
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{
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// modem
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if (size != 1)
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INFO_LOG(SH4, "modem: Invalid write size %d @ %07x", size, addr);
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return 44;
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}
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}
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if (addr >= 0x00700000 && addr <= 0x00ffffff)
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{
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// aica regs and ram
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if (size < 4)
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INFO_LOG(SH4, "aica: Invalid read size %d @ %07x", size, addr);
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return 12 * size / 4; // undocumented
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}
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if (addr >= 0x01000000 && addr <= 0x01ffffff)
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{
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// G2 external area
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switch (size)
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{
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case 1:
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case 2:
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case 4:
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return 28;
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case 32:
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default:
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return 52;
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}
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}
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break;
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case 1:
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// VRAM
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switch (size)
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{
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case 1:
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INFO_LOG(SH4, "vram: Invalid write size 1 @ %07x", addr);
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return 12;
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case 2:
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case 4:
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return 12;
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case 32:
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default:
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return 38;
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}
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case 2:
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// Area 2
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INFO_LOG(SH4, "Invalid read to area 2 @ %07x", addr);
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return 12;
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case 3:
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// System RAM
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return 4; // or 9 if row miss TODO average?
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case 4:
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// TA FIFO
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if (size != 32)
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INFO_LOG(SH4, "Invalid write size %d to area 4 (TA FIFO) @ %07x", size, addr);
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if ((addr >= 0x10000000 && addr <= 0x107fffff) || (addr >= 0x12000000 && addr <= 0x127fffff))
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// TA polygon data
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return 7; // undocumented
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if ((addr >= 0x10800000 && addr <= 0x10ffffff) || (addr >= 0x12800000 && addr <= 0x12ffffff))
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// YUV converter
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return 9; // 858 cycles for 3072 bytes (YUV420)
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if ((addr >= 0x11000000 && addr <= 0x11ffffff) || (addr >= 0x13000000 && addr <= 0x13ffffff))
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// VRAM (64 bits)
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return 5; // 8 for 32-bit access (LMMODE0/1)
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break;
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case 5:
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// Ext device
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switch (size)
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{
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case 1:
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case 2:
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case 4:
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return 28;
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case 32:
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default:
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return 52;
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}
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case 6:
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// Area 6
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INFO_LOG(SH4, "Invalid write to area 6 @ %07x", addr);
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return 14;
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case 7:
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// SH4 registers
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return 0;
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}
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INFO_LOG(SH4, "Unmapped read @ %08x", addr);
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return 14;
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}
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