Commit Graph

6 Commits

Author SHA1 Message Date
flyinghead 46044c068b cheats: don't rely on cheat count on load. Fix compile warnings 2021-12-11 18:33:28 +01:00
Flyinghead 8f80bcb159 New serialize framework. Delay maple dma xfer
New serialize framework. Refactor serialization into modules.
Maple dma xfer must not be executed immediately. Delay until interrupt
is raised.
Fixes Geist Force freeze at start.
2021-11-13 15:56:42 +01:00
Flyinghead b3de6a166d area 7 access to sh4 mm registers only through mmu translation
on-chip ram area isn't translated in both user and supervisor modes
vmem: return 0 for non-mapped region reads
Fixes dolphin blue crash/freeze. Issue #62
Fixes Resident Evil - Code Veronica X (Chris) floor 1F crash
2021-04-01 13:30:37 +02:00
Flyinghead 74aae115ee sh4: implement C and WT MMU bits in cache. Use mem handlers everywhere
o/icache use C and WT bits from mmu to override cache and copy back
settings (fixes Windows CE)
move mem handlers setup out of mmu into sh4_mem. Call in dc_resume and
detect transitions interp -> dynarec to flush caches.
fix ssa tlb miss exception wih slow mmu
2020-06-24 15:23:47 +02:00
Flyinghead 22dcb1ec99 sh4 ocache implementation. IC and OC address/data read/write in P4
ignore SR.RB in user mode instead of forcing it 0
add STRICT_MODE to enable ocache in interpreter
don't flush mmu table when enabling it
fix fixNan64()
2020-06-12 17:35:14 +02:00
Flyinghead 333df13fce sh4 icache implementation. move aica out of sh4/interp.
revert to original div1 impl
serialize rtc clock value
cmake fixes: asan and logging options, -no-pie on x64/linux
2020-06-09 12:02:01 +02:00