Eliminate duplicate code for immediate memory read/write in all dynarecs
Simplify PREF to use do_sqw_nommu even for simple SQ remap
Check for address errors before mmu translation
Get rid of unneeded template params in mmu translation funcs
Option to reg alloc 64-bit regs in two host regs. Used when FPSCR.SZ ==
1 (64-bit reg and memory transfers.) Enabled for arm, arm64 and x64
(windows only) dynarecs.
Don't fallback to interpreter when FPSCR.PR==1 (double precision) for
FMOV, FLDS and FLTS.
add dynarec implementations for missing ldc and stc ops with sr and
fpscr
add dynarec implementation for tas.b
canonical implementation for div1
delete unused reg_old_sr_status and reg_sr
o/icache use C and WT bits from mmu to override cache and copy back
settings (fixes Windows CE)
move mem handlers setup out of mmu into sh4_mem. Call in dc_resume and
detect transitions interp -> dynarec to flush caches.
fix ssa tlb miss exception wih slow mmu
All ram pages containing code are write protected. In that case, no need
for block checks. Memory reads in the same block(s) can also be executed
at compile time and the results propagated as constants.
When a write is detected in a protected area, the corresponding blocks
are discarded and recompiled using traditional (slow) block checks.
Backported the blkmap code finding change from upstream.
Use smart pointers for block management to avoid reference issues.
Added WriteAfterWrite ssa pass
Fixed crash in ssa ConstProp pass when op list is modified
Flyinghead