aica: implement pitch LFO and LPF envelope
simplify channel serialization optimize aica channel reg write callbacks
This commit is contained in:
Flyinghead
parent
afc8398628
commit
fbdbd2491d
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@ -41,17 +41,8 @@ void WriteReg(u32 addr,u32 data)
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//Channel data
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u32 chan = addr >> 7;
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u32 reg = addr & 0x7F;
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if (sz==1)
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{
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WriteMemArr(aica_reg,addr,data,1);
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WriteChannelReg8(chan,reg);
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}
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else
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{
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WriteMemArr(aica_reg,addr,data,2);
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WriteChannelReg8(chan,reg);
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WriteChannelReg8(chan,reg+1);
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}
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WriteMemArr(aica_reg, addr, data, sz);
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WriteChannelReg(chan, reg, sz);
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return;
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}
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@ -1,3 +1,23 @@
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/*
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This file is part of reicast.
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reicast is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 2 of the License, or
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(at your option) any later version.
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reicast is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with reicast. If not, see <https://www.gnu.org/licenses/>.
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Some PLFO and FEG code from Highly_Theoretical lib by Neill Corlett
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(https://github.com/kode54/Highly_Theoretical)
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*/
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#include "sgc_if.h"
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#include "dsp.h"
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#include "aica_mem.h"
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@ -10,6 +30,7 @@ using namespace std;
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//#define CLIP_WARN
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#define key_printf(...) DEBUG_LOG(AICA, __VA_ARGS__)
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#define aeg_printf(...) DEBUG_LOG(AICA, __VA_ARGS__)
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#define feg_printf(...) DEBUG_LOG(AICA, __VA_ARGS__)
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#define step_printf(...) DEBUG_LOG(AICA, __VA_ARGS__)
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#ifdef CLIP_WARN
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@ -23,30 +44,36 @@ using namespace std;
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s32 volume_lut[16];
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//255 -> mute
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//Converts Send levels to TL-compatible values (DISDL, etc)
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u32 SendLevel[16]={255,14<<3,13<<3,12<<3,11<<3,10<<3,9<<3,8<<3,7<<3,6<<3,5<<3,4<<3,3<<3,2<<3,1<<3,0<<3};
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static const u32 SendLevel[16] =
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{
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255, 14 << 3, 13 << 3, 12 << 3, 11 << 3, 10 << 3, 9 << 3, 8 << 3,
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7 << 3, 6 << 3, 5 << 3, 4 << 3, 3 << 3, 2 << 3, 1 << 3, 0 << 3
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};
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s32 tl_lut[256 + 768]; //xx.15 format. >=255 is muted
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//in ms :)
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double AEG_Attack_Time[]=
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static const double AEG_Attack_Time[]=
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{
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-1,-1,8100.0,6900.0,6000.0,4800.0,4000.0,3400.0,3000.0,2400.0,2000.0,1700.0,1500.0,
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1200.0,1000.0,860.0,760.0,600.0,500.0,430.0,380.0,300.0,250.0,220.0,190.0,150.0,130.0,110.0,95.0,
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76.0,63.0,55.0,47.0,38.0,31.0,27.0,24.0,19.0,15.0,13.0,12.0,9.4,7.9,6.8,6.0,4.7,3.8,3.4,3.0,2.4,
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2.0,1.8,1.6,1.3,1.1,0.93,0.85,0.65,0.53,0.44,0.40,0.35,0.0,0.0
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};
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double AEG_DSR_Time[]=
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static const double AEG_DSR_Time[]=
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{ -1,-1,118200.0,101300.0,88600.0,70900.0,59100.0,50700.0,44300.0,35500.0,29600.0,25300.0,22200.0,17700.0,
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14800.0,12700.0,11100.0,8900.0,7400.0,6300.0,5500.0,4400.0,3700.0,3200.0,2800.0,2200.0,1800.0,1600.0,1400.0,1100.0,
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920.0,790.0,690.0,550.0,460.0,390.0,340.0,270.0,230.0,200.0,170.0,140.0,110.0,98.0,85.0,68.0,57.0,49.0,43.0,34.0,
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28.0,25.0,22.0,18.0,14.0,12.0,11.0,8.5,7.1,6.1,5.4,4.3,3.6,3.1
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};
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static const float PLFOS_Scale[8] = { 0.f, 3.61f, 7.22f, 14.44f, 28.88f, 57.75f, 115.5f, 231.f };
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static int PLFO_Scales[8][256];
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#define AEG_STEP_BITS (16)
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//Steps per sample
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u32 AEG_ATT_SPS[64];
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u32 AEG_DSR_SPS[64];
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const char* stream_names[]=
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static const char* stream_names[]=
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{
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"0: 16-bit PCM (two's complement format)",
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"1: 8-bit PCM (two's complement format)",
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@ -55,17 +82,28 @@ const char* stream_names[]=
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};
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//x.8 format
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const s32 adpcm_qs[8] =
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static const s32 adpcm_qs[8] =
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{
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0x0e6, 0x0e6, 0x0e6, 0x0e6, 0x133, 0x199, 0x200, 0x266,
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};
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//x.3 format
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const s32 adpcm_scale[16] =
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static const s32 adpcm_scale[16] =
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{
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1,3,5,7,9,11,13,15,
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-1,-3,-5,-7,-9,-11,-13,-15,
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};
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static const s32 qtable[32] = {
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0x0E00,0x0E80,0x0F00,0x0F80,
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0x1000,0x1080,0x1100,0x1180,
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0x1200,0x1280,0x1300,0x1380,
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0x1400,0x1480,0x1500,0x1580,
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0x1600,0x1680,0x1700,0x1780,
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0x1800,0x1880,0x1900,0x1980,
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0x1A00,0x1A80,0x1B00,0x1B80,
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0x1C00,0x1D00,0x1E00,0x1F00
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};
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void AICA_Sample();
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//Remove the fractional part , with rounding ;) -- does not need an extra bit
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@ -185,7 +223,9 @@ struct ChannelCommonData
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//+28 TL[7:0] -- Q[4:0]
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u32 Q:5;
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u32 rez_28_0:3;
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u32 LPOFF:1; // confirmed but not documented: 0: LPF enabled, 1: LPF disabled
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u32 VOFF:1; // unconfirmed: 0: attenuation enabled, 1: attenuation disabled (TL, AEG, ALFO)
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u32 rez_28_0:1;
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u32 TL:8;
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@ -321,10 +361,6 @@ struct ChannelEx
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void (* StepStream)(ChannelEx* ch);
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void (* StepStreamInitial)(ChannelEx* ch);
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u8 step_stream_lut1=0 ;
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u8 step_stream_lut2=0 ;
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u8 step_stream_lut3=0 ;
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struct
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{
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s32 val;
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@ -342,9 +378,21 @@ struct ChannelEx
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struct
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{
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s32 value;
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u32 value;
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__forceinline u32 GetValue() { return value >> AEG_STEP_BITS;}
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void SetValue(u32 fegb) { value = fegb << AEG_STEP_BITS; }
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_EG_state state = EG_Attack;
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} FEG;//i have to figure out how this works w/ AEG and channel state, and the iir values
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SampleType prev1;
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SampleType prev2;
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s32 q;
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u32 AttackRate;
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u32 Decay1Rate;
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u32 Decay2Rate;
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u32 ReleaseRate;
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bool active = false;
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} FEG;
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struct
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{
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@ -353,10 +401,8 @@ struct ChannelEx
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u8 state;
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u8 alfo;
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u8 alfo_shft;
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u8 plfo;
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u8 plfo_shft;
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u8 alfo_calc_lut=0 ;
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u8 plfo_calc_lut=0 ;
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fp_22_10 plfo_step;
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int *plfo_scale;
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void (* alfo_calc)(ChannelEx* ch);
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void (* plfo_calc)(ChannelEx* ch);
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__forceinline void Step(ChannelEx* ch) { counter--;if (counter==0) { state++; counter=start_value; alfo_calc(ch);plfo_calc(ch); } }
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@ -372,7 +418,7 @@ struct ChannelEx
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ccd=(ChannelCommonData*)&ccd_raw[cn*0x80];
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ChannelNumber = cn;
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for (u32 i=0;i<0x80;i++)
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RegWrite(i);
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RegWrite(i, 1);
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disable();
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}
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void disable()
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@ -405,6 +451,18 @@ struct ChannelEx
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{
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SampleType sample = InterpolateSample();
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// Low-pass filter
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if (FEG.active)
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{
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u32 fv = FEG.GetValue();
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s32 f = (((fv & 0xFF) | 0x100) << 4) >> ((fv >> 8) ^ 0x1F);
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sample = f * sample + (0x2000 - f + FEG.q) * FEG.prev1 - FEG.q * FEG.prev2;
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sample >>= 13;
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clip16(sample);
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FEG.prev2 = FEG.prev1;
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FEG.prev1 = sample;
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}
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//Volume & Mixer processing
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//All attenuations are added together then applied and mixed :)
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@ -412,8 +470,16 @@ struct ChannelEx
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//*Att is up to 511
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//logtable handles up to 1024, anything >=255 is mute
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u32 ofsatt=lfo.alfo+(AEG.GetValue()>>2);
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u32 ofsatt;
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if (ccd->VOFF == 1)
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{
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ofsatt = 0;
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}
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else
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{
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ofsatt = lfo.alfo + (AEG.GetValue() >> 2);
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ofsatt = min(ofsatt, (u32)255); // make sure it never gets more 255 -- it can happen with some alfo/aeg combinations
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}
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u32 const max_att = ((16 << 4) - 1) - ofsatt;
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s32* logtable = ofsatt + tl_lut;
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@ -466,11 +532,19 @@ struct ChannelEx
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if (newstate==EG_Release)
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ccd->KYONB=0;
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}
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void SetFegState(_EG_state newstate)
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{
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StepFEG = FEG_STEP_LUT[newstate];
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FEG.state = newstate;
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if (newstate == EG_Attack)
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{
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FEG.SetValue(ccd->FLV0);
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FEG.prev1 = 0;
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FEG.prev2 = 0;
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}
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}
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void KEY_ON()
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{
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if (AEG.state==EG_Release)
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@ -496,9 +570,11 @@ struct ChannelEx
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adpcm.Reset(this);
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StepStreamInitial(this);
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key_printf("[%d] KEY_ON %s @ %f Hz, loop %d, AEG AR %d DC1R %d DC2V %d DC2R %d RR %d", ChannelNumber, stream_names[ccd->PCMS], (44100.0 * update_rate) / 1024, ccd->LPCTL,
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AEG.AttackRate, AEG.Decay1Rate, AEG.Decay2Value, AEG.Decay2Rate, AEG.ReleaseRate);
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key_printf("[%d] KEY_ON %s @ %f Hz, loop %d - AEG AR %d DC1R %d DC2V %d DC2R %d RR %d - KRS %d OCT %d FNS %d - PFLOS %d PFLOWS %d",
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ChannelNumber, stream_names[ccd->PCMS], (44100.0 * update_rate) / 1024, ccd->LPCTL,
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ccd->AR, ccd->D1R, ccd->DL << 5, ccd->D2R, ccd->RR,
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ccd->KRS, ccd->OCT, ccd->FNS >> 9,
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ccd->PLFOS, ccd->PLFOWS);
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}
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else
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{
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@ -511,6 +587,7 @@ struct ChannelEx
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{
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key_printf("[%d] KEY_OFF -> Release", ChannelNumber);
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SetAegState(EG_Release);
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SetFegState(EG_Release);
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//switch to release state
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}
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else
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@ -527,9 +604,6 @@ struct ChannelEx
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StepStream=STREAM_STEP_LUT[fmt][ccd->LPCTL][ccd->LPSLNK];
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StepStreamInitial=STREAM_INITAL_STEP_LUT[fmt];
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step_stream_lut1 = fmt ;
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step_stream_lut2 = ccd->LPCTL ;
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step_stream_lut3 = ccd->LPSLNK ;
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}
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//SA,PCMS
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void UpdateSA()
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@ -546,31 +620,37 @@ struct ChannelEx
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loop.LSA=ccd->LSA;
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loop.LEA=ccd->LEA;
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}
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//
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u32 AEG_EffRate(u32 re)
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u32 EG_BaseRate()
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{
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s32 rv=ccd->KRS+(ccd->FNS>>9) + re*2;
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s32 rv=ccd->KRS+(ccd->FNS>>9);
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if (ccd->KRS==0xF)
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rv-=0xF;
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if (ccd->OCT&8)
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rv-=(16-ccd->OCT)*2;
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else
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rv+=ccd->OCT*2;
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if (rv<0)
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rv=0;
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if (rv>0x3f)
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rv=0x3f;
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return rv;
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}
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u32 EG_EffRate(u32 base_rate, u32 rate)
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{
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s32 rv = base_rate + rate * 2;
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clip(rv, 0, 0x3f);
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return rv;
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}
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//D2R,D1R,AR,DL,RR,KRS, [OCT,FNS] for now
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void UpdateAEG()
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{
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AEG.AttackRate = AEG_ATT_SPS[AEG_EffRate(ccd->AR)];
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AEG.Decay1Rate = AEG_DSR_SPS[AEG_EffRate(ccd->D1R)];
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s32 base_rate = EG_BaseRate();
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AEG.AttackRate = AEG_ATT_SPS[EG_EffRate(base_rate, ccd->AR)];
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AEG.Decay1Rate = AEG_DSR_SPS[EG_EffRate(base_rate, ccd->D1R)];
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AEG.Decay2Value = ccd->DL<<5;
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AEG.Decay2Rate = AEG_DSR_SPS[AEG_EffRate(ccd->D2R)];
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AEG.ReleaseRate = AEG_DSR_SPS[AEG_EffRate(ccd->RR)];
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AEG.Decay2Rate = AEG_DSR_SPS[EG_EffRate(base_rate, ccd->D2R)];
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AEG.ReleaseRate = AEG_DSR_SPS[EG_EffRate(base_rate, ccd->RR)];
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}
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//OCT,FNS
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void UpdatePitch()
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@ -586,7 +666,7 @@ struct ChannelEx
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this->update_rate=update_rate;
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}
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//LFORE,LFOF,PLFOWS,PLFOS,LFOWS,ALFOS
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//LFORE,LFOF,PLFOWS,PLFOS,ALFOWS,ALFOS
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void UpdateLFO()
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{
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{
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@ -599,13 +679,11 @@ struct ChannelEx
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lfo.SetStartValue(O);
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}
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lfo.plfo_shft=8-ccd->PLFOS;
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lfo.alfo_shft=8-ccd->ALFOS;
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lfo.alfo_calc=ALFOWS_CALC[ccd->ALFOWS];
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lfo.plfo_calc=PLFOWS_CALC[ccd->PLFOWS];
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lfo.alfo_calc_lut=ccd->ALFOWS;
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lfo.plfo_calc_lut=ccd->PLFOWS;
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lfo.plfo_scale = PLFO_Scales[ccd->PLFOS];
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if (ccd->LFORE)
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{
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@ -628,7 +706,8 @@ struct ChannelEx
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//TL,DISDL,DIPAN,IMXL
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void UpdateAtts()
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{
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u32 attFull=ccd->TL+SendLevel[ccd->DISDL];
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u32 total_level = ccd->VOFF ? 0 : ccd->TL;
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u32 attFull = total_level + SendLevel[ccd->DISDL];
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u32 attPan = attFull + SendLevel[(~ccd->DIPAN) & 0xF];
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//0x1* -> R decreases
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@ -643,29 +722,40 @@ struct ChannelEx
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VolMix.DRAtt=attFull;
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}
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VolMix.DSPAtt = ccd->TL+SendLevel[ccd->IMXL];
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VolMix.DSPAtt = total_level + SendLevel[ccd->IMXL];
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}
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//Q,FLV0,FLV1,FLV2,FLV3,FLV4,FAR,FD1R,FD2R,FRR
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void UpdateFEG()
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{
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//this needs to be filled
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FEG.active = ccd->LPOFF == 0
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&& (ccd->FLV0 < 0x1ff7 || ccd->FLV1 < 0x1ff7
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|| ccd->FLV2 < 0x1ff7 || ccd->FLV3 < 0x1ff7
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|| ccd->FLV4 < 0x1ff7);
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if (!FEG.active)
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return;
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feg_printf("FEG active channel %d Q %d FLV: %05x %05x %05x %05x %05x AR %02x FD1R %02x FD2R %02x FRR %02x",
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ChannelNumber, ccd->Q,
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ccd->FLV0, ccd->FLV1, ccd->FLV2, ccd->FLV3, ccd->FLV4,
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ccd->FAR, ccd->FD1R, ccd->FD2R, ccd->FRR);
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FEG.q = qtable[ccd->Q];
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s32 base_rate = EG_BaseRate();
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FEG.AttackRate = AEG_DSR_SPS[EG_EffRate(base_rate, ccd->FAR)];
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||||
FEG.Decay1Rate = AEG_DSR_SPS[EG_EffRate(base_rate, ccd->FD1R)];
|
||||
FEG.Decay2Rate = AEG_DSR_SPS[EG_EffRate(base_rate, ccd->FD2R)];
|
||||
FEG.ReleaseRate = AEG_DSR_SPS[EG_EffRate(base_rate, ccd->FRR)];
|
||||
}
|
||||
|
||||
//WHEE :D!
|
||||
void RegWrite(u32 offset)
|
||||
void RegWrite(u32 offset, int size)
|
||||
{
|
||||
switch(offset)
|
||||
{
|
||||
case 0x00: //yay ?
|
||||
case 0x00:
|
||||
case 0x01:
|
||||
UpdateStreamStep();
|
||||
UpdateSA();
|
||||
break;
|
||||
|
||||
case 0x01: //yay ?
|
||||
UpdateStreamStep();
|
||||
UpdateSA();
|
||||
if (ccd->KYONEX)
|
||||
if ((offset == 0x01 || size == 2) && ccd->KYONEX)
|
||||
{
|
||||
ccd->KYONEX=0;
|
||||
for (int i = 0; i < 64; i++)
|
||||
|
|
@ -708,7 +798,7 @@ struct ChannelEx
|
|||
break;
|
||||
|
||||
case 0x1C://ALFOS,ALFOWS,PLFOS
|
||||
case 0x1D://PLFOWS,LFOF,RE
|
||||
case 0x1D://PLFOWS,LFOF,LFORE
|
||||
UpdateLFO();
|
||||
break;
|
||||
|
||||
|
|
@ -724,10 +814,10 @@ struct ChannelEx
|
|||
break;
|
||||
|
||||
case 0x28://Q
|
||||
UpdateFEG();
|
||||
break;
|
||||
|
||||
case 0x29://TL
|
||||
if (size == 2 || offset == 0x28)
|
||||
UpdateFEG();
|
||||
if (size == 2 || offset == 0x29)
|
||||
UpdateAtts();
|
||||
break;
|
||||
|
||||
|
|
@ -872,7 +962,7 @@ void StepDecodeSampleInitial(ChannelEx* ch)
|
|||
template<s32 PCMS,u32 LPCTL,u32 LPSLNK>
|
||||
void StreamStep(ChannelEx* ch)
|
||||
{
|
||||
ch->step.full+=ch->update_rate;
|
||||
ch->step.full += (ch->update_rate * ch->lfo.plfo_step.full) >> 10;
|
||||
fp_22_10 sp=ch->step;
|
||||
ch->step.ip=0;
|
||||
|
||||
|
|
@ -955,20 +1045,19 @@ void CalcPlfo(ChannelEx* ch)
|
|||
break;
|
||||
|
||||
case 1: // square
|
||||
rv=ch->lfo.state&0x80?0x80:0x7F;
|
||||
rv = ch->lfo.state & 0x80 ? 0xff : 0;
|
||||
break;
|
||||
|
||||
case 2: // triangle
|
||||
rv = (ch->lfo.state & 0x7f) ^ (ch->lfo.state & 0x80 ? 0x7F : 0);
|
||||
rv <<= 1;
|
||||
rv=(u8)(rv-0x80); //2's complement
|
||||
break;
|
||||
|
||||
case 3:// random ! .. not :p
|
||||
rv = (ch->lfo.state >> 3) ^ (ch->lfo.state << 3) ^ (ch->lfo.state & 0xE3);
|
||||
break;
|
||||
}
|
||||
ch->lfo.plfo=rv>>ch->lfo.plfo_shft;
|
||||
ch->lfo.plfo_step.full = ch->lfo.plfo_scale[(u8)rv];
|
||||
}
|
||||
|
||||
template<u32 state>
|
||||
|
|
@ -1031,8 +1120,54 @@ void AegStep(ChannelEx* ch)
|
|||
template<u32 state>
|
||||
void FegStep(ChannelEx* ch)
|
||||
{
|
||||
|
||||
if (!ch->FEG.active)
|
||||
return;
|
||||
u32 delta;
|
||||
u32 target;
|
||||
switch(state)
|
||||
{
|
||||
case EG_Attack:
|
||||
delta = ch->FEG.AttackRate;
|
||||
target = ch->ccd->FLV1;
|
||||
break;
|
||||
case EG_Decay1:
|
||||
delta = ch->FEG.Decay1Rate;
|
||||
target = ch->ccd->FLV2;
|
||||
break;
|
||||
case EG_Decay2:
|
||||
delta = ch->FEG.Decay2Rate;
|
||||
target = ch->ccd->FLV3;
|
||||
break;
|
||||
case EG_Release:
|
||||
delta = ch->FEG.ReleaseRate;
|
||||
target = ch->ccd->FLV4;
|
||||
break;
|
||||
}
|
||||
target <<= AEG_STEP_BITS;
|
||||
if (ch->FEG.value < target)
|
||||
{
|
||||
u32 maxd = target - ch->FEG.value;
|
||||
if (delta > maxd)
|
||||
delta = maxd;
|
||||
ch->FEG.value += delta;
|
||||
}
|
||||
else if (ch->FEG.value > target)
|
||||
{
|
||||
u32 maxd = ch->FEG.value - target;
|
||||
if (delta > maxd)
|
||||
delta = maxd;
|
||||
ch->FEG.value -= delta;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (ch->FEG.state < EG_Decay2)
|
||||
{
|
||||
feg_printf("[%d]FEG_step : Switching to next state: %d Freq %x", ch->ChannelNumber, (int)ch->FEG.state + 1, target >> AEG_STEP_BITS);
|
||||
ch->SetFegState((_EG_state)((int)ch->FEG.state + 1));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void staticinitialise()
|
||||
{
|
||||
STREAM_STEP_LUT[0][0][0]=&StreamStep<0,0,0>;
|
||||
|
|
@ -1138,6 +1273,15 @@ void sgc_Init()
|
|||
Chans[i].Init(i,aica_reg);
|
||||
dsp_out_vol=(DSP_OUT_VOL_REG*)&aica_reg[0x2000];
|
||||
|
||||
for (int s = 0; s < 8; s++)
|
||||
{
|
||||
float limit = PLFOS_Scale[s];
|
||||
for (int i = -128; i < 128; i++)
|
||||
{
|
||||
PLFO_Scales[s][i + 128] = (u32)((1 << 10) * powf(2.0f, limit * i / 128.0f / 1200.0f));
|
||||
}
|
||||
}
|
||||
|
||||
dsp_init();
|
||||
}
|
||||
|
||||
|
|
@ -1146,9 +1290,9 @@ void sgc_Term()
|
|||
dsp_term();
|
||||
}
|
||||
|
||||
void WriteChannelReg8(u32 channel,u32 reg)
|
||||
void WriteChannelReg(u32 channel, u32 reg, int size)
|
||||
{
|
||||
Chans[channel].RegWrite(reg);
|
||||
Chans[channel].RegWrite(reg, size);
|
||||
}
|
||||
|
||||
void ReadCommonReg(u32 reg,bool byte)
|
||||
|
|
@ -1425,110 +1569,139 @@ bool channel_serialize(void **data, unsigned int *total_size)
|
|||
|
||||
for ( i = 0 ; i < 64 ; i++)
|
||||
{
|
||||
addr = Chans[i].SA - (&(aica_ram.data[0])) ;
|
||||
addr = Chans[i].SA - (&(aica_ram[0])) ;
|
||||
REICAST_S(addr);
|
||||
|
||||
REICAST_S(Chans[i].CA) ;
|
||||
REICAST_S(Chans[i].step) ;
|
||||
REICAST_S(Chans[i].update_rate) ;
|
||||
REICAST_S(Chans[i].s0) ;
|
||||
REICAST_S(Chans[i].s1) ;
|
||||
REICAST_S(Chans[i].loop) ;
|
||||
REICAST_S(Chans[i].loop.looped) ;
|
||||
REICAST_S(Chans[i].adpcm.last_quant) ;
|
||||
REICAST_S(Chans[i].adpcm.loopstart_quant);
|
||||
REICAST_S(Chans[i].adpcm.loopstart_prev_sample);
|
||||
REICAST_S(Chans[i].adpcm.in_loop);
|
||||
REICAST_S(Chans[i].noise_state) ;
|
||||
REICAST_S(Chans[i].VolMix.DLAtt) ;
|
||||
REICAST_S(Chans[i].VolMix.DRAtt) ;
|
||||
REICAST_S(Chans[i].VolMix.DSPAtt) ;
|
||||
|
||||
addr = Chans[i].VolMix.DSPOut - (&(dsp.MIXS[0])) ;
|
||||
REICAST_S(addr);
|
||||
|
||||
REICAST_S(Chans[i].AEG.val) ;
|
||||
REICAST_S(Chans[i].AEG.state) ;
|
||||
REICAST_S(Chans[i].AEG.AttackRate) ;
|
||||
REICAST_S(Chans[i].AEG.Decay1Rate) ;
|
||||
REICAST_S(Chans[i].AEG.Decay2Rate) ;
|
||||
REICAST_S(Chans[i].AEG.Decay2Value) ;
|
||||
REICAST_S(Chans[i].AEG.ReleaseRate) ;
|
||||
REICAST_S(Chans[i].FEG) ;
|
||||
REICAST_S(Chans[i].step_stream_lut1) ;
|
||||
REICAST_S(Chans[i].step_stream_lut2) ;
|
||||
REICAST_S(Chans[i].step_stream_lut3) ;
|
||||
REICAST_S(Chans[i].FEG.value);
|
||||
REICAST_S(Chans[i].FEG.state);
|
||||
REICAST_S(Chans[i].FEG.prev1);
|
||||
REICAST_S(Chans[i].FEG.prev2);
|
||||
|
||||
REICAST_S(Chans[i].lfo.counter) ;
|
||||
REICAST_S(Chans[i].lfo.start_value) ;
|
||||
REICAST_S(Chans[i].lfo.state) ;
|
||||
REICAST_S(Chans[i].lfo.alfo) ;
|
||||
REICAST_S(Chans[i].lfo.alfo_shft) ;
|
||||
REICAST_S(Chans[i].lfo.plfo) ;
|
||||
REICAST_S(Chans[i].lfo.plfo_shft) ;
|
||||
REICAST_S(Chans[i].lfo.alfo_calc_lut) ;
|
||||
REICAST_S(Chans[i].lfo.plfo_calc_lut) ;
|
||||
REICAST_S(Chans[i].enabled) ;
|
||||
REICAST_S(Chans[i].ChannelNumber) ;
|
||||
}
|
||||
|
||||
/* TODO/FIXME - no possibility for this to return false? */
|
||||
return true;
|
||||
}
|
||||
|
||||
bool channel_unserialize(void **data, unsigned int *total_size)
|
||||
bool channel_unserialize(void **data, unsigned int *total_size, serialize_version_enum ver)
|
||||
{
|
||||
int i = 0 ;
|
||||
int addr = 0 ;
|
||||
u32 dum;
|
||||
|
||||
for ( i = 0 ; i < 64 ; i++)
|
||||
{
|
||||
REICAST_US(addr);
|
||||
Chans[i].SA = addr + (&(aica_ram.data[0])) ;
|
||||
Chans[i].SA = addr + (&(aica_ram[0])) ;
|
||||
|
||||
REICAST_US(Chans[i].CA) ;
|
||||
REICAST_US(Chans[i].step) ;
|
||||
REICAST_US(Chans[i].update_rate) ;
|
||||
if (ver < V7)
|
||||
REICAST_US(dum); // Chans[i].update_rate
|
||||
Chans[i].UpdatePitch();
|
||||
REICAST_US(Chans[i].s0) ;
|
||||
REICAST_US(Chans[i].s1) ;
|
||||
REICAST_US(Chans[i].loop) ;
|
||||
REICAST_US(Chans[i].loop.looped);
|
||||
if (ver < V7)
|
||||
{
|
||||
REICAST_US(dum); // Chans[i].loop.LSA
|
||||
REICAST_US(dum); // Chans[i].loop.LEA
|
||||
}
|
||||
Chans[i].UpdateLoop();
|
||||
REICAST_US(Chans[i].adpcm.last_quant) ;
|
||||
if (ver >= V7)
|
||||
{
|
||||
REICAST_US(Chans[i].adpcm.loopstart_quant);
|
||||
REICAST_US(Chans[i].adpcm.loopstart_prev_sample);
|
||||
REICAST_US(Chans[i].adpcm.in_loop);
|
||||
}
|
||||
else
|
||||
{
|
||||
Chans[i].adpcm.in_loop = true;
|
||||
Chans[i].adpcm.loopstart_quant = 0;
|
||||
Chans[i].adpcm.loopstart_prev_sample = 0;
|
||||
}
|
||||
REICAST_US(Chans[i].noise_state) ;
|
||||
REICAST_US(Chans[i].VolMix.DLAtt) ;
|
||||
REICAST_US(Chans[i].VolMix.DRAtt) ;
|
||||
REICAST_US(Chans[i].VolMix.DSPAtt) ;
|
||||
|
||||
REICAST_US(addr);
|
||||
Chans[i].VolMix.DSPOut = addr + (&(dsp.MIXS[0])) ;
|
||||
if (ver < V7)
|
||||
{
|
||||
REICAST_US(dum); // Chans[i].VolMix.DLAtt
|
||||
REICAST_US(dum); // Chans[i].VolMix.DRAtt
|
||||
REICAST_US(dum); // Chans[i].VolMix.DSPAtt
|
||||
}
|
||||
Chans[i].UpdateAtts();
|
||||
if (ver < V7)
|
||||
REICAST_US(dum); // Chans[i].VolMix.DSPOut
|
||||
Chans[i].UpdateDSPMIX();
|
||||
|
||||
REICAST_US(Chans[i].AEG.val) ;
|
||||
REICAST_US(Chans[i].AEG.state) ;
|
||||
Chans[i].StepAEG=AEG_STEP_LUT[Chans[i].AEG.state];
|
||||
REICAST_US(Chans[i].AEG.AttackRate) ;
|
||||
REICAST_US(Chans[i].AEG.Decay1Rate) ;
|
||||
REICAST_US(Chans[i].AEG.Decay2Rate) ;
|
||||
REICAST_US(Chans[i].AEG.Decay2Value) ;
|
||||
REICAST_US(Chans[i].AEG.ReleaseRate) ;
|
||||
REICAST_US(Chans[i].FEG) ;
|
||||
Chans[i].StepFEG=FEG_STEP_LUT[Chans[i].FEG.state];
|
||||
REICAST_US(Chans[i].step_stream_lut1) ;
|
||||
REICAST_US(Chans[i].step_stream_lut2) ;
|
||||
REICAST_US(Chans[i].step_stream_lut3) ;
|
||||
Chans[i].StepStream=STREAM_STEP_LUT[Chans[i].step_stream_lut1][Chans[i].step_stream_lut2][Chans[i].step_stream_lut3] ;
|
||||
Chans[i].StepStreamInitial=STREAM_INITAL_STEP_LUT[Chans[i].step_stream_lut1];
|
||||
Chans[i].SetAegState(Chans[i].AEG.state);
|
||||
if (ver < V7)
|
||||
{
|
||||
REICAST_US(dum); // Chans[i].AEG.AttackRate
|
||||
REICAST_US(dum); // Chans[i].AEG.Decay1Rate
|
||||
REICAST_US(dum); // Chans[i].AEG.Decay2Rate
|
||||
REICAST_US(dum); // Chans[i].AEG.Decay2Value
|
||||
REICAST_US(dum); // Chans[i].AEG.ReleaseRate
|
||||
}
|
||||
Chans[i].UpdateAEG();
|
||||
REICAST_US(Chans[i].FEG.value);
|
||||
REICAST_US(Chans[i].FEG.state);
|
||||
if (ver >= V7)
|
||||
{
|
||||
REICAST_US(Chans[i].FEG.prev1);
|
||||
REICAST_US(Chans[i].FEG.prev2);
|
||||
}
|
||||
else
|
||||
{
|
||||
Chans[i].FEG.prev1 = 0;
|
||||
Chans[i].FEG.prev2 = 0;
|
||||
}
|
||||
Chans[i].SetFegState(Chans[i].FEG.state);
|
||||
Chans[i].UpdateFEG();
|
||||
if (ver < V7)
|
||||
{
|
||||
u8 dumu8;
|
||||
REICAST_US(dumu8); // Chans[i].step_stream_lut1
|
||||
REICAST_US(dumu8); // Chans[i].step_stream_lut2
|
||||
REICAST_US(dumu8); // Chans[i].step_stream_lut3
|
||||
}
|
||||
Chans[i].UpdateStreamStep();
|
||||
|
||||
REICAST_US(Chans[i].lfo.counter) ;
|
||||
REICAST_US(Chans[i].lfo.start_value) ;
|
||||
if (ver < V7)
|
||||
REICAST_US(dum); // Chans[i].lfo.start_value
|
||||
REICAST_US(Chans[i].lfo.state) ;
|
||||
REICAST_US(Chans[i].lfo.alfo) ;
|
||||
REICAST_US(Chans[i].lfo.alfo_shft) ;
|
||||
REICAST_US(Chans[i].lfo.plfo) ;
|
||||
REICAST_US(Chans[i].lfo.plfo_shft) ;
|
||||
REICAST_US(Chans[i].lfo.alfo_calc_lut) ;
|
||||
REICAST_US(Chans[i].lfo.plfo_calc_lut) ;
|
||||
Chans[i].lfo.alfo_calc = ALFOWS_CALC[Chans[i].lfo.alfo_calc_lut];
|
||||
Chans[i].lfo.plfo_calc = PLFOWS_CALC[Chans[i].lfo.plfo_calc_lut];
|
||||
if (ver < V7)
|
||||
{
|
||||
u8 dumu8;
|
||||
REICAST_US(dumu8); // Chans[i].lfo.alfo
|
||||
REICAST_US(dumu8); // Chans[i].lfo.alfo_shft
|
||||
REICAST_US(dumu8); // Chans[i].lfo.plfo
|
||||
REICAST_US(dumu8); // Chans[i].lfo.plfo_shft
|
||||
REICAST_US(dumu8); // Chans[i].lfo.alfo_calc_lut
|
||||
REICAST_US(dumu8); // Chans[i].lfo.plfo_calc_lut
|
||||
}
|
||||
Chans[i].UpdateLFO();
|
||||
REICAST_US(Chans[i].enabled) ;
|
||||
REICAST_US(Chans[i].ChannelNumber) ;
|
||||
|
||||
if (ver < V7)
|
||||
REICAST_US(dum); // Chans[i].ChannelNumber
|
||||
}
|
||||
|
||||
/* TODO/FIXME - no possibility for this to return false? */
|
||||
return true;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ void AICA_Sample();
|
|||
void AICA_Sample32();
|
||||
|
||||
//u32 ReadChannelReg(u32 channel,u32 reg);
|
||||
void WriteChannelReg8(u32 channel,u32 reg);
|
||||
void WriteChannelReg(u32 channel, u32 reg, int size);
|
||||
|
||||
void sgc_Init();
|
||||
void sgc_Term();
|
||||
|
|
@ -56,7 +56,7 @@ typedef s32 SampleType;
|
|||
|
||||
void ReadCommonReg(u32 reg,bool byte);
|
||||
void WriteCommonReg8(u32 reg,u32 data);
|
||||
#define clip(x,min,max) if ((x)<(min)) (x)=(min); if ((x)>(max)) (x)=(max);
|
||||
#define clip(x,min,max) do { if ((x)<(min)) (x)=(min); else if ((x)>(max)) (x)=(max); } while (false)
|
||||
#define clip16(x) clip(x,-32768,32767)
|
||||
bool channel_serialize(void **data, unsigned int *total_size);
|
||||
bool channel_unserialize(void **data, unsigned int *total_size);
|
||||
bool channel_unserialize(void **data, unsigned int *total_size, serialize_version_enum version);
|
||||
|
|
|
|||
|
|
@ -30,19 +30,6 @@
|
|||
|
||||
extern "C" void DYNACALL TAWriteSQ(u32 address,u8* sqb);
|
||||
|
||||
enum serialize_version_enum {
|
||||
V1,
|
||||
V2,
|
||||
V3,
|
||||
V4,
|
||||
V5_LIBRETRO_UNSUPPORTED,
|
||||
V6_LIBRETRO_UNSUPPORTED,
|
||||
V7_LIBRETRO,
|
||||
|
||||
V5 = 800,
|
||||
V6 = 801,
|
||||
} ;
|
||||
|
||||
//./core/hw/arm7/arm_mem.cpp
|
||||
extern bool aica_interr;
|
||||
extern u32 aica_reg_L;
|
||||
|
|
@ -316,7 +303,7 @@ bool dc_serialize(void **data, unsigned int *total_size)
|
|||
{
|
||||
int i = 0;
|
||||
int j = 0;
|
||||
serialize_version_enum version = V6;
|
||||
serialize_version_enum version = V7;
|
||||
|
||||
*total_size = 0 ;
|
||||
|
||||
|
|
@ -618,7 +605,7 @@ static bool dc_unserialize_libretro(void **data, unsigned int *total_size)
|
|||
|
||||
REICAST_USA(aica_reg,0x8000);
|
||||
|
||||
channel_unserialize(data, total_size) ;
|
||||
channel_unserialize(data, total_size, V7_LIBRETRO);
|
||||
|
||||
REICAST_USA(cdda_sector,CDDA_SIZE);
|
||||
REICAST_US(cdda_index);
|
||||
|
|
@ -988,7 +975,7 @@ bool dc_unserialize(void **data, unsigned int *total_size)
|
|||
REICAST_SKIP(2);
|
||||
REICAST_SKIP(2);
|
||||
}
|
||||
channel_unserialize(data, total_size) ;
|
||||
channel_unserialize(data, total_size, version);
|
||||
|
||||
REICAST_USA(cdda_sector,CDDA_SIZE);
|
||||
REICAST_US(cdda_index);
|
||||
|
|
|
|||
14
core/types.h
14
core/types.h
|
|
@ -675,3 +675,17 @@ public:
|
|||
|
||||
std::string reason;
|
||||
};
|
||||
|
||||
enum serialize_version_enum {
|
||||
V1,
|
||||
V2,
|
||||
V3,
|
||||
V4,
|
||||
V5_LIBRETRO_UNSUPPORTED,
|
||||
V6_LIBRETRO_UNSUPPORTED,
|
||||
V7_LIBRETRO,
|
||||
|
||||
V5 = 800,
|
||||
V6 = 801,
|
||||
V7 = 802,
|
||||
} ;
|
||||
|
|
|
|||
Loading…
Reference in New Issue