diff --git a/core/hw/aica/aica_if.cpp b/core/hw/aica/aica_if.cpp
index 4d7a35d16..397fe8764 100644
--- a/core/hw/aica/aica_if.cpp
+++ b/core/hw/aica/aica_if.cpp
@@ -393,7 +393,7 @@ static void Write_SB_ADST(u32 addr, u32 data)
 			SB_ADSUSP &= ~0x10;
 
 			// Schedule the end of DMA transfer interrupt
-			int cycles = len * (SH4_MAIN_CLOCK / 2 / 25000000);       // 16 bits @ 25 MHz
+			int cycles = len * (SH4_MAIN_CLOCK / 2 / G2_BUS_CLOCK);       // 16 bits @ 25 MHz
 			if (cycles < 4096)
 				dma_end_sched(0, 0, 0);
 			else
@@ -492,8 +492,10 @@ void aica_sb_Init()
 
 void aica_sb_Reset(bool hard)
 {
-	if (hard)
+	if (hard) {
 		SB_ADST = 0;
+		SB_G2APRO = 0x7f00;
+	}
 }
 
 void aica_sb_Term()
diff --git a/core/hw/gdrom/gdromv3.cpp b/core/hw/gdrom/gdromv3.cpp
index 60934d572..82d43e081 100644
--- a/core/hw/gdrom/gdromv3.cpp
+++ b/core/hw/gdrom/gdromv3.cpp
@@ -1250,20 +1250,20 @@ static int GDRomschd(int i, int c, int j)
 }
 
 //DMA Start
-void GDROM_DmaStart(u32 addr, u32 data)
+static void GDROM_DmaStart(u32 addr, u32 data)
 {
-	if (SB_GDEN==0)
-	{
-		INFO_LOG(GDROM, "Invalid GD-DMA start, SB_GDEN=0. Ignoring it.");
-		return;
-	}
-	SB_GDST|=data&1;
+	SB_GDST |= data & 1;
 
-	if (SB_GDST==1)
+	if (SB_GDST == 1)
 	{
-		SB_GDSTARD=SB_GDSTAR;
-		SB_GDLEND=0;
-		DEBUG_LOG(GDROM, "GDROM-DMA start addr %08X len %d", SB_GDSTAR, SB_GDLEN);
+		if (SB_GDEN == 0)
+		{
+			INFO_LOG(GDROM, "Invalid GD-DMA start, SB_GDEN=0. Ignoring it.");
+			return;
+		}
+		SB_GDSTARD = SB_GDSTAR;
+		SB_GDLEND = 0;
+		DEBUG_LOG(GDROM, "GDROM-DMA start addr %08X len %d fad %x", SB_GDSTAR, SB_GDLEN, read_params.start_sector);
 
 		int ticks = getGDROMTicks();
 		if (ticks < SH4_TIMESLICE)
@@ -1276,9 +1276,9 @@ void GDROM_DmaStart(u32 addr, u32 data)
 	}
 }
 
-void GDROM_DmaEnable(u32 addr, u32 data)
+static void GDROM_DmaEnable(u32 addr, u32 data)
 {
-	SB_GDEN = (data & 1);
+	SB_GDEN = data & 1;
 	if (SB_GDEN == 0 && SB_GDST == 1)
 	{
 		printf_spi("GD-DMA aborted");
diff --git a/core/hw/holly/sb.cpp b/core/hw/holly/sb.cpp
index 300696162..683967d01 100644
--- a/core/hw/holly/sb.cpp
+++ b/core/hw/holly/sb.cpp
@@ -173,57 +173,34 @@ static const char *regName(u32 addr)
 		return it->second;
 }
 
-u32 sb_ReadMem(u32 addr,u32 sz)
+u32 sb_ReadMem(u32 addr)
 {
 	u32 offset = ((addr - SB_BASE) >> 2) & 0x1fff;
 	u32 rv;
 
-	if (!(sb_regs[offset].flags & (REG_RF|REG_WO)))
-	{
-		if (sz==4)
-			rv = sb_regs[offset].data32;
-		else if (sz==2)
-			rv = sb_regs[offset].data16;
-		else
-			rv = sb_regs[offset].data8;
-	}
+	if (!(sb_regs[offset].flags & REG_RF))
+		rv = sb_regs[offset].data32;
 	else
-	{
-		if ((sb_regs[offset].flags & REG_WO) || sb_regs[offset].readFunctionAddr == NULL)
-		{
-			INFO_LOG(HOLLY, "sb_ReadMem write-only reg %08x %d", addr, sz);
-			rv = 0;
-		}
-		else
-			rv = sb_regs[offset].readFunctionAddr(addr);
-	}
+		rv = sb_regs[offset].readFunctionAddr(addr);
+
 	if ((addr & 0xffffff) != 0x5f6c18) // SB_MDST
-		DEBUG_LOG(HOLLY, "read(%d) %s.%c == %x", sz, regName(addr),
+		DEBUG_LOG(HOLLY, "read %s.%c == %x", regName(addr),
 				((addr >> 26) & 7) == 2 ? 'b' : (addr & 0x2000000) ? '1' : '0',
 						rv);
 	return rv;
 }
 
-void sb_WriteMem(u32 addr,u32 data,u32 sz)
+void sb_WriteMem(u32 addr, u32 data)
 {
-	DEBUG_LOG(HOLLY, "write(%d) %s.%c = %x", sz, regName(addr),
+	DEBUG_LOG(HOLLY, "write %s.%c = %x", regName(addr),
 			((addr >> 26) & 7) == 2 ? 'b' : (addr & 0x2000000) ? '1' : '0',
 					data);
 	u32 offset = ((addr - SB_BASE) >> 2) & 0x1fff;
 
 	if (!(sb_regs[offset].flags & REG_WF))
-	{
-		if (sz==4)
-			sb_regs[offset].data32=data;
-		else if (sz==2)
-			sb_regs[offset].data16=(u16)data;
-		else
-			sb_regs[offset].data8=(u8)data;
-	}
+		sb_regs[offset].data32 = data;
 	else
-	{
-		sb_regs[offset].writeFunctionAddr(addr,data);
-	}
+		sb_regs[offset].writeFunctionAddr(addr, data);
 }
 
 static u32 sbio_read_noacc(u32 addr)
@@ -253,7 +230,7 @@ static void sb_write_gdrom_unlock(u32 addr, u32 data)
 
 void sb_rio_register(u32 reg_addr, RegIO flags, RegReadAddrFP* rf, RegWriteAddrFP* wf)
 {
-	u32 idx=(reg_addr-SB_BASE)/4;
+	u32 idx = (reg_addr - SB_BASE) / 4;
 
 	verify(idx < sb_regs.size());
 
@@ -261,22 +238,23 @@ void sb_rio_register(u32 reg_addr, RegIO flags, RegReadAddrFP* rf, RegWriteAddrF
 
 	if (flags == RIO_NO_ACCESS)
 	{
-		sb_regs[idx].readFunctionAddr=&sbio_read_noacc;
-		sb_regs[idx].writeFunctionAddr=&sbio_write_noacc;
+		sb_regs[idx].readFunctionAddr = sbio_read_noacc;
+		sb_regs[idx].writeFunctionAddr = sbio_write_noacc;
 	}
-	else if (flags == RIO_CONST)
+	else if (flags == RIO_RO)
 	{
-		sb_regs[idx].writeFunctionAddr=&sbio_write_const;
+		sb_regs[idx].writeFunctionAddr = sbio_write_const;
+		sb_regs[idx].data32 = 0;
 	}
 	else
 	{
-		sb_regs[idx].data32=0;
-
 		if (flags & REG_RF)
-			sb_regs[idx].readFunctionAddr=rf;
+			sb_regs[idx].readFunctionAddr = rf;
+		else
+			sb_regs[idx].data32 = 0;
 
 		if (flags & REG_WF)
-			sb_regs[idx].writeFunctionAddr=wf==0?&sbio_write_noacc:wf;
+			sb_regs[idx].writeFunctionAddr = wf == nullptr ? sbio_write_noacc : wf;
 	}
 }
 
@@ -288,14 +266,9 @@ void sb_write_reg(u32 addr, u32 data)
 
 u32 SB_FFST_rc;
 u32 SB_FFST;
-static u32 sb_read_SB_FFST(u32 addr)
+static u32 read_SB_FFST(u32 addr)
 {
-	SB_FFST_rc++;
-	if (SB_FFST_rc & 0x8)
-	{
-		SB_FFST^=31;
-	}
-	return 0; // does the fifo status has really to be faked ?
+	return 0;
 }
 
 static void sb_write_SB_SFRES(u32 addr, u32 data)
@@ -367,13 +340,13 @@ void sb_Init()
 	sb_rio_register(SB_LMMODE1_addr, RIO_WF, 0, sb_write_reg<SB_LMMODE1_addr, 1>);
 
 	//0x005F688C    SB_FFST     R   FIFO status
-	sb_rio_register(SB_FFST_addr, RIO_RO_FUNC, sb_read_SB_FFST);
+	sb_rio_register(SB_FFST_addr, RIO_RO_FUNC, read_SB_FFST);
 
 	//0x005F6890    SB_SFRES    W   System reset
 	sb_rio_register(SB_SFRES_addr, RIO_WO_FUNC, 0, sb_write_SB_SFRES);
 
 	//0x005F689C    SB_SBREV    R   System bus revision number
-	sb_rio_register(SB_SBREV_addr,RIO_CONST);
+	sb_rio_register(SB_SBREV_addr, RIO_RO);
 
 	//0x005F68A0    SB_RBSPLT   RW  SH4 Root Bus split enable
 	sb_rio_register(SB_RBSPLT_addr, RIO_WF, 0, sb_write_reg<SB_RBSPLT_addr, 0x80000000>);
@@ -620,7 +593,7 @@ void sb_Init()
 	sb_rio_register(SB_DDSUSP_addr, RIO_WF, 0, sb_write_SUSP<SB_DDSUSP_addr>);
 
 	//0x005F7880    SB_G2ID     R   G2 bus version
-	sb_rio_register(SB_G2ID_addr,RIO_CONST);
+	sb_rio_register(SB_G2ID_addr, RIO_RO);
 
 	//0x005F7890    SB_G2DSTO   RW  G2/DS timeout
 	sb_rio_register(SB_G2DSTO_addr,RIO_DATA);
@@ -747,11 +720,11 @@ void sb_Reset(bool hard)
 	{
 		for (auto& reg : sb_regs)
 			reg.reset();
+		SB_PDAPRO = 0x7f00;
+		SB_GDAPRO = 0x7f00;
 	}
 	SB_ISTNRM = 0;
 	SB_ISTNRM1 = 0;
-	SB_FFST_rc = 0;
-	SB_FFST = 0;
 
 	bba_Reset(hard);
 	ModemReset();
diff --git a/core/hw/holly/sb.h b/core/hw/holly/sb.h
index 5fe9f0dcd..137fd0a8e 100644
--- a/core/hw/holly/sb.h
+++ b/core/hw/holly/sb.h
@@ -7,8 +7,8 @@
 #include "hw/hwreg.h"
 #include <array>
 
-u32 sb_ReadMem(u32 addr,u32 sz);
-void sb_WriteMem(u32 addr,u32 data,u32 sz);
+u32 sb_ReadMem(u32 addr);
+void sb_WriteMem(u32 addr, u32 data);
 void sb_Init();
 void sb_Reset(bool hard);
 void sb_Term();
@@ -355,7 +355,7 @@ extern std::array<RegisterStruct, 0x540> sb_regs;
 //0x005F6888    SB_LMMODE1  RW  Via TA texture memory bus select 1
 #define SB_LMMODE1 SB_REG_32(LMMODE1)
 //0x005F688C    SB_FFST R   FIFO status
-extern u32 SB_FFST;
+//#define SB_FFST SB_REG_32(FFST)
 //0x005F6890    SB_SFRES    W   System reset
 #define SB_SFRES SB_REG_32(SFRES)
 
diff --git a/core/hw/holly/sb_mem.cpp b/core/hw/holly/sb_mem.cpp
index a92be8bad..619095f4e 100644
--- a/core/hw/holly/sb_mem.cpp
+++ b/core/hw/holly/sb_mem.cpp
@@ -325,7 +325,7 @@ T DYNACALL ReadMem_area0(u32 paddr)
 		}
 		// All SB registers
 		if (addr >= 0x005F6800 && addr <= 0x005F7CFF)
-			return (T)sb_ReadMem(paddr, sz);
+			return (T)sb_ReadMem(paddr);
 		// TA / PVR core registers
 		if (addr >= 0x005F8000 && addr <= 0x005F9FFF)
 		{
@@ -435,7 +435,7 @@ void DYNACALL WriteMem_area0(u32 paddr, T data)
 		// All SB registers
 		if (addr >= 0x005F6800 && addr <= 0x005F7CFF)
 		{
-			sb_WriteMem(paddr, data, sz);
+			sb_WriteMem(paddr, data);
 			return;
 		}
 		// TA / PVR core registers
diff --git a/core/hw/hwreg.h b/core/hw/hwreg.h
index e2f46fedc..58bbc8e01 100644
--- a/core/hw/hwreg.h
+++ b/core/hw/hwreg.h
@@ -11,7 +11,6 @@ typedef void RegWriteAddrFP(u32 addr, u32 data);
 	F    F     N      -> RF|WF		-> RIO_FUNC
 	D    X     N      -> RO|WF		-> RIO_RO
 	F    X     N      -> RF|WF|RO	-> RIO_RO_FUNC
-	D    X     Y      -> CONST|RO|WF-> RIO_CONST
 	X    F     N      -> RF|WF|WO	-> RIO_WO_FUNC
 */
 enum RegStructFlags
@@ -30,7 +29,6 @@ enum RegIO
 	RIO_FUNC = REG_WF | REG_RF,
 	RIO_RO = REG_RO | REG_WF,
 	RIO_RO_FUNC = REG_RO | REG_RF | REG_WF,
-	RIO_CONST = REG_RO | REG_WF,
 	RIO_WO_FUNC = REG_WF | REG_RF | REG_WO,
 	RIO_NO_ACCESS = REG_WF | REG_RF | REG_NO_ACCESS
 };
@@ -39,16 +37,13 @@ struct RegisterStruct
 {
 	union
 	{
-		u32 data32;					//stores data of reg variable [if used] 32b
-		u16 data16;					//stores data of reg variable [if used] 16b
-		u8  data8;					//stores data of reg variable [if used]	8b
-
-		RegReadAddrFP* readFunctionAddr; //stored pointer to reg read function
+		u32 data32;						 // Register value
+		RegReadAddrFP* readFunctionAddr; // Register read handler
 	};
 
-	RegWriteAddrFP* writeFunctionAddr; //stored pointer to reg write function
+	RegWriteAddrFP* writeFunctionAddr;	 // Register write handler
 
-	u32 flags;					//Access flags !
+	u32 flags;							 // Access flags
 
 	void reset()
 	{
diff --git a/core/hw/naomi/naomi.cpp b/core/hw/naomi/naomi.cpp
index 3183d069c..a203de6e7 100644
--- a/core/hw/naomi/naomi.cpp
+++ b/core/hw/naomi/naomi.cpp
@@ -422,19 +422,16 @@ void WriteMem_naomi(u32 address, u32 data, u32 size)
 }
 
 //Dma Start
-void Naomi_DmaStart(u32 addr, u32 data)
+static void Naomi_DmaStart(u32 addr, u32 data)
 {
-	if (SB_GDEN==0)
+	if ((data & 1) == 0)
+		return;
+	if (SB_GDEN == 0)
 	{
 		INFO_LOG(NAOMI, "Invalid (NAOMI)GD-DMA start, SB_GDEN=0. Ignoring it.");
 		return;
 	}
 	
-	SB_GDST |= data & 1;
-
-	if (SB_GDST == 0)
-		return;
-
 	if (!m3comm.DmaStart(addr, data) && CurrentCartridge != NULL)
 	{
 		DEBUG_LOG(NAOMI, "NAOMI-DMA start addr %08X len %d", SB_GDSTAR, SB_GDLEN);
@@ -464,20 +461,20 @@ void Naomi_DmaStart(u32 addr, u32 data)
 		SB_GDSTARD = SB_GDSTAR + SB_GDLEN;
 		SB_GDLEND = SB_GDLEN;
 	}
-	SB_GDST = 0;
 	asic_RaiseInterrupt(holly_GDROM_DMA);
 }
 
 
-void Naomi_DmaEnable(u32 addr, u32 data)
+static void Naomi_DmaEnable(u32 addr, u32 data)
 {
-	SB_GDEN=data&1;
-	if (SB_GDEN==0 && SB_GDST==1)
+	SB_GDEN = data & 1;
+	if (SB_GDEN == 0 && SB_GDST == 1)
 	{
 		INFO_LOG(NAOMI, "(NAOMI)GD-DMA aborted");
-		SB_GDST=0;
+		SB_GDST = 0;
 	}
 }
+
 void naomi_reg_Init()
 {
 	#ifdef NAOMI_COMM
diff --git a/core/hw/pvr/elan.cpp b/core/hw/pvr/elan.cpp
index 70c29e381..bdd40e08f 100644
--- a/core/hw/pvr/elan.cpp
+++ b/core/hw/pvr/elan.cpp
@@ -88,7 +88,7 @@ static u32 DYNACALL read_elanreg(u32 paddr)
 	{
 	case 0x5F:
 		if (addr >= 0x005F6800 && addr <= 0x005F7CFF)
-			return sb_ReadMem(paddr, sizeof(u32));
+			return sb_ReadMem(paddr);
 		if (addr >= 0x005F8000 && addr <= 0x005F9FFF)
 			return pvr_ReadReg(paddr);
 
@@ -154,7 +154,7 @@ static void DYNACALL write_elanreg(u32 paddr, u32 data)
 	{
 	case 0x5F:
 		if (addr>= 0x005F6800 && addr <= 0x005F7CFF)
-			sb_WriteMem(paddr, data, sizeof(u32));
+			sb_WriteMem(paddr, data);
 		else if (addr >= 0x005F8000 && addr <= 0x005F9FFF)
 			pvr_WriteReg(paddr, data);
 		else
diff --git a/core/hw/sh4/sh4_mmr.h b/core/hw/sh4/sh4_mmr.h
index fac9cee81..f7effda10 100644
--- a/core/hw/sh4/sh4_mmr.h
+++ b/core/hw/sh4/sh4_mmr.h
@@ -30,17 +30,17 @@ void sh4_mmr_term();
 
 void sh4_rio_reg(RegisterStruct *arr, u32 addr, RegIO flags, RegReadAddrFP *rf = nullptr, RegWriteAddrFP *wf = nullptr);
 
-#define SH4IO_REGN(mod, addr, size) ((mod)[((addr) & 255) / 4].data##size)
-#define SH4IO_REG(mod, name, size) SH4IO_REGN(mod, mod##_##name##_addr, size)
-#define SH4IO_REG_T(mod, name, size) ((mod##_##name##_type&)SH4IO_REG(mod, name, size))
+#define SH4IO_REGN(mod, addr) ((mod)[((addr) & 255) / 4].data32)
+#define SH4IO_REG(mod, name) SH4IO_REGN(mod, mod##_##name##_addr)
+#define SH4IO_REG_T(mod, name) ((mod##_##name##_type&)SH4IO_REG(mod, name))
 
-#define SH4IO_REG_OFS(mod, name, o, s, size) SH4IO_REGN(mod, mod##_##name##0_addr + (o) * (s), size)
-#define SH4IO_REG_T_OFS(mod, name, o, s, size) ((mod##_##name##_type&)SH4IO_REG_OFS(mod, name, o, s, size))
+#define SH4IO_REG_OFS(mod, name, o, s) SH4IO_REGN(mod, mod##_##name##0_addr + (o) * (s))
+#define SH4IO_REG_T_OFS(mod, name, o, s) ((mod##_##name##_type&)SH4IO_REG_OFS(mod, name, o, s))
 
 template <RegisterStruct *Module, u32 Addr, u32 Mask = 0xffffffff, u32 OrMask = 0>
 void sh4_write_reg(u32 addr, u32 data)
 {
-	SH4IO_REGN(Module, Addr, 32) = (data & Mask) | OrMask;
+	SH4IO_REGN(Module, Addr) = (data & Mask) | OrMask;
 }
 
 template<RegisterStruct *Module, u32 Addr, u32 Mask>
@@ -500,7 +500,7 @@ union BSC_BCR1_type
 };
 
 
-#define BSC_BCR1 SH4IO_REG_T(BSC,BCR1,32)
+#define BSC_BCR1 SH4IO_REG_T(BSC, BCR1)
 //extern BCR1_type BSC_BCR1;
 
 //16 bit
@@ -531,7 +531,7 @@ union BSC_BCR2_type
 
 	u16 full;
 };
-#define BSC_BCR2 SH4IO_REG_T(BSC,BCR2,16)
+#define BSC_BCR2 SH4IO_REG_T(BSC, BCR2)
 
 //32 bits
 union BSC_WCR1_type
@@ -577,7 +577,7 @@ union BSC_WCR1_type
 
 	u32 full;
 };
-#define BSC_WCR1 SH4IO_REG_T(BSC,WCR1,32)
+#define BSC_WCR1 SH4IO_REG_T(BSC, WCR1)
 
 //32 bits
 union BSC_WCR2_type
@@ -624,7 +624,7 @@ union BSC_WCR2_type
 	u32 full;
 };
 
-#define BSC_WCR2 SH4IO_REG_T(BSC,WCR2,32)
+#define BSC_WCR2 SH4IO_REG_T(BSC, WCR2)
 
 //32 bits
 union BSC_WCR3_type
@@ -672,7 +672,7 @@ union BSC_WCR3_type
 };
 
 
-#define BSC_WCR3 SH4IO_REG_T(BSC,WCR3,32)
+#define BSC_WCR3 SH4IO_REG_T(BSC, WCR3)
 
 //32 bits
 union BSC_MCR_type
@@ -720,7 +720,7 @@ union BSC_MCR_type
 };
 
 
-#define BSC_MCR SH4IO_REG_T(BSC,MCR,32)
+#define BSC_MCR SH4IO_REG_T(BSC, MCR)
 
 //16 bits
 union BSC_PCR_type
@@ -749,7 +749,7 @@ union BSC_PCR_type
 	u16 full;
 };
 
-#define BSC_PCR SH4IO_REG_T(BSC,PCR,16)
+#define BSC_PCR SH4IO_REG_T(BSC, PCR)
 
 //16 bits -> misstype on manual ? RTSCR vs RTCSR...
 union BSC_RTCSR_type
@@ -778,7 +778,7 @@ union BSC_RTCSR_type
 	u16 full;
 };
 
-#define BSC_RTCSR SH4IO_REG_T(BSC,RTCSR,16)
+#define BSC_RTCSR SH4IO_REG_T(BSC, RTCSR)
 
 //16 bits
 union BSC_RTCNT_type
@@ -800,7 +800,7 @@ union BSC_RTCNT_type
 	u16 full;
 };
 
-#define BSC_RTCNT SH4IO_REG_T(BSC,RTCNT,16)
+#define BSC_RTCNT SH4IO_REG_T(BSC, RTCNT)
 
 //16 bits
 union BSC_RTCOR_type
@@ -823,7 +823,7 @@ union BSC_RTCOR_type
 };
 
 
-#define BSC_RTCOR SH4IO_REG_T(BSC,RTCOR,16)
+#define BSC_RTCOR SH4IO_REG_T(BSC, RTCOR)
 
 //16 bits
 union BSC_RFCR_type
@@ -843,7 +843,7 @@ union BSC_RFCR_type
 	u16 full;
 };
 
-#define BSC_RFCR SH4IO_REG_T(BSC,RFCR,16)
+#define BSC_RFCR SH4IO_REG_T(BSC, RFCR)
 
 //32 bits
 union BSC_PCTRA_type
@@ -890,7 +890,7 @@ union BSC_PCTRA_type
 	u32 full;
 };
 
-#define BSC_PCTRA SH4IO_REG_T(BSC,PCTRA,32)
+#define BSC_PCTRA SH4IO_REG_T(BSC, PCTRA)
 
 //16 bits
 union BSC_PDTRA_type
@@ -966,7 +966,7 @@ union BSC_PCTRB_type
 	u32 full;
 };
 
-#define BSC_PCTRB SH4IO_REG_T(BSC,PCTRB,32)
+#define BSC_PCTRB SH4IO_REG_T(BSC, PCTRB)
 
 //16 bits
 union BSC_PDTRB_type
@@ -995,7 +995,7 @@ union BSC_PDTRB_type
 	u16 full;
 };
 
-#define BSC_PDTRB SH4IO_REG_T(BSC,PDTRB,16)
+#define BSC_PDTRB SH4IO_REG_T(BSC, PDTRB)
 
 //16 bits
 union BSC_GPIOIC_type
@@ -1024,7 +1024,7 @@ union BSC_GPIOIC_type
 	u16 full;
 };
 
-#define BSC_GPIOIC SH4IO_REG_T(BSC,GPIOIC,16)
+#define BSC_GPIOIC SH4IO_REG_T(BSC, GPIOIC)
 
 
 
@@ -1123,27 +1123,27 @@ union CCN_QACR_type
 
 
 //Types
-#define CCN_PTEH SH4IO_REG_T(CCN,PTEH,32)
-#define CCN_PTEL SH4IO_REG_T(CCN,PTEL,32)
-#define CCN_TTB SH4IO_REG(CCN,TTB,32)
-#define CCN_TEA SH4IO_REG(CCN,TEA,32)
-#define CCN_MMUCR SH4IO_REG_T(CCN,MMUCR,32)
-#define CCN_BASRA SH4IO_REG(CCN,BASRA,8)
-#define CCN_BASRB SH4IO_REG(CCN,BASRB,8)
-#define CCN_CCR SH4IO_REG_T(CCN,CCR,32)
-#define CCN_TRA SH4IO_REG(CCN,TRA,32)
-#define CCN_EXPEVT SH4IO_REG(CCN,EXPEVT,32)
-#define CCN_INTEVT SH4IO_REG(CCN,INTEVT,32)
-#define CCN_PTEA SH4IO_REG_T(CCN,PTEA,32)
+#define CCN_PTEH SH4IO_REG_T(CCN, PTEH)
+#define CCN_PTEL SH4IO_REG_T(CCN, PTEL)
+#define CCN_TTB SH4IO_REG(CCN, TTB)
+#define CCN_TEA SH4IO_REG(CCN, TEA)
+#define CCN_MMUCR SH4IO_REG_T(CCN, MMUCR)
+#define CCN_BASRA SH4IO_REG(CCN, BASRA)
+#define CCN_BASRB SH4IO_REG(CCN, BASRB)
+#define CCN_CCR SH4IO_REG_T(CCN, CCR)
+#define CCN_TRA SH4IO_REG(CCN, TRA)
+#define CCN_EXPEVT SH4IO_REG(CCN, EXPEVT)
+#define CCN_INTEVT SH4IO_REG(CCN, INTEVT)
+#define CCN_PTEA SH4IO_REG_T(CCN, PTEA)
 
-#define CCN_QACR0 ((CCN_QACR_type&)SH4IO_REG(CCN, QACR0, 32))
-#define CCN_QACR1 ((CCN_QACR_type&)SH4IO_REG(CCN, QACR1, 32))
+#define CCN_QACR0 ((CCN_QACR_type&)SH4IO_REG(CCN, QACR0))
+#define CCN_QACR1 ((CCN_QACR_type&)SH4IO_REG(CCN, QACR1))
 
-#define CPG_FRQCR SH4IO_REG(CPG,FRQCR,16)
-#define CPG_STBCR SH4IO_REG(CPG,STBCR,8)
-#define CPG_WTCNT SH4IO_REG(CPG,WTCNT,16)
-#define CPG_WTCSR SH4IO_REG(CPG,WTCSR,16)
-#define CPG_STBCR2 SH4IO_REG(CPG,STBCR2,8)
+#define CPG_FRQCR SH4IO_REG(CPG, FRQCR)
+#define CPG_STBCR SH4IO_REG(CPG, STBCR)
+#define CPG_WTCNT SH4IO_REG(CPG, WTCNT)
+#define CPG_WTCSR SH4IO_REG(CPG, WTCSR)
+#define CPG_STBCR2 SH4IO_REG(CPG, STBCR2)
 
 
 
@@ -1222,41 +1222,41 @@ extern u32 DMAC_DMATCR[4];//only 24 bits valid
 extern DMAC_CHCR_type DMAC_CHCR[4];
 */
 
-#define DMAC_SAR(x) SH4IO_REG_OFS(DMAC,SAR,x,0x10,32)
-#define DMAC_DAR(x) SH4IO_REG_OFS(DMAC,DAR,x,0x10,32)
-#define DMAC_DMATCR(x) SH4IO_REG_OFS(DMAC,DMATCR,x,0x10,32)
-#define DMAC_CHCR(x) SH4IO_REG_T_OFS(DMAC,CHCR,x,0x10,32)
+#define DMAC_SAR(x) SH4IO_REG_OFS(DMAC, SAR, x, 0x10)
+#define DMAC_DAR(x) SH4IO_REG_OFS(DMAC, DAR, x, 0x10)
+#define DMAC_DMATCR(x) SH4IO_REG_OFS(DMAC, DMATCR, x, 0x10)
+#define DMAC_CHCR(x) SH4IO_REG_T_OFS(DMAC, CHCR, x, 0x10)
 
-#define DMAC_DMAOR SH4IO_REG_T(DMAC,DMAOR,32)
+#define DMAC_DMAOR SH4IO_REG_T(DMAC, DMAOR)
 
 
 //UBC BARA 0xFF200000 0x1F200000 32 Undefined Held Held Held Iclk
-#define UBC_BARA SH4IO_REG(UBC,BARA,32)
+#define UBC_BARA SH4IO_REG(UBC, BARA)
 //UBC BAMRA 0xFF200004 0x1F200004 8 Undefined Held Held Held Iclk
-#define UBC_BAMRA SH4IO_REG(UBC,BAMRA,8)
+#define UBC_BAMRA SH4IO_REG(UBC, BAMRA)
 //UBC BBRA 0xFF200008 0x1F200008 16 0x0000 Held Held Held Iclk
-#define UBC_BBRA SH4IO_REG(UBC,BBRA,16)
+#define UBC_BBRA SH4IO_REG(UBC, BBRA)
 //UBC BARB 0xFF20000C 0x1F20000C 32 Undefined Held Held Held Iclk
-#define UBC_BARB SH4IO_REG(UBC,BARB,32)
+#define UBC_BARB SH4IO_REG(UBC, BARB)
 //UBC BAMRB 0xFF200010 0x1F200010 8 Undefined Held Held Held Iclk
-#define UBC_BAMRB SH4IO_REG(UBC,BAMRB,8)
+#define UBC_BAMRB SH4IO_REG(UBC, BAMRB)
 //UBC BBRB 0xFF200014 0x1F200014 16 0x0000 Held Held Held Iclk
-#define UBC_BBRB SH4IO_REG(UBC,BBRB,16)
+#define UBC_BBRB SH4IO_REG(UBC, BBRB)
 //UBC BDRB 0xFF200018 0x1F200018 32 Undefined Held Held Held Iclk
-#define UBC_BDRB SH4IO_REG(UBC,BDRB,32)
+#define UBC_BDRB SH4IO_REG(UBC, BDRB)
 //UBC BDMRB 0xFF20001C 0x1F20001C 32 Undefined Held Held Held Iclk
-#define UBC_BDMRB SH4IO_REG(UBC,BDMRB,32)
+#define UBC_BDMRB SH4IO_REG(UBC, BDMRB)
 //UBC BRCR 0xFF200020 0x1F200020 16 0x0000 Held Held Held Iclk
-#define UBC_BRCR SH4IO_REG(UBC,BRCR,16)
+#define UBC_BRCR SH4IO_REG(UBC, BRCR)
 
 //TCNT exists only as cached state
 //#define TMU_TCNT(x) SH4IO_REG_OFS(TMU,TCNT,x,12,32)
 
-#define TMU_TCOR(x) SH4IO_REG_OFS(TMU,TCOR,x,12,32)
-#define TMU_TCR(x) SH4IO_REG_OFS(TMU,TCR,x,12,16)
+#define TMU_TCOR(x) SH4IO_REG_OFS(TMU, TCOR, x, 12)
+#define TMU_TCR(x) SH4IO_REG_OFS(TMU, TCR, x, 12)
 
-#define TMU_TOCR SH4IO_REG(TMU,TOCR,8)
-#define TMU_TSTR SH4IO_REG(TMU,TSTR,8)
+#define TMU_TOCR SH4IO_REG(TMU, TOCR)
+#define TMU_TSTR SH4IO_REG(TMU, TSTR)
 
 
 
@@ -1287,10 +1287,10 @@ union SCIF_SCSMR2_type
 	u16 full;
 };
 
-#define SCIF_SCSMR2 SH4IO_REG_T(SCIF,SCSMR2,16)
+#define SCIF_SCSMR2 SH4IO_REG_T(SCIF, SCSMR2)
 
 //SCIF SCBRR2 0xFFE80004 0x1FE80004 8 0xFF 0xFF Held Held Pclk
-#define SCIF_SCBRR2 SH4IO_REG(SCIF,SCBRR2,8)
+#define SCIF_SCBRR2 SH4IO_REG(SCIF, SCBRR2)
 
 //SCIF SCSCR2 0xFFE80008 0x1FE80008 16 0x0000 0x0000 Held Held Pclk
 union SCIF_SCSCR2_type
@@ -1321,7 +1321,7 @@ union SCIF_SCSCR2_type
 extern SCIF_SCSCR2_type SCIF_SCSCR2;
 
 //SCIF SCFTDR2 0xFFE8000C 0x1FE8000C 8 Undefined Undefined Held Held Pclk
-#define SCIF_SCFTDR2 SH4IO_REG(SCIF,SCFTDR2,8)
+#define SCIF_SCFTDR2 SH4IO_REG(SCIF, SCFTDR2)
 
 //SCIF SCFSR2 0xFFE80010 0x1FE80010 16 0x0060 0x0060 Held Held Pclk
 union SCIF_SCFSR2_type
@@ -1381,7 +1381,7 @@ union SCIF_SCFCR2_type
 	};
 	u16 full;
 };
-#define SCIF_SCFCR2 SH4IO_REG_T(SCIF,SCFCR2,16)
+#define SCIF_SCFCR2 SH4IO_REG_T(SCIF, SCFCR2)
 
 //Read OLNY
 //SCIF SCFDR2 0xFFE8001C 0x1FE8001C 16 0x0000 0x0000 Held Held Pclk
@@ -1425,7 +1425,7 @@ union SCIF_SCSPTR2_type
 	};
 	u16 full;
 };
-#define SCIF_SCSPTR2 SH4IO_REG_T(SCIF,SCSPTR2,16)
+#define SCIF_SCSPTR2 SH4IO_REG_T(SCIF, SCSPTR2)
 
 //SCIF SCLSR2 0xFFE80024 0x1FE80024 16 0x0000 0x0000 Held Held Pclk
 union SCIF_SCLSR2_type
@@ -1440,26 +1440,26 @@ union SCIF_SCLSR2_type
 	};
 	u16 full;
 };
-#define SCIF_SCLSR2 SH4IO_REG_T(SCIF,SCLSR2,16)
+#define SCIF_SCLSR2 SH4IO_REG_T(SCIF, SCLSR2)
 
 
-#define RTC_R64CNT SH4IO_REG(RTC,R64CNT,8)
-#define RTC_RSECCNT SH4IO_REG(RTC,RSECCNT,8)
-#define RTC_RMINCNT SH4IO_REG(RTC,RMINCNT,8)
-#define RTC_RHRCNT SH4IO_REG(RTC,RHRCNT,8)
-#define RTC_RWKCNT SH4IO_REG(RTC,RWKCNT,8)
-#define RTC_RDAYCNT SH4IO_REG(RTC,RDAYCNT,8)
-#define RTC_RMONCNT SH4IO_REG(RTC,RMONCNT,8)
-#define RTC_RYRCNT SH4IO_REG(RTC,RYRCNT,16)
+#define RTC_R64CNT SH4IO_REG(RTC, R64CNT)
+#define RTC_RSECCNT SH4IO_REG(RTC, RSECCNT)
+#define RTC_RMINCNT SH4IO_REG(RTC, RMINCNT)
+#define RTC_RHRCNT SH4IO_REG(RTC, RHRCNT)
+#define RTC_RWKCNT SH4IO_REG(RTC, RWKCNT)
+#define RTC_RDAYCNT SH4IO_REG(RTC, RDAYCNT)
+#define RTC_RMONCNT SH4IO_REG(RTC, RMONCNT)
+#define RTC_RYRCNT SH4IO_REG(RTC, RYRCNT)
 
-#define RTC_RSECAR SH4IO_REG(RTC,RSECAR,8)
-#define RTC_RMINAR SH4IO_REG(RTC,RMINAR,8)
-#define RTC_RHRAR SH4IO_REG(RTC,RHRAR,8)
-#define RTC_RWKAR SH4IO_REG(RTC,RWKAR,8)
-#define RTC_RDAYAR SH4IO_REG(RTC,RDAYAR,8)
-#define RTC_RMONAR SH4IO_REG(RTC,RMONAR,8)
-#define RTC_RCR1 SH4IO_REG(RTC,RCR1,8)
-#define RTC_RCR2 SH4IO_REG(RTC,RCR2,8)
+#define RTC_RSECAR SH4IO_REG(RTC, RSECAR)
+#define RTC_RMINAR SH4IO_REG(RTC, RMINAR)
+#define RTC_RHRAR SH4IO_REG(RTC, RHRAR)
+#define RTC_RWKAR SH4IO_REG(RTC, RWKAR)
+#define RTC_RDAYAR SH4IO_REG(RTC, RDAYAR)
+#define RTC_RMONAR SH4IO_REG(RTC, RMONAR)
+#define RTC_RCR1 SH4IO_REG(RTC, RCR1)
+#define RTC_RCR2 SH4IO_REG(RTC, RCR2)
 
 
 
@@ -1514,16 +1514,16 @@ union INTC_IPRC_type
 	};
 };
 
-#define INTC_ICR SH4IO_REG_T(INTC,ICR,16)
+#define INTC_ICR SH4IO_REG_T(INTC, ICR)
 
-#define INTC_IPRA SH4IO_REG_T(INTC,IPRA,16)
-#define INTC_IPRB SH4IO_REG_T(INTC,IPRB,16)
-#define INTC_IPRC SH4IO_REG_T(INTC,IPRC,16)
+#define INTC_IPRA SH4IO_REG_T(INTC, IPRA)
+#define INTC_IPRB SH4IO_REG_T(INTC, IPRB)
+#define INTC_IPRC SH4IO_REG_T(INTC, IPRC)
 
-#define SCI_SCSMR1 SH4IO_REG(SCI, SCSMR1, 8)
-#define SCI_SCBRR1 SH4IO_REG(SCI, SCBRR1, 8)
-#define SCI_SCSCR1 SH4IO_REG(SCI, SCSCR1, 8)
-#define SCI_SCTDR1 SH4IO_REG(SCI, SCTDR1, 8)
-#define SCI_SCSSR1 SH4IO_REG(SCI, SCSSR1, 8)
-#define SCI_SCRDR1 SH4IO_REG(SCI, SCRDR1, 8)
-#define SCI_SCSPTR1 SH4IO_REG(SCI, SCSPTR1, 8)
+#define SCI_SCSMR1 SH4IO_REG(SCI, SCSMR1)
+#define SCI_SCBRR1 SH4IO_REG(SCI, SCBRR1)
+#define SCI_SCSCR1 SH4IO_REG(SCI, SCSCR1)
+#define SCI_SCTDR1 SH4IO_REG(SCI, SCTDR1)
+#define SCI_SCSSR1 SH4IO_REG(SCI, SCSSR1)
+#define SCI_SCRDR1 SH4IO_REG(SCI, SCRDR1)
+#define SCI_SCSPTR1 SH4IO_REG(SCI, SCSPTR1)