parent
a7a70f9900
commit
e94e757743
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@ -435,36 +435,42 @@ void Naomi_DmaStart(u32 addr, u32 data)
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return;
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}
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SB_GDST|=data&1;
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SB_GDST |= data & 1;
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if (SB_GDST==1)
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if (SB_GDST == 0)
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return;
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if (!m3comm.DmaStart(addr, data) && CurrentCartridge != NULL)
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{
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if (!m3comm.DmaStart(addr, data) && CurrentCartridge != NULL)
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DEBUG_LOG(NAOMI, "NAOMI-DMA start addr %08X len %d", SB_GDSTAR, SB_GDLEN);
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verify(1 == SB_GDDIR);
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u32 start = SB_GDSTAR & 0x1FFFFFE0;
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u32 len = (SB_GDLEN + 31) & ~31;
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SB_GDLEND = 0;
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while (len > 0)
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{
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DEBUG_LOG(NAOMI, "NAOMI-DMA start addr %08X len %d", SB_GDSTAR, SB_GDLEN);
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verify(1 == SB_GDDIR);
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u32 len = (SB_GDLEN + 30) & ~30;
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u32 offset = 0;
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while (len > 0)
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u32 block_len = len;
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void* ptr = CurrentCartridge->GetDmaPtr(block_len);
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if (block_len == 0)
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{
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u32 block_len = len;
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void* ptr = CurrentCartridge->GetDmaPtr(block_len);
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if (block_len == 0)
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{
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INFO_LOG(NAOMI, "Aborted DMA transfer. Read past end of cart?");
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break;
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}
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WriteMemBlock_nommu_ptr(SB_GDSTAR + offset, (u32*)ptr, block_len);
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CurrentCartridge->AdvancePtr(block_len);
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len -= block_len;
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offset += block_len;
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INFO_LOG(NAOMI, "Aborted DMA transfer. Read past end of cart?");
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break;
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}
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WriteMemBlock_nommu_ptr(start, (u32*)ptr, block_len);
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CurrentCartridge->AdvancePtr(block_len);
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len -= block_len;
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start += block_len;
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SB_GDLEND += block_len;
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}
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SB_GDSTARD = start;
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}
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else
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{
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SB_GDSTARD = SB_GDSTAR + SB_GDLEN;
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SB_GDLEND = SB_GDLEN;
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SB_GDST = 0;
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asic_RaiseInterrupt(holly_GDROM_DMA);
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}
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SB_GDST = 0;
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asic_RaiseInterrupt(holly_GDROM_DMA);
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}
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