aica: arm32 dsp dynarec. Correct dsp level when dsp disabled
This commit is contained in:
Flyinghead
parent
2f03922b43
commit
e5ca63db20
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@ -188,10 +188,10 @@
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//defaults
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#ifndef FEAT_SHREC
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#if HOST_CPU == CPU_MIPS
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#define FEAT_SHREC DYNAREC_NONE
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#else
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#if HOST_CPU == CPU_ARM || HOST_CPU == CPU_ARM64 || HOST_CPU == CPU_X86 || HOST_CPU == CPU_X64
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#define FEAT_SHREC DYNAREC_JIT
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#else
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#define FEAT_SHREC DYNAREC_NONE
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#endif
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#endif
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@ -204,7 +204,7 @@
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#endif
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#ifndef FEAT_DSPREC
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#if HOST_CPU == CPU_X86 || HOST_CPU == CPU_ARM64 || HOST_CPU == CPU_X64
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#if HOST_CPU == CPU_ARM || HOST_CPU == CPU_ARM64 || HOST_CPU == CPU_X86 || HOST_CPU == CPU_X64
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#define FEAT_DSPREC DYNAREC_JIT
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#else
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#define FEAT_DSPREC DYNAREC_NONE
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@ -0,0 +1,426 @@
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/*
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Copyright 2021 flyinghead
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This file is part of reicast.
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reicast is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 2 of the License, or
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(at your option) any later version.
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reicast is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with reicast. If not, see <https://www.gnu.org/licenses/>.
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*/
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#include "build.h"
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#if HOST_CPU == CPU_ARM && FEAT_DSPREC != DYNAREC_NONE
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#include "dsp.h"
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#include "aica.h"
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#include "aica_if.h"
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#include "hw/mem/_vmem.h"
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#include <aarch32/macro-assembler-aarch32.h>
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using namespace vixl::aarch32;
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constexpr size_t CodeSize = 4096 * 8; //32 kb, 8 pages
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#if defined(__unix__)
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alignas(4096) static u8 DynCode[CodeSize] __attribute__((section(".text")));
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#else
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#error "Unsupported platform for arm32 DSP dynarec"
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#endif
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class DSPAssembler : public MacroAssembler
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{
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public:
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DSPAssembler(u8 *code_buffer, size_t size) : MacroAssembler(code_buffer, size, A32) {}
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void compile(dsp_t *DSP)
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{
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this->DSP = DSP;
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DEBUG_LOG(AICA_ARM, "DSPAssembler::compile recompiling for arm32 at %p", GetBuffer()->GetStartAddress<void*>());
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RegisterList regList = RegisterList::Union(
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RegisterList(r4, r5, r6, r7),
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RegisterList(r8, r9, r10, lr));
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Push(regList);
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Mov(r8, (uintptr_t)&DSP->TEMP[0]); // r8 points to TEMP, right after the code
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Mov(r7, (uintptr_t)DSPData); // r7 points to DSPData
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const Register& INPUTS = r4; // 24 bits
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const Register& ACC = r5; // 26 bits - saved
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const Register& B = r10; // 26 bits - saved
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const Register& X = r6; // 24 bits
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const Register& Y = r9; // 13 bits
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Mov(ACC, 0);
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Mov(B, 0);
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Str(B, dsp_operand(&DSP->FRC_REG));
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Str(B, dsp_operand(&DSP->Y_REG));
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Str(B, dsp_operand(&DSP->ADRS_REG));
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for (int step = 0; step < 128; ++step)
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{
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u32 *mpro = &DSPData->MPRO[step * 4];
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_INST op;
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DecodeInst(mpro, &op);
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const u32 COEF = step;
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if (op.XSEL || op.YRL || (op.ADRL && op.SHIFT != 3))
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{
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if (op.IRA <= 0x1f)
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//INPUTS = DSP->MEMS[op.IRA];
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Ldr(INPUTS, dsp_operand(DSP->MEMS, op.IRA));
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else if (op.IRA <= 0x2F)
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{
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//INPUTS = DSP->MIXS[op.IRA - 0x20] << 4; // MIXS is 20 bit
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Ldr(INPUTS, dsp_operand(DSP->MIXS, op.IRA - 0x20));
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Lsl(INPUTS, INPUTS, 4);
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}
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else if (op.IRA <= 0x31)
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{
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//INPUTS = DSPData->EXTS[op.IRA - 0x30] << 8; // EXTS is 16 bits
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Ldr(INPUTS, dspdata_operand(DSPData->EXTS, op.IRA - 0x30));
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Lsl(INPUTS, INPUTS, 8);
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}
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else
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{
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Mov(INPUTS, 0);
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}
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}
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if (op.IWT)
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{
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//DSP->MEMS[op.IWA] = MEMVAL[step & 3]; // MEMVAL was selected in previous MRD
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Ldr(r1, dsp_operand(DSP->MEMVAL, step & 3));
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Str(r1, dsp_operand(DSP->MEMS, op.IWA));
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}
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// Operand sel
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// B
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if (!op.ZERO)
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{
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if (op.BSEL)
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//B = ACC;
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Mov(B, ACC);
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else
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{
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//B = DSP->TEMP[(TRA + DSP->regs.MDEC_CT) & 0x7F];
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Ldr(r1, dsp_operand(&DSP->regs.MDEC_CT));
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if (op.TRA)
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Add(r1, r1, op.TRA);
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Bfc(r1, 7, 25);
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Ldr(B, dsp_operand(DSP->TEMP, r1));
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}
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if (op.NEGB)
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//B = 0 - B;
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Rsb(B, B, 0);
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}
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// X
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const Register* X_alias = &X;
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if (op.XSEL)
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//X = INPUTS;
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X_alias = &INPUTS;
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else
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{
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//X = DSP->TEMP[(TRA + DSP->regs.MDEC_CT) & 0x7F];
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if (!op.ZERO && !op.BSEL && !op.NEGB)
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X_alias = &B;
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else
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{
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Ldr(r1, dsp_operand(&DSP->regs.MDEC_CT));
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if (op.TRA)
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Add(r1, r1, op.TRA);
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Bfc(r1, 7, 25);
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Ldr(X, dsp_operand(DSP->TEMP, r1));
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}
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}
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// Y
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if (op.YSEL == 0)
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{
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//Y = FRC_REG;
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Ldr(Y, dsp_operand(&DSP->FRC_REG));
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}
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else if (op.YSEL == 1)
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{
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//Y = DSPData->COEF[COEF] >> 3; //COEF is 16 bits
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Ldr(Y, dspdata_operand(DSPData->COEF, COEF));
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Sbfx(Y, Y, 3, 13);
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}
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else if (op.YSEL == 2)
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{
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//Y = Y_REG >> 11;
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Ldr(r1, dsp_operand(&DSP->Y_REG));
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Asr(Y, r1, 11);
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}
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else if (op.YSEL == 3)
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{
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//Y = (Y_REG >> 4) & 0x0FFF;
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Ldr(r1, dsp_operand(&DSP->Y_REG));
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Ubfx(Y, r1, 4, 12);
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}
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if (op.YRL)
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//Y_REG = INPUTS;
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Str(INPUTS, dsp_operand(&DSP->Y_REG));
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if (op.TWT || op.FRCL || op.MWT || (op.ADRL && op.SHIFT == 3) || op.EWT)
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{
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// Shifter
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// There's a 1-step delay at the output of the X*Y + B adder. So we use the ACC value from the previous step.
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if (op.SHIFT == 0)
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{
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// SHIFTED = clamp(ACC, -0x800000, 0x7FFFFF)
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Ssat(r2, 24, ACC);
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}
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else if (op.SHIFT == 1)
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{
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//SHIFTED = ACC << 1; // x2 scale
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// SHIFTED = clamp(SHIFTED, -0x800000, 0x7FFFFF)
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Ssat(r2, 24, Operand(ACC, LSL, 1));
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}
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else if (op.SHIFT == 2)
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{
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//SHIFTED = ACC << 1; // x2 scale
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Lsl(r2, ACC, 1);
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}
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else if (op.SHIFT == 3)
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{
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//SHIFTED = ACC;
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Mov(r2, ACC);
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}
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Str(r2, dsp_operand(&DSP->SHIFTED));
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}
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// ACCUM
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//ACC = (((s64)X * (s64)Y) >> 12) + B;
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Smull(r0, r1, *X_alias, Y);
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Lsr(r0, r0, 12);
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Orr(ACC, r0, Operand(r1, LSL, 20));
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if (!op.ZERO)
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Add(ACC, ACC, B);
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if (op.TWT)
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{
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//DSP->TEMP[(op.TWA + DSP->regs.MDEC_CT) & 0x7F] = SHIFTED;
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Ldr(r2, dsp_operand(&DSP->SHIFTED));
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Ldr(r1, dsp_operand(&DSP->regs.MDEC_CT));
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if (op.TWA)
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Add(r1, r1, op.TWA);
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Bfc(r1, 7, 25);
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Str(r2, dsp_operand(DSP->TEMP, r1));
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}
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if (op.FRCL)
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{
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Ldr(r2, dsp_operand(&DSP->SHIFTED));
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if (op.SHIFT == 3)
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//FRC_REG = SHIFTED & 0x0FFF;
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Ubfx(r1, r2, 0, 12);
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else
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//FRC_REG = SHIFTED >> 11;
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Asr(r1, r2, 11);
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Str(r1, dsp_operand(&DSP->FRC_REG));
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}
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if (step & 1)
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{
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const Register& ADDR = r3;
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if (op.MRD) // memory only allowed on odd. DoA inserts NOPs on even
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{
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//MEMVAL[(step + 2) & 3] = UNPACK(*(u16 *)&aica_ram[ADDR & ARAM_MASK]);
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calculateADDR(ADDR, op);
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Mov(r1, getAicaRam());
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Ldrh(r0, MemOperand(r1, ADDR));
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genCallRuntime(UNPACK);
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Mov(r2, r0);
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Str(r2, dsp_operand(DSP->MEMVAL, (step + 2) & 3));
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}
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if (op.MWT)
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{
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// *(u16 *)&aica_ram[ADDR & ARAM_MASK] = PACK(SHIFTED);
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Ldr(r0, dsp_operand(&DSP->SHIFTED));
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genCallRuntime(PACK);
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Mov(r2, r0);
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calculateADDR(ADDR, op);
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Mov(r1, getAicaRam());
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Strh(r2, MemOperand(r1, ADDR));
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}
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}
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if (op.ADRL)
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{
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if (op.SHIFT == 3)
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{
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//ADRS_REG = SHIFTED >> 12;
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Ldr(r2, dsp_operand(&DSP->SHIFTED));
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Asr(r1, r2, 12);
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}
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else
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{
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//ADRS_REG = INPUTS >> 16;
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Asr(r1, INPUTS, 16);
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}
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Str(r1, dsp_operand(&DSP->ADRS_REG));
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}
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if (op.EWT)
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{
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//DSPData->EFREG[op.EWA] = SHIFTED >> 8;
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Ldr(r1, dsp_operand(&DSP->SHIFTED));
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Asr(r1, r1, 8);
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Str(r1, dspdata_operand(DSPData->EFREG, op.EWA));
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}
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}
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Ldr(r1, dsp_operand(&DSP->regs.MDEC_CT));
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// DSP->regs.MDEC_CT--
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Subs(r1, r1, 1);
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//if (dsp.regs.MDEC_CT == 0)
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// dsp.regs.MDEC_CT = dsp.RBL + 1; // RBL is ring buffer length - 1
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Mov(eq, r1, dsp.RBL + 1);
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Str(r1, dsp_operand(&DSP->regs.MDEC_CT));
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Pop(regList);
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Mov(pc, lr);
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FinalizeCode();
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vmem_platform_flush_cache(
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GetBuffer()->GetStartAddress<char*>(), GetBuffer()->GetEndAddress<char*>(),
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GetBuffer()->GetStartAddress<void*>(), GetBuffer()->GetEndAddress<void*>());
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}
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private:
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MemOperand dsp_operand(void *data, int index = 0, u32 element_size = 4)
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{
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ptrdiff_t offset = ((u8*)data - (u8*)DSP) - offsetof(dsp_t, TEMP) + index * element_size;
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if (offset <= 4095)
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return MemOperand(r8, offset);
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Mov(r0, offset);
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return MemOperand(r8, r0);
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}
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MemOperand dsp_operand(void *data, const Register& offset_reg, u32 element_size = 4)
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{
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ptrdiff_t offset = ((u8*)data - (u8*)DSP) - offsetof(dsp_t, TEMP);
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if (offset == 0)
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return MemOperand(r8, offset_reg, LSL, element_size == 4 ? 2 : element_size == 2 ? 1 : 0);
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Mov(r0, offset);
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Add(r0, r0, Operand(offset_reg, LSL, element_size == 4 ? 2 : element_size == 2 ? 1 : 0));
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return MemOperand(r8, r0);
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}
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MemOperand dspdata_operand(void *data, int index = 0, u32 element_size = 4)
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{
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ptrdiff_t offset = ((u8*)data - (u8*)DSPData) + index * element_size;
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if (offset <= 4095)
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return MemOperand(r7, offset);
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Mov(r0, offset);
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return MemOperand(r7, r0);
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}
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template <typename R, typename... P>
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void genCallRuntime(R (*function)(P...))
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{
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ptrdiff_t offset = reinterpret_cast<uintptr_t>(function) - GetBuffer()->GetStartAddress<uintptr_t>();
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verify((offset & 3) == 0);
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if (offset >= -32 * 1024 * 1024 && offset <= 32 * 1024 * 1024)
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{
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Label function_label(offset);
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Bl(&function_label);
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}
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else
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{
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Mov(r3, reinterpret_cast<uintptr_t>(function));
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Blx(r3);
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}
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}
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void calculateADDR(const Register& ADDR, const _INST& op)
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{
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//u32 ADDR = DSPData->MADRS[op.MASA];
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Ldr(ADDR, dspdata_operand(DSPData->MADRS, op.MASA));
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if (op.ADREB)
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{
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//ADDR += ADRS_REG & 0x0FFF;
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Ldr(r1, dsp_operand(&DSP->ADRS_REG));
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Ubfx(r0, r1, 0, 12);
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Add(ADDR, ADDR, r0);
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}
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if (op.NXADR)
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//ADDR++;
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Add(ADDR, ADDR, 1);
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if (!op.TABLE)
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{
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//ADDR += DSP->regs.MDEC_CT;
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Ldr(r1, dsp_operand(&DSP->regs.MDEC_CT));
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Add(ADDR, ADDR, r1);
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//ADDR &= DSP->RBL;
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// RBL is constant for this program
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And(ADDR, ADDR, DSP->RBL);
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}
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else
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//ADDR &= 0xFFFF;
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Bfc(ADDR, 16, 16);
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//ADDR <<= 1; // Word -> byte address
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Lsl(ADDR, ADDR, 1);
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//ADDR += DSP->RBP; // RBP is already a byte address
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// RBP is constant for this program
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Add(ADDR, ADDR, DSP->RBP);
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// ADDR & ARAM_MASK
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if (ARAM_SIZE == 2*1024*1024)
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Bfc(ADDR, 21, 11);
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else if (ARAM_SIZE == 8*1024*1024)
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Bfc(ADDR, 23, 9);
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else
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die("Unsupported ARAM_SIZE");
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}
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uintptr_t getAicaRam()
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{
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return (uintptr_t)&aica_ram[0];
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}
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dsp_t *DSP = nullptr;
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};
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void dsp_recompile()
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{
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dsp.Stopped = true;
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for (int i = 127; i >= 0; --i)
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{
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u32 *IPtr = DSPData->MPRO + i * 4;
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if (IPtr[0] != 0 || IPtr[1] != 0 || IPtr[2 ]!= 0 || IPtr[3] != 0)
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{
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dsp.Stopped = false;
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break;
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}
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}
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JITWriteProtect(false);
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DSPAssembler assembler(DynCode, CodeSize);
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assembler.compile(&dsp);
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JITWriteProtect(true);
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}
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void dsp_rec_init()
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{
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u8 *pCodeBuffer;
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verify(vmem_platform_prepare_jit_block(DynCode, CodeSize, (void**)&pCodeBuffer));
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}
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void dsp_rec_step()
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{
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((void (*)())(DynCode))();
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}
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#endif
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@ -1363,7 +1363,6 @@ void AICA_Sample32()
|
|||
|
||||
//Generate 32 samples for each channel, before moving to next channel
|
||||
//much more cache efficient !
|
||||
u32 sg=0;
|
||||
for (int ch = 0; ch < 64; ch++)
|
||||
{
|
||||
for (int i=0;i<32;i++)
|
||||
|
|
@ -1373,10 +1372,8 @@ void AICA_Sample32()
|
|||
if (!Chans[ch].Step(oLeft, oRight, oDsp))
|
||||
break;
|
||||
|
||||
sg++;
|
||||
|
||||
if (oLeft + oRight == 0)
|
||||
oLeft = oRight = oDsp;
|
||||
oLeft = oRight = oDsp >> 4;
|
||||
|
||||
mxlr[i*2+0] += oLeft;
|
||||
mxlr[i*2+1] += oRight;
|
||||
|
|
|
|||
Loading…
Reference in New Issue