diff --git a/core/hw/aica/sgc_if.cpp b/core/hw/aica/sgc_if.cpp
index 2bd3d4787..bb89a5de8 100755
--- a/core/hw/aica/sgc_if.cpp
+++ b/core/hw/aica/sgc_if.cpp
@@ -398,7 +398,7 @@ struct ChannelEx
 	struct
 	{
 		s32 val;
-		__forceinline s32 GetValue() { return val >> EG_STEP_BITS;}
+		s32 GetValue() { return val >> EG_STEP_BITS;}
 		void SetValue(u32 aegb) { val = aegb << EG_STEP_BITS; }
 
 		_EG_state state=EG_Attack;
@@ -413,7 +413,7 @@ struct ChannelEx
 	struct
 	{
 		u32 value;
-		__forceinline u32 GetValue() { return value >> EG_STEP_BITS;}
+		u32 GetValue() { return value >> EG_STEP_BITS;}
 		void SetValue(u32 fegb) { value = fegb << EG_STEP_BITS; }
 
 		_EG_state state = EG_Attack;
@@ -439,7 +439,7 @@ struct ChannelEx
 		int *plfo_scale;
 		void (* alfo_calc)(ChannelEx* ch);
 		void (* plfo_calc)(ChannelEx* ch);
-		__forceinline void Step(ChannelEx* ch) { counter--;if (counter==0) { state++; counter=start_value; alfo_calc(ch);plfo_calc(ch); } }
+		void Step(ChannelEx* ch) { counter--;if (counter==0) { state++; counter=start_value; alfo_calc(ch);plfo_calc(ch); } }
 		void Reset(ChannelEx* ch) { state=0; counter=start_value; alfo_calc(ch); plfo_calc(ch); }
 		void SetStartValue(u32 nv) { start_value = nv;}
 	} lfo;
@@ -458,17 +458,20 @@ struct ChannelEx
 		quiet = false;
 		disable();
 	}
+
 	void disable()
 	{
 		enabled=false;
 		SetAegState(EG_Release);
 		AEG.SetValue(0x3FF);
 	}
+
 	void enable()
 	{
 		enabled=true;
 	}
-	__forceinline SampleType InterpolateSample()
+
+	SampleType InterpolateSample()
 	{
 		SampleType rv;
 		u32 fp=step.fp;
@@ -477,7 +480,8 @@ struct ChannelEx
 
 		return rv;
 	}
-	__forceinline bool Step(SampleType& oLeft, SampleType& oRight, SampleType& oDsp)
+
+	bool Step(SampleType& oLeft, SampleType& oRight, SampleType& oDsp)
 	{
 		if (!enabled)
 		{
@@ -545,7 +549,7 @@ struct ChannelEx
 		}
 	}
 
-	__forceinline void Step(SampleType& mixl, SampleType& mixr)
+	void Step(SampleType& mixl, SampleType& mixr)
 	{
 		SampleType oLeft,oRight,oDsp;
 
@@ -559,7 +563,7 @@ struct ChannelEx
 		mixr+=oRight;
 	}
 
-	__forceinline static void StepAll(SampleType& mixl, SampleType& mixr)
+	static void StepAll(SampleType& mixl, SampleType& mixr)
 	{
 		for (ChannelEx& channel : Chans)
 			channel.Step(mixl, mixr);
@@ -875,7 +879,7 @@ struct ChannelEx
 	} 
 };
 
-static __forceinline SampleType DecodeADPCM(u32 sample,s32 prev,s32& quant)
+static SampleType DecodeADPCM(u32 sample,s32 prev,s32& quant)
 {
 	s32 sign=1-2*(sample/8);
 
@@ -895,7 +899,7 @@ static __forceinline SampleType DecodeADPCM(u32 sample,s32 prev,s32& quant)
 }
 
 template<s32 PCMS,bool last>
-__forceinline void StepDecodeSample(ChannelEx* ch,u32 CA)
+void StepDecodeSample(ChannelEx* ch,u32 CA)
 {
 	if (!last && PCMS<2)
 		return ;
diff --git a/core/hw/arm7/arm7.cpp b/core/hw/arm7/arm7.cpp
index 8a901e5e6..531f48666 100644
--- a/core/hw/arm7/arm7.cpp
+++ b/core/hw/arm7/arm7.cpp
@@ -305,7 +305,6 @@ void aicaarm::reset()
 	reg[15].I += 4;
 }
 
-NOINLINE
 void CPUFiq()
 {
 	u32 PC = reg[R15_ARM_NEXT].I+4;
diff --git a/core/hw/pvr/helper_classes.h b/core/hw/pvr/helper_classes.h
index a478401b1..88773b5c0 100644
--- a/core/hw/pvr/helper_classes.h
+++ b/core/hw/pvr/helper_classes.h
@@ -10,10 +10,9 @@ struct List
 	bool* overrun;
 	const char *list_name;
 
-	__forceinline int used() const { return size-avail; }
-	__forceinline int bytes() const { return used()* sizeof(T); }
+	int used() const { return size-avail; }
+	int bytes() const { return used()* sizeof(T); }
 
-	NOINLINE
 	T* sig_overrun() 
 	{ 
 		*overrun |= true;
@@ -24,7 +23,6 @@ struct List
 		return daty;
 	}
 
-	__forceinline 
 	T* Append(int n=1)
 	{
 		int ad=avail-n;
@@ -40,7 +38,6 @@ struct List
 			return sig_overrun();
 	}
 
-	__forceinline 
 	T* LastPtr(int n = 1) const
 	{ 
 		return daty-n; 
diff --git a/core/hw/pvr/pvr_mem.cpp b/core/hw/pvr/pvr_mem.cpp
index 26ee43cb2..d31642cb6 100644
--- a/core/hw/pvr/pvr_mem.cpp
+++ b/core/hw/pvr/pvr_mem.cpp
@@ -88,7 +88,7 @@ static void YUV_Block8x8(const u8* inuv, const u8* iny, u8* out)
 	}
 }
 
-static INLINE void YUV_Block384(const u8 *in, u8 *out)
+static void YUV_Block384(const u8 *in, u8 *out)
 {
 	const u8 *inuv = in;
 	const u8 *iny = in + 128;
@@ -100,7 +100,7 @@ static INLINE void YUV_Block384(const u8 *in, u8 *out)
 	YUV_Block8x8(inuv+36,iny+192,p_out+YUV_x_size*8*2+8*2); //(8,8)
 }
 
-static INLINE void YUV_ConvertMacroBlock(const u8 *datap)
+static void YUV_ConvertMacroBlock(const u8 *datap)
 {
 	//do shit
 	TA_YUV_TEX_CNT++;
diff --git a/core/hw/pvr/ta.cpp b/core/hw/pvr/ta.cpp
index 4f542a29b..15c2d9ed7 100644
--- a/core/hw/pvr/ta.cpp
+++ b/core/hw/pvr/ta.cpp
@@ -204,7 +204,7 @@ static const HollyInterruptID ListEndInterrupt[5]=
 };
 
 
-static NOINLINE void DYNACALL ta_handle_cmd(u32 trans)
+static void DYNACALL ta_handle_cmd(u32 trans)
 {
 	Ta_Dma* dat=(Ta_Dma*)(ta_tad.thd_data-32);
 
@@ -511,8 +511,7 @@ void ta_vtx_SoftReset()
 	ta_cur_state = TAS_NS;
 }
 
-static INLINE
-void DYNACALL ta_thd_data32_i(const simd256_t *data)
+static void DYNACALL ta_thd_data32_i(const simd256_t *data)
 {
 	if (ta_ctx == NULL)
 	{
diff --git a/core/hw/sh4/interpr/sh4_fpu.cpp b/core/hw/sh4/interpr/sh4_fpu.cpp
index 0d403ca46..09bbbe7f9 100644
--- a/core/hw/sh4/interpr/sh4_fpu.cpp
+++ b/core/hw/sh4/interpr/sh4_fpu.cpp
@@ -44,34 +44,9 @@ static void iNimp(const char *str);
 #define WriteMemBOU16(addr,offset,data)     WriteMemU16(addr+offset,data)
 #define WriteMemBOU8(addr,offset,data)      WriteMemU8(addr+offset,data)
 
-INLINE void Denorm32(float &value)
-{
-	if (fpscr.DN)
-	{
-		u32* v=(u32*)&value;
-		if (IS_DENORMAL(v) && (*v&0x7fFFFFFF)!=0)
-		{
-			*v&=0x80000000;
-			//printf("Denormal ..\n");
-		}
-		if ((*v<=0x007FFFFF) && *v>0)
-		{
-			*v=0;
-			INFO_LOG(INTERPRETER, "Fixed +denorm");
-		}
-		else if ((*v<=0x807FFFFF) && *v>0x80000000)
-		{
-			*v=0x80000000;
-			INFO_LOG(INTERPRETER, "Fixed -denorm");
-		}
-	}
-}
-
-
 #define CHECK_FPU_32(v) v = fixNaN(v)
 #define CHECK_FPU_64(v) v = fixNaN64(v)
 
-
 //fadd <FREG_M>,<FREG_N>
 sh4op(i1111_nnnn_mmmm_0000)
 {
diff --git a/core/hw/sh4/interpr/sh4_opcodes.cpp b/core/hw/sh4/interpr/sh4_opcodes.cpp
index 3ce78c92a..9dbafabf5 100644
--- a/core/hw/sh4/interpr/sh4_opcodes.cpp
+++ b/core/hw/sh4/interpr/sh4_opcodes.cpp
@@ -1157,7 +1157,7 @@ sh4op(i0000_nnnn_1011_0011)
 
 //pref @<REG_N>
 template<bool mmu_on>
-INLINE void DYNACALL do_sqw(u32 Dest)
+void DYNACALL do_sqw(u32 Dest)
 {
 	//TODO : Check for enabled store queues ?
 	u32 Address;
diff --git a/core/hw/sh4/sh4_core.h b/core/hw/sh4/sh4_core.h
index 86bc96729..94f1091f2 100644
--- a/core/hw/sh4/sh4_core.h
+++ b/core/hw/sh4/sh4_core.h
@@ -40,7 +40,7 @@ union DoubleReg
 	f32 sgl[2];
 };
 
-static INLINE f64 GetDR(u32 n)
+static inline f64 GetDR(u32 n)
 {
 #ifdef TRACE
 	if (n>7)
@@ -54,7 +54,7 @@ static INLINE f64 GetDR(u32 n)
 	return t.dbl;
 }
 
-static INLINE f64 GetXD(u32 n)
+static inline f64 GetXD(u32 n)
 {
 #ifdef TRACE
 	if (n>7)
@@ -68,7 +68,7 @@ static INLINE f64 GetXD(u32 n)
 	return t.dbl;
 }
 
-static INLINE void SetDR(u32 n,f64 val)
+static inline void SetDR(u32 n,f64 val)
 {
 #ifdef TRACE
 	if (n>7)
@@ -82,7 +82,7 @@ static INLINE void SetDR(u32 n,f64 val)
 	fr[(n<<1) | 0]=t.sgl[1];
 }
 
-static INLINE void SetXD(u32 n,f64 val)
+static inline void SetXD(u32 n,f64 val)
 {
 #ifdef TRACE
 	if (n>7)
@@ -104,7 +104,7 @@ struct SH4ThrownException {
 	u32 callVect;
 };
 
-static INLINE void RaiseFPUDisableException()
+static inline void RaiseFPUDisableException()
 {
 	if (config::FullMMU)
 	{
@@ -113,7 +113,7 @@ static INLINE void RaiseFPUDisableException()
 	}
 }
 
-static INLINE void AdjustDelaySlotException(SH4ThrownException& ex)
+static inline void AdjustDelaySlotException(SH4ThrownException& ex)
 {
 	ex.epc -= 2;
 	if (ex.expEvn == 0x800)	// FPU disable exception
@@ -123,7 +123,7 @@ static INLINE void AdjustDelaySlotException(SH4ThrownException& ex)
 }
 
 // The SH4 sets the signaling bit to 0 for qNaN (unlike all recent CPUs). Some games rely on this.
-static INLINE f32 fixNaN(f32 f)
+static inline f32 fixNaN(f32 f)
 {
 #ifdef STRICT_MODE
 	u32& hex = *(u32 *)&f;
@@ -140,7 +140,7 @@ static INLINE f32 fixNaN(f32 f)
 	return f;
 }
 
-static INLINE f64 fixNaN64(f64 f)
+static inline f64 fixNaN64(f64 f)
 {
 #ifdef STRICT_MODE
 	u64& hex = *(u64 *)&f;
diff --git a/core/hw/sh4/sh4_core_regs.cpp b/core/hw/sh4/sh4_core_regs.cpp
index c488f5e67..6f96ee4b3 100644
--- a/core/hw/sh4/sh4_core_regs.cpp
+++ b/core/hw/sh4/sh4_core_regs.cpp
@@ -10,12 +10,12 @@
 Sh4RCB* p_sh4rcb;
 sh4_if  sh4_cpu;
 
-static INLINE void ChangeGPR()
+static void ChangeGPR()
 {
 	std::swap((u32 (&)[8])r, r_bank);
 }
 
-static INLINE void ChangeFP()
+static void ChangeFP()
 {
 	std::swap((f32 (&)[16])Sh4cntx.xffr, *(f32 (*)[16])&Sh4cntx.xffr[16]);
 }
diff --git a/core/hw/sh4/sh4_opcode_list.h b/core/hw/sh4/sh4_opcode_list.h
index 2335d6b47..e2c215954 100644
--- a/core/hw/sh4/sh4_opcode_list.h
+++ b/core/hw/sh4/sh4_opcode_list.h
@@ -51,27 +51,27 @@ struct sh4_opcodelistentry
 		strcpy(strout, text.c_str());
 	}
 
-	INLINE bool SetPC() const
+	bool SetPC() const
 	{
 		return (type & WritesPC)!=0;
 	}
 
-	INLINE bool NeedPC() const
+	bool NeedPC() const
 	{
 		return (type & ReadsPC)!=0;
 	}
 
-	INLINE bool SetSR() const
+	bool SetSR() const
 	{
 		return (type & WritesSR)!=0;
 	}
 
-	INLINE bool SetFPSCR() const
+	bool SetFPSCR() const
 	{
 		return (type & WritesFPSCR)!=0;
 	}
 
-	INLINE bool IsFloatingPoint() const
+	bool IsFloatingPoint() const
 	{
 		return (type & UsesFPU) != 0;
 	}
diff --git a/core/oslib/oslib.h b/core/oslib/oslib.h
index e5803d16b..3ffb874a5 100644
--- a/core/oslib/oslib.h
+++ b/core/oslib/oslib.h
@@ -18,7 +18,7 @@ void os_UninstallFaultHandler();
 #include <intrin.h>
 #endif
 
-u32 static INLINE bitscanrev(u32 v)
+u32 static inline bitscanrev(u32 v)
 {
 #ifdef __GNUC__
 	return 31-__builtin_clz(v);
diff --git a/core/rend/TexCache.h b/core/rend/TexCache.h
index 1d16de3a6..28145ca5b 100644
--- a/core/rend/TexCache.h
+++ b/core/rend/TexCache.h
@@ -91,31 +91,33 @@ public:
 		pixels_per_line = 1 << level;
 	}
 
-	__forceinline pixel_type *data(u32 x = 0, u32 y = 0)
+	pixel_type *data(u32 x = 0, u32 y = 0)
 	{
 		return p_current_mipmap + pixels_per_line * y + x;
 	}
 
-	__forceinline void prel(u32 x, pixel_type value)
+	void prel(u32 x, pixel_type value)
 	{
 		p_current_pixel[x] = value;
 	}
 
-	__forceinline void prel(u32 x, u32 y, pixel_type value)
+	void prel(u32 x, u32 y, pixel_type value)
 	{
 		p_current_pixel[y * pixels_per_line + x] = value;
 	}
 
-	__forceinline void rmovex(u32 value)
+	void rmovex(u32 value)
 	{
 		p_current_pixel += value;
 	}
-	__forceinline void rmovey(u32 value)
+
+	void rmovey(u32 value)
 	{
 		p_current_line += pixels_per_line * value;
 		p_current_pixel = p_current_line;
 	}
-	__forceinline void amove(u32 x_m, u32 y_m)
+
+	void amove(u32 x_m, u32 y_m)
 	{
 		//p_current_pixel=p_buffer_start;
 		p_current_line = p_current_mipmap + pixels_per_line * y_m;
diff --git a/core/rend/gles/gldraw.cpp b/core/rend/gles/gldraw.cpp
index e9d124f3b..1054afc3f 100644
--- a/core/rend/gles/gldraw.cpp
+++ b/core/rend/gles/gldraw.cpp
@@ -102,8 +102,7 @@ static void SetBaseClipping()
 }
 
 template <u32 Type, bool SortingEnabled>
-__forceinline
-	void SetGPState(const PolyParam* gp,u32 cflip=0)
+void SetGPState(const PolyParam* gp,u32 cflip=0)
 {
 	if (gp->pcw.Texture && gp->tsp.FilterMode > 1 && Type != ListType_Punch_Through && gp->tcw.MipMapped == 1)
 	{
diff --git a/core/stdclass.h b/core/stdclass.h
index eebd96ca5..deca86406 100644
--- a/core/stdclass.h
+++ b/core/stdclass.h
@@ -85,7 +85,7 @@ public:
 		std::memset(data, 0, size);
 	}
 
-	INLINE u8& operator [](unsigned i) {
+	u8& operator [](unsigned i) {
 #ifdef MEM_BOUND_CHECK
         if (i >= size)
 		{
diff --git a/core/types.h b/core/types.h
index cb9c23490..e73d66a99 100644
--- a/core/types.h
+++ b/core/types.h
@@ -1,17 +1,6 @@
 #pragma once
-
 #include "build.h"
 
-#ifndef _MSC_VER
-#ifndef __forceinline
-#define __forceinline inline
-#endif
-#ifndef _WIN32
-#define __debugbreak
-#endif
-#endif
-
-
 #if HOST_CPU == CPU_X86
 	#ifdef _MSC_VER
 	#define DYNACALL  __fastcall
@@ -42,17 +31,8 @@ typedef uint64_t u64;
 typedef float f32;
 typedef double f64;
 
-#ifdef _M_X64
-#undef X86
-#define X64
-#endif
-
 typedef size_t unat;
 
-#ifdef X64
-typedef u64 unat;
-#endif
-
 //intc function pointer and enums
 enum HollyInterruptType
 {
@@ -172,15 +152,6 @@ inline static void JITWriteProtect(bool enabled) {
 #include <map>
 #include <stdexcept>
 
-#define INLINE __forceinline
-
-//no inline -- fixme
-#ifdef _MSC_VER
-#define NOINLINE __declspec(noinline)
-#else
-#define NOINLINE __attribute__ ((noinline))
-#endif
-
 #ifdef _MSC_VER
 #define likely(x) x
 #define unlikely(x) x
diff --git a/shell/libretro/libretro_core_options.h b/shell/libretro/libretro_core_options.h
index 8a4aefc66..7397fc204 100644
--- a/shell/libretro/libretro_core_options.h
+++ b/shell/libretro/libretro_core_options.h
@@ -1529,7 +1529,7 @@ struct retro_core_options_v2 *options_intl[RETRO_LANGUAGE_LAST] = {
  *   be as painless as possible for core devs)
  */
 
-static INLINE void libretro_set_core_options(retro_environment_t environ_cb,
+static inline void libretro_set_core_options(retro_environment_t environ_cb,
       bool *categories_supported)
 {
    unsigned version  = 0;