serial: fix RDF and TDFE status bits
RDF and TDFE can't be reset if tx/rx fifo is below/above trigger Remove rx overrun check Proper reset of scif state Fixes maxspeed, vonot and hell gate battle cable. Tetris connects but still has input responsiveness issues. sh4 mmr: use unnamed bitfields
This commit is contained in:
Flyinghead
parent
a18e3701c6
commit
cb518b5481
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@ -107,6 +107,7 @@ public:
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void receiveBreak() override;
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void init();
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void term();
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void reset();
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void serialize(Serializer& ser);
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void deserialize(Deserializer& deser);
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@ -120,11 +121,25 @@ public:
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void SCSPTR2_write(u16 data);
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static void SCBRR2_write(u32 addr, u8 data);
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static void SCSMR2_write(u32 addr, u16 data);
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static void SCSCR2_write(u32 addr, u16 data);
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void SCSCR2_write(u16 data);
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static SCIFSerialPort& Instance();
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private:
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enum StatusBit {
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DR = 0x01,
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RDF = 0x02,
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PER = 0x04,
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FER = 0x08,
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BRK = 0x10,
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TDFE = 0x20,
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TEND = 0x40,
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ER = 0x80,
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};
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void setStatusBit(StatusBit bit);
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bool isTDFE() const;
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bool isRDF() const;
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void updateBaudRate();
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void setBreak(bool on);
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void sendBreak();
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@ -64,15 +64,22 @@ int SCIFSerialPort::schedCallback(int tag, int cycles, int lag, void *arg)
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}
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}
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bool SCIFSerialPort::isTDFE() const {
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return (int)txFifo.size() <= 1 << (3 - SCIF_SCFCR2.TTRG);
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}
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bool SCIFSerialPort::isRDF() const {
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constexpr u32 trigLevels[] { 1, 4, 8, 14 };
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return rxFifo.size() >= trigLevels[SCIF_SCFCR2.RTRG];
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}
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bool SCIFSerialPort::txDone()
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{
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if (!transmitting || SCIF_SCFCR2.TFRST == 1)
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return false;
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if (txFifo.empty())
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{
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SCIF_SCFSR2.TEND = 1;
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SCIF_SCFSR2.TDFE = 1; // should not be set since the tx fifo hasn't changed but vonot needs it
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updateInterrupts();
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setStatusBit(TEND);
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transmitting = false;
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return false; // don't reschedule
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}
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@ -80,9 +87,8 @@ bool SCIFSerialPort::txDone()
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txFifo.pop_front();
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if (pipe != nullptr)
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pipe->write(v);
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u32 txTrigger = 1 << (3 - SCIF_SCFCR2.TTRG);
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if (txFifo.size() <= txTrigger) {
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SCIF_SCFSR2.TDFE = 1;
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if (isTDFE()) {
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setStatusBit(TDFE);
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updateInterrupts();
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}
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return true;
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@ -92,13 +98,6 @@ void SCIFSerialPort::rxSched()
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{
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if (pipe == nullptr)
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return;
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// FIXME fifo size checked to avoid overruns but incorrect
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if (rxFifo.size() >= 16)
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{
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SCIF_SCFSR2.RDF = 1;
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updateInterrupts();
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return;
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}
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if (pipe->available() > 0)
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{
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@ -115,9 +114,8 @@ void SCIFSerialPort::rxSched()
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else
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{
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rxFifo.push_back(v);
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constexpr u32 trigLevels[] { 1, 4, 8, 14 };
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if (rxFifo.size() >= trigLevels[SCIF_SCFCR2.RTRG]) {
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SCIF_SCFSR2.RDF = 1;
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if (isRDF()) {
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setStatusBit(RDF);
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updateInterrupts();
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}
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}
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@ -125,7 +123,7 @@ void SCIFSerialPort::rxSched()
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// TODO fifo might have been emptied since last rx
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else if (!rxFifo.empty())
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{
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SCIF_SCFSR2.DR = 1;
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setStatusBit(DR);
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updateInterrupts();
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}
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}
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@ -154,9 +152,9 @@ void SCIFSerialPort::SCFTDR2_write(u8 data)
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if (pipe != nullptr)
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pipe->write(data);
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transmitting = true;
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// Need to reschedule so it's doesn't happen too early (f355)
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// Need to reschedule so it doesn't happen too early (f355)
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sh4_sched_request(schedId, frameSize * cyclesPerBit);
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SCIF_SCFSR2.TDFE = 1; // immediately transfer SCFTDR2 into the shift register
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setStatusBit(TDFE); // immediately transfer SCFTDR2 into the shift register
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updateInterrupts();
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}
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else if (txFifo.size() < 16) {
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@ -180,19 +178,30 @@ u16 SCIFSerialPort::readStatus()
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return SCIF_SCFSR2.full;
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}
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void SCIFSerialPort::setStatusBit(StatusBit bit)
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{
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statusLastRead &= ~bit;
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SCIF_SCFSR2.full |= bit;
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}
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// SCIF_SCFSR2 write - Serial Status Register
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void SCIFSerialPort::writeStatus(u16 data)
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{
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data = data | ~0x00f3 | ~statusLastRead;
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// RDF and TDFE cannot be reset until the trigger level is reached
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if (isRDF())
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data |= RDF;
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if (isTDFE())
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data |= TDFE;
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SCIF_LOG("SCIF_SCFSR2.reset %s%s%s%s%s%s%s%s",
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(data & 0x80) ? "" : "ER ",
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(data & 0x40) ? "" : "TEND ",
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(data & 0x20) ? "" : "TDFE ",
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(data & 0x10) ? "" : "BRK ",
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(data & 0x08) ? "" : "FER ",
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(data & 0x04) ? "" : "PER ",
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(data & 0x02) ? "" : "RDF ",
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(data & 0x01) ? "" : "DR");
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(data & ER) ? "" : "ER ",
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(data & TEND) ? "" : "TEND ",
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(data & TDFE) ? "" : "TDFE ",
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(data & BRK) ? "" : "BRK ",
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(data & FER) ? "" : "FER ",
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(data & PER) ? "" : "PER ",
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(data & RDF) ? "" : "RDF ",
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(data & DR) ? "" : "DR");
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SCIF_SCFSR2.full &= data;
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statusLastRead &= data;
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@ -235,18 +244,17 @@ static u16 SCSCR2_read(u32 addr)
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return SCIF_SCSCR2.full;
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}
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void SCIFSerialPort::SCSCR2_write(u32 addr, u16 data)
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void SCIFSerialPort::SCSCR2_write(u16 data)
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{
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SCIF_SCSCR2.full = data & 0x00fa;
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if (SCIF_SCSCR2.TE == 0)
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{
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SCIF_SCFSR2.TEND = 1;
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//SCIF_SCFSR2.TDFE = 1; // TODO not sure about this one
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setStatusBit(TEND);
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// TE must be cleared to send a break
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Instance().setBreak(SCIF_SCSPTR2.SPB2IO == 1 && SCIF_SCSPTR2.SPB2DT == 0);
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setBreak(SCIF_SCSPTR2.SPB2IO == 1 && SCIF_SCSPTR2.SPB2DT == 0);
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}
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else {
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Instance().setBreak(false);
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setBreak(false);
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}
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updateInterrupts();
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SCIF_LOG("SCIF_SCSCR2= %s%s%s%s%s",
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@ -307,8 +315,8 @@ void SCIFSerialPort::SCFCR2_write(u16 data)
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{
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// when TFRST 1 -> 0
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// seems to help tetris send data during sync
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SCIF_SCFSR2.TEND = 1;
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SCIF_SCFSR2.TDFE = 1;
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setStatusBit(TEND);
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setStatusBit(TDFE);
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updateInterrupts();
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}
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SCIF_SCFCR2.full = data & 0x00ff;
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@ -346,7 +354,7 @@ void SCIFSerialPort::SCSMR2_write(u32 addr, u16 data)
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void SCIFSerialPort::receiveBreak()
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{
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SCIF_LOG("Break received");
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SCIF_SCFSR2.BRK = 1;
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setStatusBit(BRK);
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updateInterrupts();
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}
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@ -377,6 +385,16 @@ void SCIFSerialPort::term()
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}
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}
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void SCIFSerialPort::reset()
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{
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sh4_sched_request(brkSchedId, -1);
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transmitting = false;
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statusLastRead = 0;
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txFifo.clear();
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rxFifo.clear();
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updateBaudRate();
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}
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void SCIFSerialPort::serialize(Serializer& ser)
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{
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sh4_sched_serialize(ser, schedId);
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@ -553,7 +571,7 @@ void SCIFRegisters::init()
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setWriteHandler<SCIF_SCBRR2_addr, u8>(SCIFSerialPort::SCBRR2_write);
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//SCIF SCSCR2 0xFFE80008 0x1FE80008 16 0x0000 0x0000 Held Held Pclk
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setHandlers<SCIF_SCSCR2_addr>(SCSCR2_read, SCIFSerialPort::SCSCR2_write);
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setHandlers<SCIF_SCSCR2_addr>(SCSCR2_read, SINGLETON_FORWARD(SCIFSerialPort::Instance(), SCSCR2_write));
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//SCIF SCFTDR2 0xFFE8000C 0x1FE8000C 8 Undefined Undefined Held Held Pclk
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setWriteOnly<SCIF_SCFTDR2_addr>(SINGLETON_FORWARD(SCIFSerialPort::Instance(), SCFTDR2_write));
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@ -605,6 +623,7 @@ void SCIFRegisters::reset(bool hard)
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if (hard)
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SCIFSerialPort::Instance().setPipe(nullptr);
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SCIFSerialPort::Instance().reset();
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}
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void SCIFRegisters::term()
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@ -435,7 +435,7 @@ union BSC_BCR1_type
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struct
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{
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u32 A56PCM : 1;
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u32 res_0 : 1;
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u32 : 1;
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u32 DRAMTP0 : 1;
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u32 DRAMTP1 : 1;
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u32 DRAMTP2 : 1;
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@ -452,20 +452,17 @@ union BSC_BCR1_type
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u32 HIZCNT : 1;
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u32 HIZMEM : 1;
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//16
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u32 res_1 : 1;
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u32 : 1;
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u32 MEMMPX : 1;
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u32 PSHR : 1;
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u32 BREQEN : 1;
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u32 A4MBC : 1;
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u32 A1MBC : 1;
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u32 res_2 : 1;
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u32 res_3 : 1;
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u32 : 2;
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//24
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u32 OPUP : 1;
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u32 IPUP : 1;
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u32 res_4 : 1;
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u32 res_5 : 1;
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u32 res_6 : 1;
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u32 : 3;
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u32 A0MPX : 1; // Set to 1 (area 0 is mpx)
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u32 MASTER : 1; // What is it on the Dreamcast ?
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u32 ENDIAN : 1; // This is 1 on the Dreamcast
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@ -483,7 +480,7 @@ union BSC_BCR2_type
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struct
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{
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u32 PORTEN : 1;
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u32 res_0 : 1;
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u32 : 1;
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u32 A0SZ0 : 1;
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u32 A1SZ1 : 1;
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u32 A2SZ0 : 1;
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@ -514,38 +511,38 @@ union BSC_WCR1_type
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u32 A0IW0 : 1;
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u32 A0IW1 : 1;
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u32 A0IW2 : 1;
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u32 res_0 : 1;
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u32 : 1;
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u32 A1IW0 : 1;
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u32 A1IW1 : 1;
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u32 A1IW2 : 1;
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u32 res_1 : 1;
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u32 : 1;
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//8
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u32 A2IW0 : 1;
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u32 A2IW1 : 1;
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u32 A2IW2 : 1;
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u32 res_2 : 1;
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u32 : 1;
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u32 A3IW0 : 1;
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u32 A3IW1 : 1;
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u32 A3IW2 : 1;
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u32 res_3 : 1;
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u32 : 1;
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//16
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u32 A4IW0 : 1;
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u32 A4IW1 : 1;
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u32 A4IW2 : 1;
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u32 res_4 : 1;
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u32 : 1;
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u32 A5IW0 : 1;
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u32 A5IW1 : 1;
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u32 A5IW2 : 1;
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u32 res_5 : 1;
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u32 : 1;
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//24
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u32 A6IW0 : 1;
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u32 A6IW1 : 1;
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u32 A6IW2 : 1;
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u32 res_6 : 1;
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u32 : 1;
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u32 DMAIW0 : 1;
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u32 DMAIW1 : 1;
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u32 DMAIW2 : 1;
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u32 res_7 : 1;
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u32 : 1;
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};
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u32 full;
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@ -570,12 +567,12 @@ union BSC_WCR2_type
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u32 A2W0 : 1;
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u32 A2W1 : 1;
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u32 A2W2 : 1;
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u32 res_0 : 1;
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u32 : 1;
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u32 A3W0 : 1;
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u32 A3W1 : 1;
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u32 A3W2 : 1;
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//16
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u32 res_1 : 1;
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u32 : 1;
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u32 A4W0 : 1;
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u32 A4W1 : 1;
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u32 A4W2 : 1;
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@ -607,38 +604,34 @@ union BSC_WCR3_type
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u32 A0H0 : 1;
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u32 A0H1 : 1;
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u32 A0S0 : 1;
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u32 res_0 : 1;
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u32 : 1;
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u32 A1H0 : 1; //TODO: check if this is correct, on the manual it says A1H0 .. typo in the manual ?
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u32 A1H1 : 1;
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u32 A1S0 : 1;
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u32 res_1 : 1;
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u32 : 1;
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//8
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u32 A2H0 : 1;
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u32 A2H1 : 1;
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u32 A2S0 : 1;
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u32 res_2 : 1;
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u32 : 1;
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u32 A3H0 : 1;
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u32 A3H1 : 1;
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u32 A3S0 : 1;
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u32 res_3 : 1;
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u32 : 1;
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//16
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u32 A4H0 : 1;
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u32 A4H1 : 1;
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u32 A4S0 : 1;
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u32 res_4 : 1;
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u32 : 1;
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u32 A5H0 : 1;
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u32 A5H1 : 1;
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u32 A5S0 : 1;
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u32 res_5 : 1;
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u32 : 1;
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//24
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u32 A6H0 : 1;
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u32 A6H1 : 1;
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u32 A6S0 : 1;
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u32 res_6 : 1;
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u32 res_7 : 1;
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u32 res_8 : 1;
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u32 res_9 : 1;
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u32 res_10 : 1;
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u32 : 5;
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};
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u32 full;
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@ -672,16 +665,14 @@ union BSC_MCR_type
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//16
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u32 RCD0 : 1;
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u32 RCD1 : 1;
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u32 res_0 : 1;
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u32 : 1;
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u32 TPC0 : 1;
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u32 TPC1 : 1;
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u32 TPC2 : 1;
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u32 res_1 : 1;
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u32 : 1;
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u32 TCAS : 1;
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//24
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u32 res_2 : 1;
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u32 res_3 : 1;
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u32 res_4 : 1;
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u32 : 3;
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u32 TRC0 : 1;
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u32 TRC1 : 1;
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u32 TRC2 : 1;
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@ -738,14 +729,7 @@ union BSC_RTCSR_type
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u32 CMIE : 1;
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u32 CMF : 1;
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//8
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u32 res_0 : 1;
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u32 res_1 : 1;
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u32 res_2 : 1;
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u32 res_3 : 1;
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u32 res_4 : 1;
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u32 res_5 : 1;
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u32 res_6 : 1;
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u32 res_7 : 1;
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u32 : 8;
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//16
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};
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u16 full;
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@ -760,14 +744,7 @@ union BSC_RTCNT_type
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{
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u32 VALUE : 8;
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//8
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u32 res_0 : 1;
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u32 res_1 : 1;
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u32 res_2 : 1;
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u32 res_3 : 1;
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u32 res_4 : 1;
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u32 res_5 : 1;
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u32 res_6 : 1;
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u32 res_7 : 1;
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u32 : 8;
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//16
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};
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u16 full;
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@ -782,14 +759,7 @@ union BSC_RTCOR_type
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{
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u32 VALUE : 8;
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//8
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u32 res_0 : 1;
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u32 res_1 : 1;
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u32 res_2 : 1;
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u32 res_3 : 1;
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u32 res_4 : 1;
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u32 res_5 : 1;
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u32 res_6 : 1;
|
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u32 res_7 : 1;
|
||||
u32 : 8;
|
||||
//16
|
||||
};
|
||||
u16 full;
|
||||
|
|
@ -804,13 +774,7 @@ union BSC_RFCR_type
|
|||
struct
|
||||
{
|
||||
u32 VALUE : 10;
|
||||
//10
|
||||
u32 res_2 : 1;
|
||||
u32 res_3 : 1;
|
||||
u32 res_4 : 1;
|
||||
u32 res_5 : 1;
|
||||
u32 res_6 : 1;
|
||||
u32 res_7 : 1;
|
||||
u32 : 6;
|
||||
//16
|
||||
};
|
||||
u16 full;
|
||||
|
|
@ -908,32 +872,7 @@ union BSC_PCTRB_type
|
|||
u32 PB19IO : 1;
|
||||
u32 PB19PUP : 1;
|
||||
//8
|
||||
u32 res_0 : 1;
|
||||
u32 res_1 : 1;
|
||||
u32 res_2 : 1;
|
||||
u32 res_3 : 1;
|
||||
u32 res_4 : 1;
|
||||
u32 res_5 : 1;
|
||||
u32 res_6 : 1;
|
||||
u32 res_7 : 1;
|
||||
//16
|
||||
u32 res_8 : 1;
|
||||
u32 res_9 : 1;
|
||||
u32 res_10 : 1;
|
||||
u32 res_11 : 1;
|
||||
u32 res_12 : 1;
|
||||
u32 res_13 : 1;
|
||||
u32 res_14 : 1;
|
||||
u32 res_15 : 1;
|
||||
//24
|
||||
u32 res_16 : 1;
|
||||
u32 res_17 : 1;
|
||||
u32 res_18 : 1;
|
||||
u32 res_19 : 1;
|
||||
u32 res_20 : 1;
|
||||
u32 res_21 : 1;
|
||||
u32 res_22 : 1;
|
||||
u32 res_23 : 1;
|
||||
u32 :24;
|
||||
};
|
||||
|
||||
u32 full;
|
||||
|
|
@ -950,19 +889,7 @@ union BSC_PDTRB_type
|
|||
u32 PB17DT : 1;
|
||||
u32 PB18DT : 1;
|
||||
u32 PB19DT : 1;
|
||||
u32 res_0 : 1;
|
||||
u32 res_1 : 1;
|
||||
u32 res_2 : 1;
|
||||
u32 res_3 : 1;
|
||||
//8
|
||||
u32 res_4 : 1;
|
||||
u32 res_5 : 1;
|
||||
u32 res_6 : 1;
|
||||
u32 res_7 : 1;
|
||||
u32 res_8 : 1;
|
||||
u32 res_9 : 1;
|
||||
u32 res_10 : 1;
|
||||
u32 res_11 : 1;
|
||||
u32 :12;
|
||||
//16
|
||||
};
|
||||
u16 full;
|
||||
|
|
@ -1006,7 +933,7 @@ union CCN_PTEH_type
|
|||
struct
|
||||
{
|
||||
u32 ASID : 8; //0-7 ASID
|
||||
u32 res : 2; //8,9 reserved
|
||||
u32 : 2;
|
||||
u32 VPN : 22; //10-31 VPN
|
||||
};
|
||||
u32 reg_data;
|
||||
|
|
@ -1026,9 +953,9 @@ union CCN_PTEL_type
|
|||
u32 SZ1 : 1;
|
||||
|
||||
u32 V : 1;
|
||||
u32 res_0 : 1;
|
||||
u32 : 1;
|
||||
u32 PPN : 19; //PPN 10-28
|
||||
u32 res_1 : 3;
|
||||
u32 : 3;
|
||||
};
|
||||
u32 reg_data;
|
||||
};
|
||||
|
|
@ -1058,7 +985,7 @@ union CCN_PTEA_type
|
|||
{
|
||||
u32 SA : 3;
|
||||
u32 TC : 1;
|
||||
u32 res : 28;
|
||||
u32 : 28;
|
||||
};
|
||||
u32 reg_data;
|
||||
};
|
||||
|
|
@ -1071,16 +998,16 @@ union CCN_CCR_type
|
|||
u32 WT : 1;
|
||||
u32 CB : 1;
|
||||
u32 OCI : 1;
|
||||
u32 res : 1;
|
||||
u32 : 1;
|
||||
u32 ORA : 1;
|
||||
u32 res_1 : 1;
|
||||
u32 : 1;
|
||||
u32 OIX : 1;
|
||||
u32 ICE : 1;
|
||||
u32 res_2 : 2;
|
||||
u32 : 2;
|
||||
u32 ICI : 1;
|
||||
u32 res_3 : 3;
|
||||
u32 : 3;
|
||||
u32 IIX : 1;
|
||||
u32 res_4 : 16;
|
||||
u32 : 16;
|
||||
};
|
||||
u32 reg_data;
|
||||
};
|
||||
|
|
@ -1089,9 +1016,9 @@ union CCN_QACR_type
|
|||
{
|
||||
struct
|
||||
{
|
||||
u32 res : 2;
|
||||
u32 : 2;
|
||||
u32 Area : 3;
|
||||
u32 res_1 : 27;
|
||||
u32 : 27;
|
||||
};
|
||||
u32 reg_data;
|
||||
};
|
||||
|
|
@ -1129,39 +1056,28 @@ union DMAC_CHCR_type
|
|||
u32 DE : 1; //Channel Enable
|
||||
u32 TE : 1; //Transfer End
|
||||
u32 IE : 1; //Interrupt Enable
|
||||
u32 res0 : 1;
|
||||
u32 : 1;
|
||||
|
||||
u32 TS : 3; //Transmit Size
|
||||
//u32 TS1 :1;
|
||||
//u32 TS2 :1;
|
||||
u32 TM : 1; //Transmit Mode
|
||||
|
||||
u32 RS : 4; //Resource Select
|
||||
//u32 RS1 :1;
|
||||
//u32 RS2 :1;
|
||||
//u32 RS3 :1;
|
||||
|
||||
u32 SM : 2; //SRC mode
|
||||
//u32 SM1 :1;
|
||||
u32 DM : 2; //DST mode
|
||||
//u32 DM1 :1;
|
||||
|
||||
u32 AL : 1; //Acknowledge Level
|
||||
u32 AM : 1; //Acknowledge Mode
|
||||
u32 RL : 1; //In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, this bit is invalid.
|
||||
u32 DS : 1; //In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, it is valid in CHCR0<52>CHCR3.
|
||||
|
||||
u32 res1 : 4;
|
||||
u32 : 4;
|
||||
|
||||
u32 DTC : 1;
|
||||
u32 DSA : 3;
|
||||
//u32 DSA1:1;
|
||||
//u32 DSA2:1;
|
||||
|
||||
u32 STC : 1;
|
||||
u32 SSA : 3;
|
||||
//u32 SSA1:1;
|
||||
//u32 SSA2:1;
|
||||
};
|
||||
u32 full;
|
||||
};
|
||||
|
|
@ -1173,19 +1089,16 @@ union DMAC_DMAOR_type
|
|||
u32 DME : 1;
|
||||
u32 NMIF : 1;
|
||||
u32 AE : 1;
|
||||
u32 res0 : 1;
|
||||
|
||||
u32 : 1;
|
||||
u32 COD : 1;
|
||||
u32 res1 : 3;
|
||||
u32 : 3;
|
||||
|
||||
u32 PR0 : 1;
|
||||
u32 PR1 : 1;
|
||||
u32 res2 : 2;
|
||||
|
||||
u32 res3 : 3;
|
||||
u32 : 5;
|
||||
u32 DDT : 1;
|
||||
|
||||
u32 res4 : 16;
|
||||
u32 : 16;
|
||||
};
|
||||
u32 full;
|
||||
};
|
||||
|
|
@ -1393,11 +1306,11 @@ union INTC_ICR_type
|
|||
u16 reg_data;
|
||||
struct
|
||||
{
|
||||
u32 res : 7;
|
||||
u32 : 7;
|
||||
u32 IRLM : 1;
|
||||
u32 NMIE : 1;
|
||||
u32 NMIB : 1;
|
||||
u32 res_2 : 4;
|
||||
u32 : 4;
|
||||
u32 MAI : 1;
|
||||
u32 NMIL : 1;
|
||||
};
|
||||
|
|
@ -1420,7 +1333,7 @@ union INTC_IPRB_type
|
|||
u16 reg_data;
|
||||
struct
|
||||
{
|
||||
u32 Reserved : 4;
|
||||
u32 : 4;
|
||||
u32 SCI1 : 4;
|
||||
u32 REF : 4;
|
||||
u32 WDT : 4;
|
||||
|
|
|
|||
Loading…
Reference in New Issue