diff --git a/core/hw/sh4/dyna/regalloc.h b/core/hw/sh4/dyna/regalloc.h index 774d3d4a6..4b3fd7b04 100644 --- a/core/hw/sh4/dyna/regalloc.h +++ b/core/hw/sh4/dyna/regalloc.h @@ -228,10 +228,10 @@ struct RegAlloc bool IsAllocg(Sh4RegType reg) { - for (u32 sid=0;sidregstart==(u32)reg && all_spans[sid]->contains(current_opid)) - return !all_spans[sid]->fpr; + if (span->regstart == (u32)reg && span->contains(current_opid)) + return !span->fpr; } return false; @@ -252,10 +252,10 @@ struct RegAlloc bool IsAllocf(Sh4RegType reg) { - for (u32 sid=0;sidregstart==(u32)reg && all_spans[sid]->contains(current_opid)) - return all_spans[sid]->fpr; + if (span->regstart == (u32)reg && span->contains(current_opid)) + return span->fpr; } return false; @@ -405,11 +405,11 @@ struct RegAlloc RegSpan* FindSpan(Sh4RegType reg, u32 opid) { - for (u32 sid=0;sidregstart==(u32)reg && all_spans[sid]->contains(opid)) + if (span->regstart == (u32)reg && span->contains(opid)) { - return all_spans[sid]; + return span; } } die("Failed to find span"); @@ -432,13 +432,6 @@ struct RegAlloc { op=&block->oplist[opid]; - /* - if (op->op!=shop_readm && op->op!=shop_writem && ( op->rd.is_vector() ||op->rs1.is_vector())) - { - // __asm int 3; - }*/ - - //if (op->op != shop_readm && op->op != shop_writem && op->op != shop_jcond && op->op != shop_jdyn && op->op != shop_mov32 && op->op != shop_mov64 && (op->op != shop_add || block->addr<=0x8c0DA0BA)) if (IsFlushOp(block,opid)) { bool fp=false,gpr_b=false,all=false; @@ -564,29 +557,29 @@ struct RegAlloc { reg_rd.erase(*iter); { - if ((*iter).is_reg()) + if (iter->is_reg()) { //r~w - if ((*iter).is_r32()) + if (iter->is_r32()) { - if (spans[(*iter)._reg]==0) + if (spans[iter->_reg]==0) { - spans[(*iter)._reg] = new RegSpan((*iter),opid,AM_READWRITE); - all_spans.push_back(spans[(*iter)._reg]); + spans[iter->_reg] = new RegSpan(*iter, opid, AM_READWRITE); + all_spans.push_back(spans[iter->_reg]); } else { - spans[(*iter)._reg]->Access(opid,AM_READWRITE); + spans[iter->_reg]->Access(opid, AM_READWRITE); } } else { - for (u32 i=0; i<(*iter).count(); i++) + for (u32 i = 0; i < iter->count(); i++) { - if (spans[(*iter)._reg+i]!=0) - spans[(*iter)._reg+i]->Flush(); + if (spans[iter->_reg + i] != 0) + spans[iter->_reg + i]->Flush(); - spans[(*iter)._reg+i]=0; + spans[iter->_reg + i]=0; } } } @@ -594,65 +587,65 @@ struct RegAlloc } else { - if ((*iter).is_reg()) + if (iter->is_reg()) { - for (u32 i=0; i<(*iter).count(); i++) + for (u32 i = 0; i < iter->count(); i++) { - if (spans[(*iter)._reg+i]!=0) + if (spans[iter->_reg + i] != 0) { //hack// //this is a bug on the current reg alloc code, affects fipr. //generally, vector registers aren't treated correctly //as groups of phy registers. I really need a better model //to accommodate for that on the reg alloc side of things .. - if ((*iter).count()==1 && iter->_reg==op->rs1._reg+3) - spans[(*iter)._reg+i]->Flush(); + if (iter->count() == 1 && iter->_reg == op->rs1._reg + 3) + spans[iter->_reg + i]->Flush(); else - spans[(*iter)._reg+i]->Kill(); + spans[iter->_reg + i]->Kill(); } - spans[(*iter)._reg+i]=0; + spans[iter->_reg + i] = 0; } //w - if ((*iter).is_r32()) + if (iter->is_r32()) { - if (spans[(*iter)._reg]!=0) - spans[(*iter)._reg]->Kill(); + if (spans[iter->_reg] != 0) + spans[iter->_reg]->Kill(); - spans[(*iter)._reg]= new RegSpan((*iter),opid,AM_WRITE); - all_spans.push_back(spans[(*iter)._reg]); + spans[iter->_reg] = new RegSpan(*iter, opid, AM_WRITE); + all_spans.push_back(spans[iter->_reg]); } } } ++iter; } - iter=reg_rd.begin(); - while( iter != reg_rd.end() ) + iter = reg_rd.begin(); + while (iter != reg_rd.end()) { //r - if ((*iter).is_reg()) + if (iter->is_reg()) { - if ((*iter).is_r32()) + if (iter->is_r32()) { - if (spans[(*iter)._reg]==0) + if (spans[iter->_reg] == 0) { - spans[(*iter)._reg] = new RegSpan((*iter),opid,AM_READ); - all_spans.push_back(spans[(*iter)._reg]); + spans[iter->_reg] = new RegSpan((*iter), opid, AM_READ); + all_spans.push_back(spans[iter->_reg]); } else { - spans[(*iter)._reg]->Access(opid,AM_READ); + spans[iter->_reg]->Access(opid, AM_READ); } } else { - for (u32 i=0; i<(*iter).count(); i++) + for (u32 i = 0; i < iter->count(); i++) { - if (spans[(*iter)._reg+i]!=0) - spans[(*iter)._reg+i]->Flush(); + if (spans[iter->_reg + i] != 0) + spans[iter->_reg + i]->Flush(); - spans[(*iter)._reg+i]=0; + spans[iter->_reg + i] = 0; } } } @@ -698,11 +691,11 @@ struct RegAlloc u32 cc_g=0; u32 cc_f=0; - for (u32 sid=0;sidcontains(opid)) + if (span->contains(opid)) { - if (all_spans[sid]->fpr) + if (span->fpr) cc_f++; else cc_g++; @@ -768,22 +761,20 @@ struct RegAlloc if (!alias_mov) { - for (u32 sid=0;sidbegining(opid)) + if (span->begining(opid)) { - if (spn->fpr) + if (span->fpr) { verify(regsf.size()>0); - spn->nregf=regsf.back(); + span->nregf=regsf.back(); regsf.pop_back(); } else { verify(regs.size()>0); - spn->nreg=regs.back(); + span->nreg=regs.back(); regs.pop_back(); //printf("rALOC %d from %d\n",spn->regstart,spn->nreg); @@ -791,21 +782,19 @@ struct RegAlloc } } } - for (u32 sid=0;sidending(opid) && !spn->aliased) + if (span->ending(opid) && !span->aliased) { - if (spn->fpr) + if (span->fpr) { verify(regsf.size()nregf); + regsf.push_front(span->nregf); } else { verify(regs.size()nreg); + regs.push_front(span->nreg); //printf("rFREE %d from %d\n",spn->regstart,spn->nreg); } } @@ -970,41 +959,39 @@ struct RegAlloc RegSpan* last_pacc=0; RegSpan* last_nacc=0; - for (u32 sid=0;sidcontains(opid) && fpr==spn->fpr) + if (span->contains(opid) && fpr==span->fpr) { - if (!spn->cacc(opid)) + if (!span->cacc(opid)) { - if (!last_nacc || spn->nacc(opid)>last_nacc->nacc(opid)) - last_nacc=spn; + if (!last_nacc || span->nacc(opid)>last_nacc->nacc(opid)) + last_nacc=span; - if (!last_pacc || spn->pacc(opid)pacc(opid)) - last_pacc=spn; + if (!last_pacc || span->pacc(opid)pacc(opid)) + last_pacc=span; } if (was_large) - printf("\t[%c]span: %d (r%d), [%d:%d],n: %d, p: %d\n",spn->cacc(opid)?'x':' ',sid,all_spans[sid]->regstart,all_spans[sid]->start,all_spans[sid]->end,all_spans[sid]->nacc(opid),all_spans[sid]->pacc(opid)); + printf("\t[%c]span: r%d, [%d:%d],n: %d, p: %d\n",span->cacc(opid)?'x':' ',span->regstart,span->start,span->end,span->nacc(opid),span->pacc(opid)); } } //printf("Last pacc: %d, vlen %d | reg r%d\n",last_pacc->nacc(opid)-opid,last_pacc->nacc(opid)-last_pacc->pacc(opid),last_pacc->regstart); //printf("Last nacc: %d, vlen %d | reg r%d\n",last_nacc->nacc(opid)-opid,last_nacc->nacc(opid)-last_nacc->pacc(opid),last_nacc->regstart); - RegSpan* spn= new RegSpan(*last_nacc); - spn->start=last_nacc->nacc(opid); + RegSpan* span= new RegSpan(*last_nacc); + span->start=last_nacc->nacc(opid); last_nacc->end=last_nacc->pacc(opid); //trim the access arrays as required .. - spn->trim_access(); + span->trim_access(); last_nacc->trim_access(); - spn->preload=spn->NeedsPL(); + span->preload=span->NeedsPL(); last_nacc->writeback=last_nacc->NeedsWB(); //add it to the span list ! - all_spans.push_back(spn); + all_spans.push_back(span); spills++; cc--; } @@ -1014,9 +1001,9 @@ struct RegAlloc { verify(reg!=-1); int cc=0; - for (u32 sid=0;sidregstart==reg && all_spans[sid]->contains(opid)) + if (span->regstart == reg && span->contains(opid)) cc++; } return cc; @@ -1026,9 +1013,9 @@ struct RegAlloc { verify(nreg!=-1); int cc=0; - for (u32 sid=0;sidnreg==nreg && all_spans[sid]->contains(opid)) + if (span->nreg == nreg && span->contains(opid)) cc++; } return cc; @@ -1038,9 +1025,9 @@ struct RegAlloc { verify(nregf!=-1); int cc=0; - for (u32 sid=0;sidnregf==nregf && all_spans[sid]->contains(opid)) + if (span->nregf == nregf && span->contains(opid)) cc++; } return cc; @@ -1050,11 +1037,9 @@ struct RegAlloc { int rv=0; - for (u32 sid=0;sidpreload && spn->begining(opid)) + if (span->preload && span->begining(opid)) rv++; } @@ -1065,11 +1050,9 @@ struct RegAlloc { int rv=0; - for (u32 sid=0;sidwriteback && spn->ending(opid)) + if (span->writeback && span->ending(opid)) rv++; } @@ -1080,23 +1063,21 @@ struct RegAlloc { current_opid=opid; - for (u32 sid=0;sidbegining(current_opid) && spn->preload) + if (span->begining(current_opid) && span->preload) { - if (spn->fpr) + if (span->fpr) { //printf("Op %d: Preloading f%d to %d\n",current_opid,spn->regstart,spn->nregf); preload_fpu++; - Preload_FPU(spn->regstart,spn->nregf); + Preload_FPU(span->regstart,span->nregf); } else { //printf("Op %d: Preloading r%d to %d\n",current_opid,spn->regstart,spn->nreg); preload_gpr++; - Preload(spn->regstart,spn->nreg); + Preload(span->regstart,span->nreg); } } } @@ -1104,23 +1085,21 @@ struct RegAlloc void OpEnd(shil_opcode* op) { - for (u32 sid=0;sidending(current_opid) && spn->writeback) + if (span->ending(current_opid) && span->writeback) { - if (spn->fpr) + if (span->fpr) { //printf("Op %d: Writing back f%d from %d\n",current_opid,spn->regstart,spn->nregf); writeback_fpu++; - Writeback_FPU(spn->regstart,spn->nregf); + Writeback_FPU(span->regstart,span->nregf); } else { //printf("Op %d: Writing back r%d from %d\n",current_opid,spn->regstart,spn->nreg); writeback_gpr++; - Writeback(spn->regstart,spn->nreg); + Writeback(span->regstart,span->nreg); } } } @@ -1128,23 +1107,17 @@ struct RegAlloc void BailOut(u32 opid) { - for (u32 sid = 0; sid < all_spans.size(); sid++) + for (RegSpan *span : all_spans) { - RegSpan* spn = all_spans[sid]; - - if (spn->end >= opid && spn->start < opid && spn->writeback) + if (span->end >= opid && span->start < opid && span->writeback) { - if (spn->fpr) + if (span->fpr) { - //printf("Op %d: Writing back f%d from %d\n",current_opid,spn->regstart,spn->nregf); - writeback_fpu++; - Writeback_FPU(spn->regstart,spn->nregf); + Writeback_FPU(span->regstart, span->nregf); } else { - //printf("Op %d: Writing back r%d from %d\n",current_opid,spn->regstart,spn->nreg); - writeback_gpr++; - Writeback(spn->regstart,spn->nreg); + Writeback(span->regstart, span->nreg); } } } @@ -1161,8 +1134,8 @@ struct RegAlloc spans[sid]=0; } - for (size_t sid=0;sid