From c5cc2f1e50c96c9baed1f2b3e90d71e35f988449 Mon Sep 17 00:00:00 2001
From: Stefanos Kornilios Mitsis Poiitidis <skmp@nillware.com>
Date: Tue, 6 Jan 2015 14:10:48 +0200
Subject: [PATCH] Document sh4_shced, fix tmu a bit

---
 core/hw/sh4/interpr/sh4_interpreter.cpp |  5 +-
 core/hw/sh4/modules/tmu.cpp             | 74 ++++++++++++-------------
 core/hw/sh4/sh4_sched.cpp               |  8 +++
 core/hw/sh4/sh4_sched.h                 | 33 +++++++++++
 4 files changed, 81 insertions(+), 39 deletions(-)

diff --git a/core/hw/sh4/interpr/sh4_interpreter.cpp b/core/hw/sh4/interpr/sh4_interpreter.cpp
index 16ee6f82b..f5640af6c 100644
--- a/core/hw/sh4/interpr/sh4_interpreter.cpp
+++ b/core/hw/sh4/interpr/sh4_interpreter.cpp
@@ -170,6 +170,8 @@ int AicaUpdate(int tag, int c, int j)
 
 	return AICA_TICK;
 }
+
+
 int DreamcastSecond(int tag, int c, int j)
 {
 	settings.dreamcast.RTC++;
@@ -183,7 +185,8 @@ int DreamcastSecond(int tag, int c, int j)
 #endif
 
 	//printf("%d ticks\n",sh4_sched_intr);
-	sh4_sched_intr=0;	return SH4_MAIN_CLOCK;
+	sh4_sched_intr=0;
+	return SH4_MAIN_CLOCK;
 }
 
 int UpdateSystem_rec()
diff --git a/core/hw/sh4/modules/tmu.cpp b/core/hw/sh4/modules/tmu.cpp
index f207babd0..28d500330 100644
--- a/core/hw/sh4/modules/tmu.cpp
+++ b/core/hw/sh4/modules/tmu.cpp
@@ -100,29 +100,28 @@ void write_TMU_TCNT(u32 addr, u32 data)
 	write_TMU_TCNTch(ch,data);
 }
 
+void sched_chan_tick(int ch)
+{
+	//schedule next interrupt
+	//return TMU_TCOR(ch) << tmu_shift[ch];
+
+	u32 tcor = TMU_TCOR(ch);
+	u32 cycles = tcor << tmu_shift[ch];
+
+	if (tmu_mask[ch])
+		sh4_sched_request(tmu_sched[ch], cycles);
+	else
+		sh4_sched_request(tmu_sched[ch], -1);
+	//sched_tmu_cb
+}
+
 void turn_on_off_ch(u32 ch, bool on)
 {
 	u32 TCNT=read_TMU_TCNTch(ch);
 	tmu_mask[ch]=on?0xFFFFFFFF:0x00000000;
 	write_TMU_TCNTch(ch,TCNT);
-}
 
-void sched_chan_tick(int ch)
-{
-	//max ticks
-	u32 tcnt = read_TMU_TCNTch(ch);
-
-	u64 togo=tcnt;
-
-	togo<<=tmu_shift[ch];
-
-	if (togo>SH4_MAIN_CLOCK)
-		togo=SH4_MAIN_CLOCK;
-
-	if (togo>-sh4_sched_now())
-		togo=-sh4_sched_now();
-
-	sh4_sched_request(tmu_sched[ch],togo);
+	sched_chan_tick(ch);
 }
 
 //Update internal counter registers
@@ -173,6 +172,7 @@ void UpdateTMUCounts(u32 reg)
 	}
 	tmu_shift[reg]+=2;
 	write_TMU_TCNTch(reg,TCNT);
+	sched_chan_tick(reg);
 }
 
 //Write to status registers
@@ -204,25 +204,24 @@ void write_TMU_TSTR(u32 addr, u32 data)
 		turn_on_off_ch(i,data&(1<<i));
 }
 
-int sched_tmu_cb(int tag, int sch_cycl, int jitter)
+int sched_tmu_cb(int ch, int sch_cycl, int jitter)
 {
-	/*
-	static int _target_intvr=200*1000*100;
-	static int sh4_last=-1, long_term;
-	if (sh4_last!=-1)
-	{
-		int eeel=sh4_sched_now()-sh4_last;
-		long_term+=eeel-_target_intvr;
+	if (tmu_mask[ch]) {
+		
+		//printf("Interrupt for %d, %d cycles\n", ch, sch_cycl);
 
-		//printf("Dreamcast second... %d | lteerr %d\n",eeel,long_term);
+		//raise interrupt, timer counted down
+		InterruptPend(tmu_intID[ch], 1);
+
+		u32 tcnt = read_TMU_TCNTch(ch);
+		u32 tcor = TMU_TCOR(ch);
+		u32 cycles = tcor << tmu_shift[ch];
+		//schedule next interrupt
+		return cycles;
+	}
+	else {
+		return jitter - 1;
 	}
-	sh4_last=sh4_sched_now();
-
-	return _target_intvr;
-
-	*/
-
-	return jitter-1;
 }
 
 //Init/Res/Term
@@ -264,11 +263,10 @@ void tmu_init()
 	//TMU TCPR2 0xFFD8002C 0x1FD8002C 32 Held Held Held Held Pclk
 	sh4_rio_reg(TMU,TMU_TCPR2_addr,RIO_FUNC,32,&TMU_TCPR2_read,&TMU_TCPR2_write);
 
-	for (int i=0;i<1;i++)
-		tmu_sched[i]=sh4_sched_register(i,&sched_tmu_cb);
-
-	sh4_sched_request(tmu_sched[0],-1);
-	
+	for (int i = 0; i < 3; i++) {
+		tmu_sched[i] = sh4_sched_register(i, &sched_tmu_cb);
+		sh4_sched_request(tmu_sched[i], -1);
+	}
 }
 
 
diff --git a/core/hw/sh4/sh4_sched.cpp b/core/hw/sh4/sh4_sched.cpp
index 1fa6e0c82..516bee912 100755
--- a/core/hw/sh4/sh4_sched.cpp
+++ b/core/hw/sh4/sh4_sched.cpp
@@ -86,17 +86,25 @@ int sh4_sched_register(int tag, sh4_sched_callback* ssc)
 	return list.size()-1;
 }
 
+/*
+	Return current cycle count, in 32 bits (wraps after 21 dreamcast seconds)
+*/
 u32 sh4_sched_now()
 {
 	return sh4_sched_ffb-Sh4cntx.sh4_sched_next;
 }
 
+/*
+	Return current cycle count, in 64 bits (effectivelly never wraps)
+*/
 u64 sh4_sched_now64()
 {
 	return sh4_sched_ffb-Sh4cntx.sh4_sched_next;
 }
 void sh4_sched_request(int id, int cycles)
 {
+	verify(cycles <= SH4_MAIN_CLOCK);
+
 	list[id].start=sh4_sched_now();
 	list[id].end=list[id].start+cycles;
 
diff --git a/core/hw/sh4/sh4_sched.h b/core/hw/sh4/sh4_sched.h
index 570faf690..59ee66d3c 100644
--- a/core/hw/sh4/sh4_sched.h
+++ b/core/hw/sh4/sh4_sched.h
@@ -1,14 +1,47 @@
 #include "types.h"
 
+/*
+	tag, as passed on sh4_sched_register
+	sch_cycles, the cycle duration that the callback requested (sh4_sched_request)
+	jitter, the number of cycles that the callback was delayed, [0... 448]
+*/
 typedef int sh4_sched_callback(int tag, int sch_cycl, int jitter);
 
+/*
+	Registed a callback to the scheduler. The returned id 
+	is used for sh4_sched_request and sh4_sched_elapsed calls
+*/
 int sh4_sched_register(int tag, sh4_sched_callback* ssc);
+
+/*
+	current time in SH4 cycles, referenced to boot.
+	Wraps every ~21 secs
+*/
 u32 sh4_sched_now();
+
+/*
+	current time, in SH4 cycles, referenced to boot.
+	Does not wrap, 64 bits.
+*/
 u64 sh4_sched_now64();
 
+/*
+	Schedule a callback to be called sh4 *cycles* after the
+	invocation of this function. *Cycles* range is (0, 200M].
+	
+	Passing a value of 0 disables the callback.
+	If called multiple times, only the last call is in effect
+*/
 void sh4_sched_request(int id, int cycles);
+
+/*
+	Returns how much time has passed for this callback
+*/
 int sh4_sched_elapsed(int id);
 
+/*
+	Tick for *cycles*
+*/
 void sh4_sched_tick(int cycles);
 
 extern u32 sh4_sched_intr;
\ No newline at end of file