Update XBYAK to 71b75f653f3858403eb33d48f6346eef34b837fe
This commit is contained in:
Stefanos Kornilios Mitsis Poiitidis
parent
e6afd22f98
commit
c52165adbd
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@ -1,47 +1,47 @@
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Copyright (c) 2007 MITSUNARI Shigeo
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
Neither the name of the copyright owner nor the names of its contributors may
|
||||
be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
THE POSSIBILITY OF SUCH DAMAGE.
|
||||
-----------------------------------------------------------------------------
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||||
ソースコード形式かバイナリ形式か、変更するかしないかを問わず、以下の条件を満た
|
||||
す場合に限り、再頒布および使用が許可されます。
|
||||
|
||||
ソースコードを再頒布する場合、上記の著作権表示、本条件一覧、および下記免責条項
|
||||
を含めること。
|
||||
バイナリ形式で再頒布する場合、頒布物に付属のドキュメント等の資料に、上記の著作
|
||||
権表示、本条件一覧、および下記免責条項を含めること。
|
||||
書面による特別の許可なしに、本ソフトウェアから派生した製品の宣伝または販売促進
|
||||
に、著作権者の名前またはコントリビューターの名前を使用してはならない。
|
||||
本ソフトウェアは、著作権者およびコントリビューターによって「現状のまま」提供さ
|
||||
れており、明示黙示を問わず、商業的な使用可能性、および特定の目的に対する適合性
|
||||
に関する暗黙の保証も含め、またそれに限定されない、いかなる保証もありません。
|
||||
著作権者もコントリビューターも、事由のいかんを問わず、 損害発生の原因いかんを
|
||||
問わず、かつ責任の根拠が契約であるか厳格責任であるか（過失その他の）不法行為で
|
||||
あるかを問わず、仮にそのような損害が発生する可能性を知らされていたとしても、
|
||||
本ソフトウェアの使用によって発生した（代替品または代用サービスの調達、使用の
|
||||
喪失、データの喪失、利益の喪失、業務の中断も含め、またそれに限定されない）直接
|
||||
損害、間接損害、偶発的な損害、特別損害、懲罰的損害、または結果損害について、
|
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一切責任を負わないものとします。
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||||
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Copyright (c) 2007 MITSUNARI Shigeo
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All rights reserved.
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|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
Neither the name of the copyright owner nor the names of its contributors may
|
||||
be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
THE POSSIBILITY OF SUCH DAMAGE.
|
||||
-----------------------------------------------------------------------------
|
||||
ソースコード形式かバイナリ形式か、変更するかしないかを問わず、以下の条件を満た
|
||||
す場合に限り、再頒布および使用が許可されます。
|
||||
|
||||
ソースコードを再頒布する場合、上記の著作権表示、本条件一覧、および下記免責条項
|
||||
を含めること。
|
||||
バイナリ形式で再頒布する場合、頒布物に付属のドキュメント等の資料に、上記の著作
|
||||
権表示、本条件一覧、および下記免責条項を含めること。
|
||||
書面による特別の許可なしに、本ソフトウェアから派生した製品の宣伝または販売促進
|
||||
に、著作権者の名前またはコントリビューターの名前を使用してはならない。
|
||||
本ソフトウェアは、著作権者およびコントリビューターによって「現状のまま」提供さ
|
||||
れており、明示黙示を問わず、商業的な使用可能性、および特定の目的に対する適合性
|
||||
に関する暗黙の保証も含め、またそれに限定されない、いかなる保証もありません。
|
||||
著作権者もコントリビューターも、事由のいかんを問わず、 損害発生の原因いかんを
|
||||
問わず、かつ責任の根拠が契約であるか厳格責任であるか（過失その他の）不法行為で
|
||||
あるかを問わず、仮にそのような損害が発生する可能性を知らされていたとしても、
|
||||
本ソフトウェアの使用によって発生した（代替品または代用サービスの調達、使用の
|
||||
喪失、データの喪失、利益の喪失、業務の中断も含め、またそれに限定されない）直接
|
||||
損害、間接損害、偶発的な損害、特別損害、懲罰的損害、または結果損害について、
|
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一切責任を負わないものとします。
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||||
|
|
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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@ -48,10 +48,6 @@
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#endif
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#endif
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#ifdef _MSC_VER
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extern "C" unsigned __int64 __xgetbv(int);
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#endif
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namespace Xbyak { namespace util {
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/**
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@ -88,6 +84,67 @@ class Cpu {
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displayModel = model;
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}
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}
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unsigned int extractBit(unsigned int val, unsigned int base, unsigned int end)
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{
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return (val >> base) & ((1u << (end - base)) - 1);
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}
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void setCacheHierarchy()
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{
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if ((type_ & tINTEL) == 0) return;
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const unsigned int NO_CACHE = 0;
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const unsigned int DATA_CACHE = 1;
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// const unsigned int INSTRUCTION_CACHE = 2;
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const unsigned int UNIFIED_CACHE = 3;
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unsigned int smt_width = 0;
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unsigned int n_cores = 0;
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unsigned int data[4];
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/*
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if leaf 11 exists, we use it to get the number of smt cores and cores on socket
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If x2APIC is supported, these are the only correct numbers.
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leaf 0xB can be zeroed-out by a hypervisor
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*/
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getCpuidEx(0x0, 0, data);
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if (data[0] >= 0xB) {
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getCpuidEx(0xB, 0, data); // CPUID for SMT Level
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smt_width = data[1] & 0x7FFF;
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getCpuidEx(0xB, 1, data); // CPUID for CORE Level
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n_cores = data[1] & 0x7FFF;
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}
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/*
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Assumptions:
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the first level of data cache is not shared (which is the
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case for every existing architecture) and use this to
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determine the SMT width for arch not supporting leaf 11.
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when leaf 4 reports a number of core less than n_cores
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on socket reported by leaf 11, then it is a correct number
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of cores not an upperbound.
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*/
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for (int i = 0; data_cache_levels < maxNumberCacheLevels; i++) {
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getCpuidEx(0x4, i, data);
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unsigned int cacheType = extractBit(data[0], 0, 4);
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if (cacheType == NO_CACHE) break;
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if (cacheType == DATA_CACHE || cacheType == UNIFIED_CACHE) {
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unsigned int nb_logical_cores = extractBit(data[0], 14, 25) + 1;
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if (n_cores != 0) { // true only if leaf 0xB is supported and valid
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nb_logical_cores = (std::min)(nb_logical_cores, n_cores);
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}
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assert(nb_logical_cores != 0);
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data_cache_size[data_cache_levels] =
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(extractBit(data[1], 22, 31) + 1)
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* (extractBit(data[1], 12, 21) + 1)
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* (extractBit(data[1], 0, 11) + 1)
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* (data[2] + 1);
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if (cacheType == DATA_CACHE && smt_width == 0) smt_width = nb_logical_cores;
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assert(smt_width != 0);
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cores_sharing_data_cache[data_cache_levels] = nb_logical_cores / smt_width;
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data_cache_levels++;
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}
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}
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}
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public:
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int model;
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int family;
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@ -96,6 +153,28 @@ public:
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int extFamily;
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int displayFamily; // family + extFamily
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int displayModel; // model + extModel
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// may I move these members into private?
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static const unsigned int maxNumberCacheLevels = 10;
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unsigned int data_cache_size[maxNumberCacheLevels];
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unsigned int cores_sharing_data_cache[maxNumberCacheLevels];
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unsigned int data_cache_levels;
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unsigned int getDataCacheLevels() const { return data_cache_levels; }
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unsigned int getCoresSharingDataCache(unsigned int i) const
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{
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if (i >= data_cache_levels) throw Error(ERR_BAD_PARAMETER);
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return cores_sharing_data_cache[i];
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}
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unsigned int getDataCacheSize(unsigned int i) const
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{
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if (i >= data_cache_levels) throw Error(ERR_BAD_PARAMETER);
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return data_cache_size[i];
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}
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/*
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data[] = { eax, ebx, ecx, edx }
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*/
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static inline void getCpuid(unsigned int eaxIn, unsigned int data[4])
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{
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#ifdef _MSC_VER
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@ -115,7 +194,7 @@ public:
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static inline uint64 getXfeature()
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{
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#ifdef _MSC_VER
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return __xgetbv(0);
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return _xgetbv(0);
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#else
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unsigned int eax, edx;
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// xgetvb is not support on gcc 4.2
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@ -125,6 +204,7 @@ public:
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#endif
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}
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typedef uint64 Type;
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static const Type NONE = 0;
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static const Type tMMX = 1 << 0;
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static const Type tMMX2 = 1 << 1;
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@ -164,71 +244,128 @@ public:
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static const Type tRTM = uint64(1) << 32; // xbegin, xend, xabort
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static const Type tF16C = uint64(1) << 33; // vcvtph2ps, vcvtps2ph
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static const Type tMOVBE = uint64(1) << 34; // mobve
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static const Type tAVX512F = uint64(1) << 35;
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static const Type tAVX512DQ = uint64(1) << 36;
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static const Type tAVX512_IFMA = uint64(1) << 37;
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static const Type tAVX512IFMA = tAVX512_IFMA;
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static const Type tAVX512PF = uint64(1) << 38;
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static const Type tAVX512ER = uint64(1) << 39;
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static const Type tAVX512CD = uint64(1) << 40;
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static const Type tAVX512BW = uint64(1) << 41;
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static const Type tAVX512VL = uint64(1) << 42;
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static const Type tAVX512_VBMI = uint64(1) << 43;
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static const Type tAVX512VBMI = tAVX512_VBMI; // changed by Intel's manual
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static const Type tAVX512_4VNNIW = uint64(1) << 44;
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static const Type tAVX512_4FMAPS = uint64(1) << 45;
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static const Type tPREFETCHWT1 = uint64(1) << 46;
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static const Type tPREFETCHW = uint64(1) << 47;
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static const Type tSHA = uint64(1) << 48;
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static const Type tMPX = uint64(1) << 49;
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static const Type tAVX512_VBMI2 = uint64(1) << 50;
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static const Type tGFNI = uint64(1) << 51;
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static const Type tVAES = uint64(1) << 52;
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static const Type tVPCLMULQDQ = uint64(1) << 53;
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static const Type tAVX512_VNNI = uint64(1) << 54;
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static const Type tAVX512_BITALG = uint64(1) << 55;
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static const Type tAVX512_VPOPCNTDQ = uint64(1) << 56;
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Cpu()
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: type_(NONE)
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, data_cache_levels(0)
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{
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unsigned int data[4];
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const unsigned int& EAX = data[0];
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const unsigned int& EBX = data[1];
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const unsigned int& ECX = data[2];
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const unsigned int& EDX = data[3];
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getCpuid(0, data);
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const unsigned int maxNum = data[0];
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const unsigned int maxNum = EAX;
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static const char intel[] = "ntel";
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static const char amd[] = "cAMD";
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if (data[2] == get32bitAsBE(amd)) {
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if (ECX == get32bitAsBE(amd)) {
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type_ |= tAMD;
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getCpuid(0x80000001, data);
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if (data[3] & (1U << 31)) type_ |= t3DN;
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if (data[3] & (1U << 15)) type_ |= tCMOV;
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if (data[3] & (1U << 30)) type_ |= tE3DN;
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if (data[3] & (1U << 22)) type_ |= tMMX2;
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if (data[3] & (1U << 27)) type_ |= tRDTSCP;
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if (EDX & (1U << 31)) type_ |= t3DN;
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if (EDX & (1U << 15)) type_ |= tCMOV;
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if (EDX & (1U << 30)) type_ |= tE3DN;
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if (EDX & (1U << 22)) type_ |= tMMX2;
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if (EDX & (1U << 27)) type_ |= tRDTSCP;
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}
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if (data[2] == get32bitAsBE(intel)) {
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if (ECX == get32bitAsBE(intel)) {
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type_ |= tINTEL;
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getCpuid(0x80000001, data);
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if (data[3] & (1U << 27)) type_ |= tRDTSCP;
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if (data[2] & (1U << 5)) type_ |= tLZCNT;
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if (EDX & (1U << 27)) type_ |= tRDTSCP;
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if (ECX & (1U << 5)) type_ |= tLZCNT;
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if (ECX & (1U << 8)) type_ |= tPREFETCHW;
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}
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getCpuid(1, data);
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if (data[2] & (1U << 0)) type_ |= tSSE3;
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if (data[2] & (1U << 9)) type_ |= tSSSE3;
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if (data[2] & (1U << 19)) type_ |= tSSE41;
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if (data[2] & (1U << 20)) type_ |= tSSE42;
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if (data[2] & (1U << 22)) type_ |= tMOVBE;
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if (data[2] & (1U << 23)) type_ |= tPOPCNT;
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if (data[2] & (1U << 25)) type_ |= tAESNI;
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if (data[2] & (1U << 1)) type_ |= tPCLMULQDQ;
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if (data[2] & (1U << 27)) type_ |= tOSXSAVE;
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if (data[2] & (1U << 30)) type_ |= tRDRAND;
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if (data[2] & (1U << 29)) type_ |= tF16C;
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if (ECX & (1U << 0)) type_ |= tSSE3;
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if (ECX & (1U << 9)) type_ |= tSSSE3;
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if (ECX & (1U << 19)) type_ |= tSSE41;
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if (ECX & (1U << 20)) type_ |= tSSE42;
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if (ECX & (1U << 22)) type_ |= tMOVBE;
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if (ECX & (1U << 23)) type_ |= tPOPCNT;
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if (ECX & (1U << 25)) type_ |= tAESNI;
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if (ECX & (1U << 1)) type_ |= tPCLMULQDQ;
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if (ECX & (1U << 27)) type_ |= tOSXSAVE;
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if (ECX & (1U << 30)) type_ |= tRDRAND;
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if (ECX & (1U << 29)) type_ |= tF16C;
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if (data[3] & (1U << 15)) type_ |= tCMOV;
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if (data[3] & (1U << 23)) type_ |= tMMX;
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if (data[3] & (1U << 25)) type_ |= tMMX2 | tSSE;
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if (data[3] & (1U << 26)) type_ |= tSSE2;
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if (EDX & (1U << 15)) type_ |= tCMOV;
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if (EDX & (1U << 23)) type_ |= tMMX;
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if (EDX & (1U << 25)) type_ |= tMMX2 | tSSE;
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if (EDX & (1U << 26)) type_ |= tSSE2;
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if (type_ & tOSXSAVE) {
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// check XFEATURE_ENABLED_MASK[2:1] = '11b'
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uint64 bv = getXfeature();
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if ((bv & 6) == 6) {
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if (data[2] & (1U << 28)) type_ |= tAVX;
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if (data[2] & (1U << 12)) type_ |= tFMA;
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if (ECX & (1U << 28)) type_ |= tAVX;
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if (ECX & (1U << 12)) type_ |= tFMA;
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if (((bv >> 5) & 7) == 7) {
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getCpuidEx(7, 0, data);
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if (EBX & (1U << 16)) type_ |= tAVX512F;
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if (type_ & tAVX512F) {
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if (EBX & (1U << 17)) type_ |= tAVX512DQ;
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if (EBX & (1U << 21)) type_ |= tAVX512_IFMA;
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if (EBX & (1U << 26)) type_ |= tAVX512PF;
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if (EBX & (1U << 27)) type_ |= tAVX512ER;
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if (EBX & (1U << 28)) type_ |= tAVX512CD;
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if (EBX & (1U << 30)) type_ |= tAVX512BW;
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if (EBX & (1U << 31)) type_ |= tAVX512VL;
|
||||
if (ECX & (1U << 1)) type_ |= tAVX512_VBMI;
|
||||
if (ECX & (1U << 6)) type_ |= tAVX512_VBMI2;
|
||||
if (ECX & (1U << 8)) type_ |= tGFNI;
|
||||
if (ECX & (1U << 9)) type_ |= tVAES;
|
||||
if (ECX & (1U << 10)) type_ |= tVPCLMULQDQ;
|
||||
if (ECX & (1U << 11)) type_ |= tAVX512_VNNI;
|
||||
if (ECX & (1U << 12)) type_ |= tAVX512_BITALG;
|
||||
if (ECX & (1U << 14)) type_ |= tAVX512_VPOPCNTDQ;
|
||||
if (EDX & (1U << 2)) type_ |= tAVX512_4VNNIW;
|
||||
if (EDX & (1U << 3)) type_ |= tAVX512_4FMAPS;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
if (maxNum >= 7) {
|
||||
getCpuidEx(7, 0, data);
|
||||
if (type_ & tAVX && data[1] & 0x20) type_ |= tAVX2;
|
||||
if (data[1] & (1U << 3)) type_ |= tBMI1;
|
||||
if (data[1] & (1U << 8)) type_ |= tBMI2;
|
||||
if (data[1] & (1U << 9)) type_ |= tENHANCED_REP;
|
||||
if (data[1] & (1U << 18)) type_ |= tRDSEED;
|
||||
if (data[1] & (1U << 19)) type_ |= tADX;
|
||||
if (data[1] & (1U << 20)) type_ |= tSMAP;
|
||||
if (data[1] & (1U << 4)) type_ |= tHLE;
|
||||
if (data[1] & (1U << 11)) type_ |= tRTM;
|
||||
if (type_ & tAVX && (EBX & (1U << 5))) type_ |= tAVX2;
|
||||
if (EBX & (1U << 3)) type_ |= tBMI1;
|
||||
if (EBX & (1U << 8)) type_ |= tBMI2;
|
||||
if (EBX & (1U << 9)) type_ |= tENHANCED_REP;
|
||||
if (EBX & (1U << 18)) type_ |= tRDSEED;
|
||||
if (EBX & (1U << 19)) type_ |= tADX;
|
||||
if (EBX & (1U << 20)) type_ |= tSMAP;
|
||||
if (EBX & (1U << 4)) type_ |= tHLE;
|
||||
if (EBX & (1U << 11)) type_ |= tRTM;
|
||||
if (EBX & (1U << 14)) type_ |= tMPX;
|
||||
if (EBX & (1U << 29)) type_ |= tSHA;
|
||||
if (ECX & (1U << 0)) type_ |= tPREFETCHWT1;
|
||||
}
|
||||
setFamily();
|
||||
setCacheHierarchy();
|
||||
}
|
||||
void putFamily()
|
||||
void putFamily() const
|
||||
{
|
||||
printf("family=%d, model=%X, stepping=%d, extFamily=%d, extModel=%X\n",
|
||||
family, model, stepping, extFamily, extModel);
|
||||
|
|
@ -283,14 +420,19 @@ class Pack {
|
|||
const Xbyak::Reg64 *tbl_[maxTblNum];
|
||||
size_t n_;
|
||||
public:
|
||||
Pack() : n_(0) {}
|
||||
Pack() : tbl_(), n_(0) {}
|
||||
Pack(const Xbyak::Reg64 *tbl, size_t n) { init(tbl, n); }
|
||||
Pack(const Pack& rhs)
|
||||
: n_(rhs.n_)
|
||||
{
|
||||
if (n_ > maxTblNum) throw Error(ERR_INTERNAL);
|
||||
for (size_t i = 0; i < n_; i++) tbl_[i] = rhs.tbl_[i];
|
||||
}
|
||||
Pack& operator=(const Pack& rhs)
|
||||
{
|
||||
n_ = rhs.n_;
|
||||
for (size_t i = 0; i < n_; i++) tbl_[i] = rhs.tbl_[i];
|
||||
return *this;
|
||||
}
|
||||
Pack(const Xbyak::Reg64& t0)
|
||||
{ n_ = 1; tbl_[0] = &t0; }
|
||||
Pack(const Xbyak::Reg64& t1, const Xbyak::Reg64& t0)
|
||||
|
|
@ -313,7 +455,7 @@ public:
|
|||
{ n_ = 10; tbl_[0] = &t0; tbl_[1] = &t1; tbl_[2] = &t2; tbl_[3] = &t3; tbl_[4] = &t4; tbl_[5] = &t5; tbl_[6] = &t6; tbl_[7] = &t7; tbl_[8] = &t8; tbl_[9] = &t9; }
|
||||
Pack& append(const Xbyak::Reg64& t)
|
||||
{
|
||||
if (n_ == 10) {
|
||||
if (n_ == maxTblNum) {
|
||||
fprintf(stderr, "ERR Pack::can't append\n");
|
||||
throw Error(ERR_BAD_PARAMETER);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue