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Naomi rename vars and clean up. Logging changes.

This commit is contained in:
Flyinghead 2019-07-13 12:44:10 +02:00
parent 60ec054b59
commit bbc11a30aa
10 changed files with 127 additions and 218 deletions
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2
core/hw/flashrom/flashrom.h
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@ -283,7 +283,7 @@ struct DCFlashChip : MemChip
state = FS_ReadAMDID1; state = FS_ReadAMDID1;
break; break;
default: default:
EMUERROR("Unknown FlashWrite mode: %x\n", val); INFO_LOG(FLASHROM, "Unknown FlashWrite mode: %x\n", val);
break; break;
} }
break; break;

14
core/hw/mem/_vmem.cpp
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@ -299,31 +299,31 @@ void DYNACALL _vmem_WriteMem64(u32 Address,u64 data) { _vmem_writet<u64>(Address
//default read handlers //default read handlers
u8 DYNACALL _vmem_ReadMem8_not_mapped(u32 addresss) u8 DYNACALL _vmem_ReadMem8_not_mapped(u32 addresss)
{ {
DEBUG_LOG(MEMORY, "[sh4]Read8 from 0x%X, not mapped [_vmem default handler]", addresss); INFO_LOG(MEMORY, "[sh4]Read8 from 0x%X, not mapped [_vmem default handler]", addresss);
return (u8)MEM_ERROR_RETURN_VALUE; return (u8)MEM_ERROR_RETURN_VALUE;
} }
u16 DYNACALL _vmem_ReadMem16_not_mapped(u32 addresss) u16 DYNACALL _vmem_ReadMem16_not_mapped(u32 addresss)
{ {
DEBUG_LOG(MEMORY, "[sh4]Read16 from 0x%X, not mapped [_vmem default handler]", addresss); INFO_LOG(MEMORY, "[sh4]Read16 from 0x%X, not mapped [_vmem default handler]", addresss);
return (u16)MEM_ERROR_RETURN_VALUE; return (u16)MEM_ERROR_RETURN_VALUE;
} }
u32 DYNACALL _vmem_ReadMem32_not_mapped(u32 addresss) u32 DYNACALL _vmem_ReadMem32_not_mapped(u32 address)
{ {
DEBUG_LOG(MEMORY, "[sh4]Read32 from 0x%X, not mapped [_vmem default handler]", addresss); INFO_LOG(MEMORY, "[sh4]Read32 from 0x%X, not mapped [_vmem default handler]", address);
return (u32)MEM_ERROR_RETURN_VALUE; return (u32)MEM_ERROR_RETURN_VALUE;
} }
//default write handers //default write handers
void DYNACALL _vmem_WriteMem8_not_mapped(u32 addresss,u8 data) void DYNACALL _vmem_WriteMem8_not_mapped(u32 addresss,u8 data)
{ {
DEBUG_LOG(MEMORY, "[sh4]Write8 to 0x%X=0x%X, not mapped [_vmem default handler]", addresss, data); INFO_LOG(MEMORY, "[sh4]Write8 to 0x%X=0x%X, not mapped [_vmem default handler]", addresss, data);
} }
void DYNACALL _vmem_WriteMem16_not_mapped(u32 addresss,u16 data) void DYNACALL _vmem_WriteMem16_not_mapped(u32 addresss,u16 data)
{ {
DEBUG_LOG(MEMORY, "[sh4]Write16 to 0x%X=0x%X, not mapped [_vmem default handler]", addresss, data); INFO_LOG(MEMORY, "[sh4]Write16 to 0x%X=0x%X, not mapped [_vmem default handler]", addresss, data);
} }
void DYNACALL _vmem_WriteMem32_not_mapped(u32 addresss,u32 data) void DYNACALL _vmem_WriteMem32_not_mapped(u32 addresss,u32 data)
{ {
DEBUG_LOG(MEMORY, "[sh4]Write32 to 0x%X=0x%X, not mapped [_vmem default handler]", addresss, data); INFO_LOG(MEMORY, "[sh4]Write32 to 0x%X=0x%X, not mapped [_vmem default handler]", addresss, data);
} }
//code to register handlers //code to register handlers
//0 is considered error :) //0 is considered error :)

145
core/hw/naomi/naomi.cpp
View File

@ -8,6 +8,7 @@
#include "hw/holly/holly_intc.h" #include "hw/holly/holly_intc.h"
#include "hw/maple/maple_cfg.h" #include "hw/maple/maple_cfg.h"
#include "hw/sh4/sh4_sched.h" #include "hw/sh4/sh4_sched.h"
#include "hw/sh4/modules/dmac.h"
#include "naomi.h" #include "naomi.h"
#include "naomi_cart.h" #include "naomi_cart.h"
@ -340,23 +341,6 @@ u16 NaomiGameIDRead()
return (GSerialBuffer&(1<<(31-GBufPos)))?1:0; return (GSerialBuffer&(1<<(31-GBufPos)))?1:0;
} }
u32 _ReadMem_naomi(u32 Addr, u32 sz)
{
verify(sz!=1);
DEBUG_LOG(NAOMI, "naomi?WTF? ReadMem: %X, %d", Addr, sz);
return 1;
}
void _WriteMem_naomi(u32 Addr, u32 data, u32 sz)
{
DEBUG_LOG(NAOMI, "naomi?WTF? WriteMem: %X <= %X, %d", Addr, data, sz);
}
//DIMM board //DIMM board
//Uses interrupt ext#3 (holly_EXT_PCI) //Uses interrupt ext#3 (holly_EXT_PCI)
@ -382,23 +366,22 @@ void _WriteMem_naomi(u32 Addr, u32 data, u32 sz)
//n1 bios writes the value -1, meaning it expects the bit 0 to be set //n1 bios writes the value -1, meaning it expects the bit 0 to be set
//.// //.//
u32 reg_dimm_3c; //IO window ! written, 0x1E03 some flag ? u32 reg_dimm_command; // command, written, 0x1E03 some flag ?
u32 reg_dimm_40; //parameters u32 reg_dimm_offsetl;
u32 reg_dimm_44; //parameters u32 reg_dimm_parameterl;
u32 reg_dimm_48; //parameters u32 reg_dimm_parameterh;
u32 reg_dimm_status = 0x11;
u32 reg_dimm_4c=0x11; //status/control reg ?
bool NaomiDataRead = false; bool NaomiDataRead = false;
static bool aw_ram_test_skipped = false; static bool aw_ram_test_skipped = false;
void naomi_process(u32 r3c,u32 r40,u32 r44, u32 r48) void naomi_process(u32 command, u32 offsetl, u32 parameterl, u32 parameterh)
{ {
DEBUG_LOG(NAOMI, "Naomi process 0x%04X 0x%04X 0x%04X 0x%04X", r3c, r40, r44, r48); DEBUG_LOG(NAOMI, "Naomi process 0x%04X 0x%04X 0x%04X 0x%04X", command, offsetl, parameterl, parameterh);
DEBUG_LOG(NAOMI, "Possible format 0 %d 0x%02X 0x%04X",r3c >> 15,(r3c & 0x7e00) >> 9, r3c & 0x1FF); DEBUG_LOG(NAOMI, "Possible format 0 %d 0x%02X 0x%04X",command >> 15,(command & 0x7e00) >> 9, command & 0x1FF);
DEBUG_LOG(NAOMI, "Possible format 1 0x%02X 0x%02X", (r3c & 0xFF00) >> 8,r3c & 0xFF); DEBUG_LOG(NAOMI, "Possible format 1 0x%02X 0x%02X", (command & 0xFF00) >> 8,command & 0xFF);
u32 param=(r3c&0xFF); u32 param=(command&0xFF);
if (param==0xFF) if (param==0xFF)
{ {
DEBUG_LOG(NAOMI, "invalid opcode or smth ?"); DEBUG_LOG(NAOMI, "invalid opcode or smth ?");
@ -407,8 +390,8 @@ void naomi_process(u32 r3c,u32 r40,u32 r44, u32 r48)
//else if (param!=3) //else if (param!=3)
if (opcd<255) if (opcd<255)
{ {
reg_dimm_3c=0x8000 | (opcd%12<<9) | (0x0); reg_dimm_command=0x8000 | (opcd%12<<9) | (0x0);
DEBUG_LOG(NAOMI, "new reg is 0x%X", reg_dimm_3c); DEBUG_LOG(NAOMI, "new reg is 0x%X", reg_dimm_command);
asic_RaiseInterrupt(holly_EXP_PCI); asic_RaiseInterrupt(holly_EXP_PCI);
DEBUG_LOG(NAOMI, "Interrupt raised"); DEBUG_LOG(NAOMI, "Interrupt raised");
opcd++; opcd++;
@ -451,11 +434,12 @@ void Naomi_DmaStart(u32 addr, u32 data)
if (SB_GDST==1) if (SB_GDST==1)
{ {
verify(1 == SB_GDDIR ); verify(1 == SB_GDDIR );
DEBUG_LOG(NAOMI, "NAOMI-DMA start addr %08X len %d", SB_GDSTAR, SB_GDLEN);
SB_GDSTARD=SB_GDSTAR+SB_GDLEN;
SB_GDSTARD = SB_GDSTAR + SB_GDLEN;
SB_GDLEND=SB_GDLEN; SB_GDLEND = SB_GDLEN;
SB_GDST=0; SB_GDST = 0;
if (CurrentCartridge != NULL) if (CurrentCartridge != NULL)
{ {
u32 len = SB_GDLEN; u32 len = SB_GDLEN;
@ -464,8 +448,12 @@ void Naomi_DmaStart(u32 addr, u32 data)
{ {
u32 block_len = len; u32 block_len = len;
void* ptr = CurrentCartridge->GetDmaPtr(block_len); void* ptr = CurrentCartridge->GetDmaPtr(block_len);
if (ptr != NULL) if (block_len == 0)
WriteMemBlock_nommu_ptr(SB_GDSTAR + offset, (u32*)ptr, block_len); {
INFO_LOG(NAOMI, "Aborted DMA transfer. Read past end of cart?");
break;
}
WriteMemBlock_nommu_ptr(SB_GDSTAR + offset, (u32*)ptr, block_len);
CurrentCartridge->AdvancePtr(block_len); CurrentCartridge->AdvancePtr(block_len);
len -= block_len; len -= block_len;
offset += block_len; offset += block_len;
@ -573,82 +561,11 @@ void naomi_reg_Reset(bool Manual)
GLastCmd = 0; GLastCmd = 0;
SerStep = 0; SerStep = 0;
SerStep2 = 0; SerStep2 = 0;
} reg_dimm_command = 0;
reg_dimm_offsetl = 0;
void Update_naomi() reg_dimm_parameterl = 0;
{ reg_dimm_parameterh = 0;
/* reg_dimm_status = 0x11;
if (naomi_updates>1)
{
naomi_updates--;
}
else if (naomi_updates==1)
{
naomi_updates=0;
asic_RaiseInterrupt(holly_EXP_PCI);
}*/
#if 0
if(!(SB_GDST&1) || !(SB_GDEN &1))
return;
//SB_GDST=0;
//TODO : Fix dmaor
u32 dmaor = DMAC_DMAOR.full;
u32 src = SB_GDSTARD,
len = SB_GDLEN-SB_GDLEND ;
//len=min(len,(u32)32);
// do we need to do this for gdrom dma ?
if(0x8201 != (dmaor &DMAOR_MASK)) {
INFO_LOG(NAOMI, "GDROM: DMAOR has invalid settings (%X) !", dmaor);
//return;
}
if(len & 0x1F) {
INFO_LOG(NAOMI, "GDROM: SB_GDLEN has invalid size (%X) !", len);
return;
}
if(0 == len)
{
INFO_LOG(NAOMI, "GDROM: Len: %X, Abnormal Termination !", len);
}
u32 len_backup=len;
if( 1 == SB_GDDIR )
{
WriteMemBlock_nommu_ptr(dst,NaomiRom+(DmaOffset&0x7ffffff),size);
DmaCount=0xffff;
}
else
INFO_LOG(NAOMI, "GDROM: SB_GDDIR %X (TO AICA WAVE MEM?)");
//SB_GDLEN = 0x00000000; //13/5/2k7 -> acording to docs these regs are not updated by hardware
//SB_GDSTAR = (src + len_backup);
SB_GDLEND+= len_backup;
SB_GDSTARD+= len_backup;//(src + len_backup)&0x1FFFFFFF;
if (SB_GDLEND==SB_GDLEN)
{
//printf("Streamed GDMA end - %d bytes trasnfered\n",SB_GDLEND);
SB_GDST=0;//done
// The DMA end interrupt flag
asic_RaiseInterrupt(holly_GDROM_DMA);
}
//Readed ALL sectors
if (read_params.remaining_sectors==0)
{
u32 buff_size =read_buff.cache_size - read_buff.cache_index;
//And all buffer :p
if (buff_size==0)
{
verify(!SB_GDST&1)
gd_set_state(gds_procpacketdone);
}
}
#endif
} }
static u8 aw_maple_devs; static u8 aw_maple_devs;
@ -659,6 +576,10 @@ u32 libExtDevice_ReadMem_A0_006(u32 addr,u32 size) {
//printf("libExtDevice_ReadMem_A0_006 %d@%08x: %x\n", size, addr, mem600[addr]); //printf("libExtDevice_ReadMem_A0_006 %d@%08x: %x\n", size, addr, mem600[addr]);
switch (addr) switch (addr)
{ {
// case 0:
// return 0;
// case 4:
// return 1;
case 0x280: case 0x280:
// 0x00600280 r 0000dcba // 0x00600280 r 0000dcba
// a/b - 1P/2P coin inputs (JAMMA), active low // a/b - 1P/2P coin inputs (JAMMA), active low

22
core/hw/naomi/naomi.h
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@ -8,8 +8,6 @@ void naomi_reg_Init();
void naomi_reg_Term(); void naomi_reg_Term();
void naomi_reg_Reset(bool Manual); void naomi_reg_Reset(bool Manual);
void Update_naomi();
u32 ReadMem_naomi(u32 Addr, u32 sz); u32 ReadMem_naomi(u32 Addr, u32 sz);
void WriteMem_naomi(u32 Addr, u32 data, u32 sz); void WriteMem_naomi(u32 Addr, u32 data, u32 sz);
@ -20,21 +18,11 @@ u16 NaomiGameIDRead();
void NaomiGameIDWrite(const u16 Data); void NaomiGameIDWrite(const u16 Data);
void naomi_process(u32 r3c,u32 r40,u32 r44, u32 r48); void naomi_process(u32 r3c,u32 r40,u32 r44, u32 r48);
typedef u16 (*getNaomiAxisFP)(); extern u32 reg_dimm_command; // command, written, 0x1E03 some flag ?
extern u32 reg_dimm_offsetl;
struct NaomiInputMapping { extern u32 reg_dimm_parameterl;
getNaomiAxisFP axis[8]; extern u32 reg_dimm_parameterh;
u8 button_mapping_byte[16]; extern u32 reg_dimm_status;
u8 button_mapping_mask[16];
};
extern NaomiInputMapping Naomi_Mapping;
extern u32 reg_dimm_3c; //IO window ! written, 0x1E03 some flag ?
extern u32 reg_dimm_40; //parameters
extern u32 reg_dimm_44; //parameters
extern u32 reg_dimm_48; //parameters
extern u32 reg_dimm_4c; //status/control reg ?
extern bool NaomiDataRead; extern bool NaomiDataRead;
extern u32 naomi_updates; extern u32 naomi_updates;

74
core/hw/naomi/naomi_cart.cpp
View File

@ -730,23 +730,25 @@ void NaomiCartridge::AdvancePtr(u32 size) {
u32 NaomiCartridge::ReadMem(u32 address, u32 size) u32 NaomiCartridge::ReadMem(u32 address, u32 size)
{ {
verify(size!=1); verify(size!=1);
//printf("+naomi?WTF? ReadMem: %X, %d\n", address, size);
switch(address & 255) switch(address & 255)
{ {
case 0x3c: case 0x3c: // 5f703c: DIMM COMMAND
DEBUG_LOG(NAOMI, "naomi GD? READ: %X, %d", address, size); DEBUG_LOG(NAOMI, "DIMM COMMAND read<%d>", size);
return reg_dimm_3c | (NaomiDataRead ? 0 : -1); //pretend the board isn't there for the bios return reg_dimm_command | (NaomiDataRead ? 0 : -1); //pretend the board isn't there for the bios
case 0x40: case 0x40: // 5f7040: DIMM OFFSETL
DEBUG_LOG(NAOMI, "naomi GD? READ: %X, %d", address, size); DEBUG_LOG(NAOMI, "DIMM OFFSETL read<%d>", size);
return reg_dimm_40; return reg_dimm_offsetl;
case 0x44: case 0x44: // 5f7044: DIMM PARAMETERL
DEBUG_LOG(NAOMI, "naomi GD? READ: %X, %d", address, size); DEBUG_LOG(NAOMI, "DIMM PARAMETERL read<%d>", size);
return reg_dimm_44; return reg_dimm_parameterl;
case 0x48: case 0x48: // 5f7048: DIMM PARAMETERH
DEBUG_LOG(NAOMI, "naomi GD? READ: %X, %d", address, size); DEBUG_LOG(NAOMI, "DIMM PARAMETERH read<%d>", size);
return reg_dimm_48; return reg_dimm_parameterh;
case 0x04C: // 5f704c: DIMM STATUS
DEBUG_LOG(NAOMI, "DIMM STATUS read<%d>", size);
return reg_dimm_status;
//These are known to be valid on normal ROMs and DIMM board
case NAOMI_ROM_OFFSETH_addr&255: case NAOMI_ROM_OFFSETH_addr&255:
return RomPioOffset>>16 | (RomPioAutoIncrement << 15); return RomPioOffset>>16 | (RomPioAutoIncrement << 15);
@ -786,7 +788,6 @@ u32 NaomiCartridge::ReadMem(u32 address, u32 size)
return 1; return 1;
//This should be valid
case NAOMI_DMA_OFFSETH_addr&255: case NAOMI_DMA_OFFSETH_addr&255:
return DmaOffset>>16; return DmaOffset>>16;
case NAOMI_DMA_OFFSETL_addr&255: case NAOMI_DMA_OFFSETL_addr&255:
@ -796,10 +797,6 @@ u32 NaomiCartridge::ReadMem(u32 address, u32 size)
DEBUG_LOG(NAOMI, "naomi ReadBoardId: %X, %d", address, size); DEBUG_LOG(NAOMI, "naomi ReadBoardId: %X, %d", address, size);
return 1; return 1;
case 0x04C:
DEBUG_LOG(NAOMI, "naomi GD? READ: %X, %d", address, size);
return reg_dimm_4c;
case NAOMI_COMM2_CTRL_addr & 255: case NAOMI_COMM2_CTRL_addr & 255:
DEBUG_LOG(NAOMI, "NAOMI_COMM2_CTRL read"); DEBUG_LOG(NAOMI, "NAOMI_COMM2_CTRL read");
return comm_ctrl; return comm_ctrl;
@ -840,35 +837,34 @@ u32 NaomiCartridge::ReadMem(u32 address, u32 size)
void NaomiCartridge::WriteMem(u32 address, u32 data, u32 size) void NaomiCartridge::WriteMem(u32 address, u32 data, u32 size)
{ {
// printf("+naomi WriteMem: %X <= %X, %d\n", address, data, size);
switch(address & 255) switch(address & 255)
{ {
case 0x3c: case 0x3c: // 5f703c: DIMM COMMAND
if (0x1E03==data) if (0x1E03 == data)
{ {
/* /*
if (!(reg_dimm_4c&0x100)) if (!(reg_dimm_status & 0x100))
asic_RaiseInterrupt(holly_EXP_PCI); asic_RaiseInterrupt(holly_EXP_PCI);
reg_dimm_4c|=1;*/ reg_dimm_status |= 1;*/
} }
reg_dimm_3c=data; reg_dimm_command = data;
DEBUG_LOG(NAOMI, "naomi GD? Write: %X <= %X, %d", address, data, size); DEBUG_LOG(NAOMI, "DIMM COMMAND Write: %X <= %X, %d", address, data, size);
return; return;
case 0x40: case 0x40: // 5f7040: DIMM OFFSETL
reg_dimm_40=data; reg_dimm_offsetl = data;
DEBUG_LOG(NAOMI, "naomi GD? Write: %X <= %X, %d", address, data, size); DEBUG_LOG(NAOMI, "DIMM OFFSETL Write: %X <= %X, %d", address, data, size);
return; return;
case 0x44: case 0x44: // 5f7044: DIMM PARAMETERL
reg_dimm_44=data; reg_dimm_parameterl = data;
DEBUG_LOG(NAOMI, "naomi GD? Write: %X <= %X, %d", address, data, size); DEBUG_LOG(NAOMI, "DIMM PARAMETERL Write: %X <= %X, %d", address, data, size);
return; return;
case 0x48: case 0x48: // 5f7048: DIMM PARAMETERH
reg_dimm_48=data; reg_dimm_parameterh = data;
DEBUG_LOG(NAOMI, "naomi GD? Write: %X <= %X, %d", address, data, size); DEBUG_LOG(NAOMI, "DIMM PARAMETERH Write: %X <= %X, %d", address, data, size);
return; return;
case 0x4C: case 0x4C: // 5f704c: DIMM STATUS
if (data&0x100) if (data&0x100)
{ {
asic_CancelInterrupt(holly_EXP_PCI); asic_CancelInterrupt(holly_EXP_PCI);
@ -879,10 +875,10 @@ void NaomiCartridge::WriteMem(u32 address, u32 data, u32 size)
/*FILE* ramd=fopen("c:\\ndc.ram.bin","wb"); /*FILE* ramd=fopen("c:\\ndc.ram.bin","wb");
fwrite(mem_b.data,1,RAM_SIZE,ramd); fwrite(mem_b.data,1,RAM_SIZE,ramd);
fclose(ramd);*/ fclose(ramd);*/
naomi_process(reg_dimm_3c,reg_dimm_40,reg_dimm_44,reg_dimm_48); naomi_process(reg_dimm_command, reg_dimm_offsetl, reg_dimm_parameterl, reg_dimm_parameterh);
} }
reg_dimm_4c=data&~0x100; reg_dimm_status = data & ~0x100;
DEBUG_LOG(NAOMI, "naomi GD? Write: %X <= %X, %d", address, data, size); DEBUG_LOG(NAOMI, "DIMM STATUS Write: %X <= %X, %d", address, data, size);
return; return;
//These are known to be valid on normal ROMs and DIMM board //These are known to be valid on normal ROMs and DIMM board

2
core/hw/sh4/modules/fastmmu.cpp
View File

@ -323,7 +323,7 @@ u32 mmu_data_translation(u32 va, u32& rv)
if (va == unresolved_unicode_string) if (va == unresolved_unicode_string)
{ {
unresolved_unicode_string = 0; unresolved_unicode_string = 0;
INFO_LOG(SH4, "RESOLVED %s", get_unicode_string(va).c_str()); printf("RESOLVED %s\n", get_unicode_string(va).c_str());
} }
} }
#endif #endif

2
core/hw/sh4/modules/mmu.cpp
View File

@ -81,6 +81,8 @@ u32 mmu_full_lookup(u32 va, u32& idx, u32& rv);
#ifdef TRACE_WINCE_SYSCALLS #ifdef TRACE_WINCE_SYSCALLS
#include "wince.h" #include "wince.h"
u32 unresolved_ascii_string;
u32 unresolved_unicode_string;
#endif #endif
#define printf_mmu(...) DEBUG_LOG(SH4, __VA_ARGS__) #define printf_mmu(...) DEBUG_LOG(SH4, __VA_ARGS__)

42
core/hw/sh4/modules/wince.h
View File

@ -31,7 +31,7 @@ static bool read_mem32(u32 addr, u32& data)
{ {
u32 pa; u32 pa;
const TLB_Entry *entry; const TLB_Entry *entry;
if (mmu_full_lookup<true>(addr, &entry, pa) != MMU_ERROR_NONE) if (mmu_full_lookup<false>(addr, &entry, pa) != MMU_ERROR_NONE)
return false; return false;
data = ReadMem32_nommu(pa); data = ReadMem32_nommu(pa);
return true; return true;
@ -41,7 +41,7 @@ static bool read_mem16(u32 addr, u16& data)
{ {
u32 pa; u32 pa;
const TLB_Entry *entry; const TLB_Entry *entry;
if (mmu_full_lookup<true>(addr, &entry, pa) != MMU_ERROR_NONE) if (mmu_full_lookup<false>(addr, &entry, pa) != MMU_ERROR_NONE)
return false; return false;
data = ReadMem16_nommu(pa); data = ReadMem16_nommu(pa);
return true; return true;
@ -51,7 +51,7 @@ static bool read_mem8(u32 addr, u8& data)
{ {
u32 pa; u32 pa;
const TLB_Entry *entry; const TLB_Entry *entry;
if (mmu_full_lookup<true>(addr, &entry, pa) != MMU_ERROR_NONE) if (mmu_full_lookup<false>(addr, &entry, pa) != MMU_ERROR_NONE)
return false; return false;
data = ReadMem8_nommu(pa); data = ReadMem8_nommu(pa);
return true; return true;
@ -227,10 +227,10 @@ static const char *wince_methods[][256] = {
}, },
}; };
u32 unresolved_ascii_string; extern u32 unresolved_ascii_string;
u32 unresolved_unicode_string; extern u32 unresolved_unicode_string;
std::string get_unicode_string(u32 addr) static inline std::string get_unicode_string(u32 addr)
{ {
std::string str; std::string str;
while (true) while (true)
@ -248,7 +248,7 @@ std::string get_unicode_string(u32 addr)
} }
return str; return str;
} }
std::string get_ascii_string(u32 addr) static inline std::string get_ascii_string(u32 addr)
{ {
std::string str; std::string str;
while (true) while (true)
@ -312,31 +312,33 @@ static bool print_wince_syscall(u32 address)
sprintf(method_buf, "[%d]", meth_id); sprintf(method_buf, "[%d]", meth_id);
method = method_buf; method = method_buf;
} }
INFO_LOG(SH4, "WinCE %08x %04x.%04x %s: %s", address, getCurrentProcessId() & 0xffff, getCurrentThreadId() & 0xffff, api, method); printf("WinCE %08x %04x.%04x %s: %s", address, getCurrentProcessId() & 0xffff, getCurrentThreadId() & 0xffff, api, method);
if (address == 0xfffffd51) // SetLastError if (address == 0xfffffd51) // SetLastError
INFO_LOG(SH4, " dwErrCode = %x", r[4]); printf(" dwErrCode = %x\n", r[4]);
else if (address == 0xffffd5ef) // CreateFile else if (address == 0xffffd5ef) // CreateFile
INFO_LOG(SH4, " lpFileName = %s", get_unicode_string(r[4]).c_str()); printf(" lpFileName = %s\n", get_unicode_string(r[4]).c_str());
else if (address == 0xfffffd97) // CreateProc else if (address == 0xfffffd97) // CreateProc
INFO_LOG(SH4, " imageName = %s, commandLine = %s", get_unicode_string(r[4]).c_str(), get_unicode_string(r[5]).c_str()); printf(" imageName = %s, commandLine = %s\n", get_unicode_string(r[4]).c_str(), get_unicode_string(r[5]).c_str());
else if (!strcmp("DebugNotify", method)) else if (!strcmp("DebugNotify", method))
INFO_LOG(SH4, " %x, %x\n", r[4], r[5]); printf(" %x, %x\n", r[4], r[5]);
else if (address == 0xffffd5d3) // RegOpenKeyExW else if (address == 0xffffd5d3) // RegOpenKeyExW
INFO_LOG(SH4, " hKey = %x, lpSubKey = %s", r[4], get_unicode_string(r[5]).c_str()); printf(" hKey = %x, lpSubKey = %s\n", r[4], get_unicode_string(r[5]).c_str());
else if (!strcmp("LoadLibraryW", method)) else if (!strcmp("LoadLibraryW", method))
INFO_LOG(SH4, " fileName = %s", get_unicode_string(r[4]).c_str()); printf(" fileName = %s\n", get_unicode_string(r[4]).c_str());
else if (!strcmp("GetProcAddressW", method)) else if (!strcmp("GetProcAddressW", method))
INFO_LOG(SH4, " hModule = %x, procName = %s", r[4], get_unicode_string(r[5]).c_str()); printf(" hModule = %x, procName = %s\n", r[4], get_unicode_string(r[5]).c_str());
else if (!strcmp("NKvDbgPrintfW", method)) else if (!strcmp("NKvDbgPrintfW", method))
INFO_LOG(SH4, " fmt = %s", get_unicode_string(r[4]).c_str()); printf(" fmt = %s\n", get_unicode_string(r[4]).c_str());
else if (!strcmp("OutputDebugStringW", method)) else if (!strcmp("OutputDebugStringW", method))
INFO_LOG(SH4, " str = %s", get_unicode_string(r[4]).c_str()); printf(" str = %s\n", get_unicode_string(r[4]).c_str());
else if (!strcmp("RegisterAFSName", method)) else if (!strcmp("RegisterAFSName", method))
INFO_LOG(SH4, " name = %s", get_unicode_string(r[4]).c_str()); printf(" name = %s\n", get_unicode_string(r[4]).c_str());
else if (!strcmp("CreateAPISet", method)) else if (!strcmp("CreateAPISet", method))
INFO_LOG(SH4, " name = %s", get_ascii_string(r[4]).c_str()); printf(" name = %s\n", get_ascii_string(r[4]).c_str());
else if (!strcmp("Register", method) && !strcmp("APISET", api)) else if (!strcmp("Register", method) && !strcmp("APISET", api))
INFO_LOG(SH4, " p = %x, id = %x", r[4], r[5]); printf(" p = %x, id = %x\n", r[4], r[5]);
else
printf("\n");
// might be useful to detect errors? (hidden & dangerous) // might be useful to detect errors? (hidden & dangerous)
//if (!strcmp("GetProcName", method)) //if (!strcmp("GetProcName", method))
// os_DebugBreak(); // os_DebugBreak();

2
core/rend/norend/norend.cpp
View File

@ -22,7 +22,7 @@ struct norend : Renderer
bool Render() bool Render()
{ {
return true;//!pvrrc.isRTT; return !pvrrc.isRTT;
} }
void Present() { } void Present() { }

40
core/serialize.cpp
View File

@ -622,11 +622,11 @@ extern int SerStep;
extern int SerStep2; extern int SerStep2;
extern unsigned char BSerial[]; extern unsigned char BSerial[];
extern unsigned char GSerial[]; extern unsigned char GSerial[];
extern u32 reg_dimm_3c; //IO window ! writen, 0x1E03 some flag ? extern u32 reg_dimm_command;
extern u32 reg_dimm_40; //parameters extern u32 reg_dimm_offsetl;
extern u32 reg_dimm_44; //parameters extern u32 reg_dimm_parameterl;
extern u32 reg_dimm_48; //parameters extern u32 reg_dimm_parameterh;
extern u32 reg_dimm_4c; //status/control reg ? extern u32 reg_dimm_status;
extern bool NaomiDataRead; extern bool NaomiDataRead;
@ -1079,11 +1079,11 @@ bool dc_serialize(void **data, unsigned int *total_size)
REICAST_S(SerStep2); REICAST_S(SerStep2);
REICAST_SA(BSerial,69); REICAST_SA(BSerial,69);
REICAST_SA(GSerial,69); REICAST_SA(GSerial,69);
REICAST_S(reg_dimm_3c); REICAST_S(reg_dimm_command);
REICAST_S(reg_dimm_40); REICAST_S(reg_dimm_offsetl);
REICAST_S(reg_dimm_44); REICAST_S(reg_dimm_parameterl);
REICAST_S(reg_dimm_48); REICAST_S(reg_dimm_parameterh);
REICAST_S(reg_dimm_4c); REICAST_S(reg_dimm_status);
REICAST_S(NaomiDataRead); REICAST_S(NaomiDataRead);
#if FEAT_SHREC == DYNAREC_CPP #if FEAT_SHREC == DYNAREC_CPP
@ -1471,11 +1471,11 @@ static bool dc_unserialize_libretro(void **data, unsigned int *total_size)
REICAST_US(SerStep2); REICAST_US(SerStep2);
REICAST_USA(BSerial,69); REICAST_USA(BSerial,69);
REICAST_USA(GSerial,69); REICAST_USA(GSerial,69);
REICAST_US(reg_dimm_3c); REICAST_US(reg_dimm_command);
REICAST_US(reg_dimm_40); REICAST_US(reg_dimm_offsetl);
REICAST_US(reg_dimm_44); REICAST_US(reg_dimm_parameterl);
REICAST_US(reg_dimm_48); REICAST_US(reg_dimm_parameterh);
REICAST_US(reg_dimm_4c); REICAST_US(reg_dimm_status);
REICAST_US(NaomiDataRead); REICAST_US(NaomiDataRead);
REICAST_US(i); //LIBRETRO_S(cycle_counter); REICAST_US(i); //LIBRETRO_S(cycle_counter);
@ -1850,11 +1850,11 @@ bool dc_unserialize(void **data, unsigned int *total_size)
REICAST_US(SerStep2); REICAST_US(SerStep2);
REICAST_USA(BSerial,69); REICAST_USA(BSerial,69);
REICAST_USA(GSerial,69); REICAST_USA(GSerial,69);
REICAST_US(reg_dimm_3c); REICAST_US(reg_dimm_command);
REICAST_US(reg_dimm_40); REICAST_US(reg_dimm_offsetl);
REICAST_US(reg_dimm_44); REICAST_US(reg_dimm_parameterl);
REICAST_US(reg_dimm_48); REICAST_US(reg_dimm_parameterh);
REICAST_US(reg_dimm_4c); REICAST_US(reg_dimm_status);
REICAST_US(NaomiDataRead); REICAST_US(NaomiDataRead);
#if FEAT_SHREC == DYNAREC_CPP #if FEAT_SHREC == DYNAREC_CPP