refactor sh4_sr_GetFull/sh4_sr_SetFull

core/debug/debug_agent.h

@@ -122,7 +122,7 @@ public:
 		for (u32 i = 0; i < Sh4RegList.size(); i++)
 		{
 			if (Sh4RegList[i] == reg_sr_status)
-				allregs[i] = sh4_sr_GetFull();
+				allregs[i] = p_sh4rcb->cntx.sr.getFull();
 			else if (Sh4RegList[i] != NoReg)
 				allregs[i] = *GetRegPtr(Sh4RegList[i]);
 		}
@@ -143,7 +143,7 @@ public:
 			return 0;
 		Sh4RegType reg = Sh4RegList[regNum];
 		if (reg == reg_sr_status)
-			return sh4_sr_GetFull();
+			return p_sh4rcb->cntx.sr.getFull();
 		if (reg != NoReg)
 			return *GetRegPtr(reg);
 		return 0;
@@ -154,7 +154,7 @@ public:
 			return;
 		Sh4RegType reg = Sh4RegList[regNum];
 		if (reg == reg_sr_status)
-			sh4_sr_SetFull(value);
+			p_sh4rcb->cntx.sr.setFull(value);
 		else if (reg != NoReg)
 			*GetRegPtr(reg) = value;
 	}

core/hw/sh4/dyna/decoder.cpp

@@ -95,9 +95,6 @@ static void dec_End(u32 dst, BlockEndType flags, bool delaySlot)
 		verify(state.JumpAddr != NullAddress);
 }
 
-#define SR_STATUS_MASK STATUS_MASK
-#define SR_T_MASK 1
-
 static u32 dec_jump_simm8(u32 op)
 {
 	return state.cpu.rpc + GetSImm8(op)*2 + 4;
@@ -114,8 +111,8 @@ static u32 dec_set_pr()
 }
 static void dec_write_sr(shil_param src)
 {
-	Emit(shop_and,mk_reg(reg_sr_status),src,mk_imm(SR_STATUS_MASK));
+	Emit(shop_and, mk_reg(reg_sr_status), src, mk_imm(sr_t::MASK));
-	Emit(shop_and,mk_reg(reg_sr_T),src,mk_imm(SR_T_MASK));
+	Emit(shop_and, mk_reg(reg_sr_T), src, mk_imm(1));
 }
 //bf <bdisp8>
 sh4dec(i1000_1011_iiii_iiii)

core/hw/sh4/interpr/sh4_opcodes.cpp

@@ -1875,7 +1875,7 @@ sh4op(i0100_nnnn_0001_1011)
 sh4op(i0000_nnnn_0000_0010)//0002
 {
 	u32 n = GetN(op);
-	r[n] = sh4_sr_GetFull();
+	r[n] = sr.getFull();
 }
 
  //sts FPSCR,<REG_N>
@@ -1897,7 +1897,7 @@ sh4op(i0100_nnnn_0110_0010)
 sh4op(i0100_nnnn_0000_0011)
 {
 	u32 n = GetN(op);
-	WriteMemU32(r[n] - 4, sh4_sr_GetFull());
+	WriteMemU32(r[n] - 4, sr.getFull());
 	r[n] -= 4;
 }
 
@@ -1920,7 +1920,7 @@ sh4op(i0100_nnnn_0000_0111)
 	u32 sr_t;
 	ReadMemU32(sr_t,r[n]);
 
-	sh4_sr_SetFull(sr_t);
+	sr.setFull(sr_t);
 	r[n] += 4;
 	if (UpdateSR())
 		UpdateINTC();
@@ -1938,7 +1938,7 @@ sh4op(i0100_nnnn_0110_1010)
 sh4op(i0100_nnnn_0000_1110)
 {
 	u32 n = GetN(op);
-	sh4_sr_SetFull(r[n]);
+	sr.setFull(r[n]);
 	if (UpdateSR())
 		UpdateINTC();
 }

core/hw/sh4/sh4_if.h

@@ -145,8 +145,6 @@ union sr_status_t
 	u32 status;
 };
 
-#define STATUS_MASK 0x700083F2
-
 // Status register with isolated T bit.
 // Used in place of the normal SR bitfield so that the T bit can be
 // handled as a regular register. This simplifies dynarec implementations.
@@ -173,6 +171,17 @@ struct sr_t
 		u32 status;
 	};
 	u32 T;
+
+	static constexpr u32 MASK = 0x700083F2;
+
+	u32 getFull() const {
+		return (status & MASK) | T;
+	}
+
+	void setFull(u32 v) {
+		status = v & MASK;
+		T = v & 1;
+	}
 };
 
 // FPSCR (fpu status and control register)
@@ -300,17 +309,6 @@ struct alignas(PAGE_SIZE) Sh4RCB
 
 extern Sh4RCB* p_sh4rcb;
 
-static inline u32 sh4_sr_GetFull()
-{
-	return (p_sh4rcb->cntx.sr.status & STATUS_MASK) | p_sh4rcb->cntx.sr.T;
-}
-
-static inline void sh4_sr_SetFull(u32 value)
-{
-	p_sh4rcb->cntx.sr.status=value & STATUS_MASK;
-	p_sh4rcb->cntx.sr.T=value&1;
-}
-
 #define do_sqw_nommu sh4rcb.do_sqw_nommu
 
 #define sh4rcb (*p_sh4rcb)

core/hw/sh4/sh4_interrupts.cpp

@@ -185,7 +185,7 @@ static void Do_Interrupt(Sh4ExceptionCode intEvn)
 {
 	CCN_INTEVT = intEvn;
 
-	ssr = sh4_sr_GetFull();
+	ssr = sr.getFull();
 	spc = next_pc;
 	sgr = r[15];
 	sr.BL = 1;
@@ -204,7 +204,7 @@ void Do_Exception(u32 epc, Sh4ExceptionCode expEvn)
 		throw FlycastException("Fatal: SH4 exception when blocked");
 	CCN_EXPEVT = expEvn;
 
-	ssr = sh4_sr_GetFull();
+	ssr = sr.getFull();
 	spc = epc;
 	sgr = r[15];
 	sr.BL = 1;