diff --git a/core/hw/sh4/interpr/sh4_interpreter.cpp b/core/hw/sh4/interpr/sh4_interpreter.cpp
index 027ea4223..4d2d21eac 100644
--- a/core/hw/sh4/interpr/sh4_interpreter.cpp
+++ b/core/hw/sh4/interpr/sh4_interpreter.cpp
@@ -109,6 +109,8 @@ void Sh4_int_Reset(bool hard)
 	}
 	else
 	{
+		if (hard)
+			memset(&p_sh4rcb->cntx, 0, sizeof(p_sh4rcb->cntx));
 		next_pc = 0xA0000000;
 
 		memset(r,0,sizeof(r));
diff --git a/core/hw/sh4/modules/bsc.cpp b/core/hw/sh4/modules/bsc.cpp
index a238785b7..8346c2417 100644
--- a/core/hw/sh4/modules/bsc.cpp
+++ b/core/hw/sh4/modules/bsc.cpp
@@ -111,10 +111,9 @@ void bsc_init()
 
 	//note: naomi//aw might depend on rfcr
 	sh4_rio_reg(BSC, BSC_RFCR_addr, RIO_RO, 16);
-	BSC_RFCR.full = 17;
 }
 
-void bsc_reset()
+void bsc_reset(bool hard)
 {
 	/*
 	BSC BCR1 H'FF80 0000 H'1F80 0000 32 H'0000 0000*2 Held Held Held Bclk
@@ -149,9 +148,11 @@ void bsc_reset()
 	BSC_RTCNT.full=0x0;
 	BSC_RTCOR.full=0x0;
 	BSC_PCTRA.full=0x0;
-	//BSC_PDTRA.full; undef
+	if (hard)
+		BSC_PDTRA.full = 0;
 	BSC_PCTRB.full=0x0;
-	//BSC_PDTRB.full; undef
+	if (hard)
+		BSC_PDTRB.full = 0;
 	BSC_GPIOIC.full=0x0;
 
 	BSC_RFCR.full = 17;
diff --git a/core/hw/sh4/modules/modules.h b/core/hw/sh4/modules/modules.h
index 7d726a3af..59f5c4393 100644
--- a/core/hw/sh4/modules/modules.h
+++ b/core/hw/sh4/modules/modules.h
@@ -2,7 +2,7 @@
 #include "types.h"
 
 void bsc_init();
-void bsc_reset();
+void bsc_reset(bool hard);
 void bsc_term();
 
 
@@ -31,7 +31,7 @@ void ubc_reset();
 void ubc_term();
 
 void tmu_init();
-void tmu_reset();
+void tmu_reset(bool hard);
 void tmu_term();
 
 void ccn_init();
diff --git a/core/hw/sh4/modules/tmu.cpp b/core/hw/sh4/modules/tmu.cpp
index 56b2d9996..0c71d5581 100644
--- a/core/hw/sh4/modules/tmu.cpp
+++ b/core/hw/sh4/modules/tmu.cpp
@@ -10,24 +10,23 @@
 
 #define tmu_underflow 0x0100
 #define tmu_UNIE      0x0020
-/*
-u32 tmu_prescaler[3];
-u32 tmu_prescaler_shift[3];
-u32 tmu_prescaler_mask[3];
-*/
 
 u32 tmu_shift[3];
 u32 tmu_mask[3];
 u64 tmu_mask64[3];
 
-const u32 tmu_ch_bit[3]={1,2,4};
-
 u32 old_mode[3] = {0xFFFF,0xFFFF,0xFFFF};
 
-const InterruptID tmu_intID[3]={sh4_TMU0_TUNI0,sh4_TMU1_TUNI1,sh4_TMU2_TUNI2};
+static const InterruptID tmu_intID[3]={sh4_TMU0_TUNI0,sh4_TMU1_TUNI1,sh4_TMU2_TUNI2};
 int tmu_sched[3];
 
 #if 0
+const u32 tmu_ch_bit[3]={1,2,4};
+
+u32 tmu_prescaler[3];
+u32 tmu_prescaler_shift[3];
+u32 tmu_prescaler_mask[3];
+
 //Accurate counts for the channel ch
 template<u32 ch>
 void UpdateTMU_chan(u32 clc)
@@ -302,8 +301,17 @@ void tmu_init()
 }
 
 
-void tmu_reset()
+void tmu_reset(bool hard)
 {
+	if (hard)
+	{
+		memset(tmu_shift, 0, sizeof(tmu_shift));
+		memset(tmu_mask, 0, sizeof(tmu_mask));
+		memset(tmu_mask64, 0, sizeof(tmu_mask64));
+		memset(old_mode, 0xFF, sizeof(old_mode));
+		memset(tmu_ch_base, 0, sizeof(tmu_ch_base));
+		memset(tmu_ch_base64, 0, sizeof(tmu_ch_base64));
+	}
 	TMU_TOCR=TMU_TSTR=0;
 	TMU_TCOR(0) = TMU_TCOR(1) = TMU_TCOR(2) = 0xffffffff;
 //	TMU_TCNT(0) = TMU_TCNT(1) = TMU_TCNT(2) = 0xffffffff;
diff --git a/core/hw/sh4/sh4_mmr.cpp b/core/hw/sh4/sh4_mmr.cpp
index a15919741..b3db050ca 100644
--- a/core/hw/sh4/sh4_mmr.cpp
+++ b/core/hw/sh4/sh4_mmr.cpp
@@ -26,6 +26,8 @@ Array<RegisterStruct> TMU(12,true);  //TMU  : 12 registers
 Array<RegisterStruct> SCI(8,true);   //SCI  : 8 registers
 Array<RegisterStruct> SCIF(10,true); //SCIF : 10 registers
 
+Array<RegisterStruct> * const AllRegisters[] = { &CCN, &UBC, &BSC, &DMAC, &CPG, &RTC, &INTC, &TMU, &SCI, &SCIF };
+
 u32 sh4io_read_noacc(u32 addr) 
 { 
 	INFO_LOG(SH4, "sh4io: Invalid read access @@ %08X", addr);
@@ -828,40 +830,20 @@ void sh4_mmr_reset(bool hard)
 {
 	if (hard)
 	{
-		for (int i = 0; i < 30; i++)
-		{
-			if (i < CCN.Size)
-				CCN[i].reset();
-			if (i < UBC.Size)
-				UBC[i].reset();
-			if (i < BSC.Size)
-				BSC[i].reset();
-			if (i < DMAC.Size)
-				DMAC[i].reset();
-			if (i < CPG.Size)
-				CPG[i].reset();
-			if (i < RTC.Size)
-				RTC[i].reset();
-			if (i < INTC.Size)
-				INTC[i].reset();
-			if (i < TMU.Size)
-				TMU[i].reset();
-			if (i < SCI.Size)
-				SCI[i].reset();
-			if (i < SCIF.Size)
-				SCIF[i].reset();
-		}
+		for (int i = 0; i < ARRAY_SIZE(AllRegisters); i++)
+			for (int j = 0; j < AllRegisters[i]->Size; j++)
+				(*AllRegisters[i])[j].reset();
 	}
 	OnChipRAM.Zero();
 	//Reset register values
-	bsc_reset();
+	bsc_reset(hard);
 	ccn_reset();
 	cpg_reset();
 	dmac_reset();
 	intc_reset();
 	rtc_reset();
 	serial_reset();
-	tmu_reset();
+	tmu_reset(hard);
 	ubc_reset();
 }