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arm[64] dynarec: xtrct can have immediate operands 

Fixes MINIDUMP-15
Sakura Taisen 2 crash
This commit is contained in:
Flyinghead 2023-01-03 15:15:13 +01:00
parent ba0a357d48
commit 9ef37d9776
2 changed files with 40 additions and 8 deletions
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20
core/rec-ARM/rec_arm.cpp
View File

@ -1748,8 +1748,24 @@ static void ngen_compile_opcode(RuntimeBlockInfo* block, shil_opcode* op, bool o
case shop_xtrct:
{
Register rd = reg.mapReg(op->rd);
Register rs1 = reg.mapReg(op->rs1);
Register rs2 = reg.mapReg(op->rs2);
Register rs1;
if (op->rs1.is_imm()) {
rs1 = r1;
ass.Mov(rs1, op->rs1._imm);
}
else
{
rs1 = reg.mapReg(op->rs1);
}
Register rs2;
if (op->rs2.is_imm()) {
rs2 = r2;
ass.Mov(rs2, op->rs2._imm);
}
else
{
rs2 = reg.mapReg(op->rs2);
}
if (rd.Is(rs1))
{
verify(!rd.Is(rs2));

28
core/rec-ARM64/rec_arm64.cpp
View File

@ -791,12 +791,12 @@ public:
{
reg2 = regalloc.MapRegister(op.rs2);
}
const Register& rd_xreg = Register::GetXRegFromCode(regalloc.MapRegister(op.rd).GetCode());
const Register& rd_xreg = regalloc.MapRegister(op.rd).X();
if (op.op == shop_mul_u64)
Umull(rd_xreg, regalloc.MapRegister(op.rs1), reg2);
else
Smull(rd_xreg, regalloc.MapRegister(op.rs1), reg2);
const Register& rd2_xreg = Register::GetXRegFromCode(regalloc.MapRegister(op.rd2).GetCode());
const Register& rd2_xreg = regalloc.MapRegister(op.rd2).X();
Lsr(rd2_xreg, rd_xreg, 32);
}
break;
@ -855,11 +855,27 @@ public:
case shop_xtrct:
{
const Register rd = regalloc.MapRegister(op.rd);
const Register rs1 = regalloc.MapRegister(op.rs1);
const Register rs2 = regalloc.MapRegister(op.rs2);
if (op.rs1._reg == op.rd._reg)
Register rs1;
if (op.rs1.is_imm()) {
rs1 = w1;
Mov(rs1, op.rs1._imm);
}
else
{
verify(op.rs2._reg != op.rd._reg);
rs1 = regalloc.MapRegister(op.rs1);
}
Register rs2;
if (op.rs2.is_imm()) {
rs2 = w2;
Mov(rs2, op.rs2._imm);
}
else
{
rs2 = regalloc.MapRegister(op.rs2);
}
if (rd.Is(rs1))
{
verify(!rd.Is(rs2));
Lsr(rd, rs1, 16);
Lsl(w0, rs2, 16);
}