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unneeded address/value masking. clean up

This commit is contained in:
Flyinghead 2021-04-01 22:17:29 +02:00
parent 2e0c15bae7
commit 92abf760de
4 changed files with 115 additions and 147 deletions
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148
core/hw/aica/aica_if.cpp
View File

@ -40,77 +40,71 @@ u32 GetRTC_now()
return (20 * 365 + 5) * 24 * 60 * 60 + rawtime + time_offset;
}
u32 ReadMem_aica_rtc(u32 addr,u32 sz)
u32 ReadMem_aica_rtc(u32 addr, u32 sz)
{
switch( addr & 0xFF )
switch (addr & 0xFF)
{
case 0:
return RealTimeClock>>16;
return RealTimeClock >> 16;
case 4:
return RealTimeClock &0xFFFF;
return RealTimeClock & 0xFFFF;
case 8:
return 0;
}
WARN_LOG(AICA, "ReadMem_aica_rtc : invalid address %x sz %d", addr, sz);
WARN_LOG(AICA, "ReadMem_aica_rtc: invalid address %x sz %d", addr, sz);
return 0;
}
void WriteMem_aica_rtc(u32 addr,u32 data,u32 sz)
void WriteMem_aica_rtc(u32 addr, u32 data, u32 sz)
{
switch( addr & 0xFF )
switch (addr & 0xFF)
{
case 0:
if (rtc_EN)
{
RealTimeClock&=0xFFFF;
RealTimeClock|=(data&0xFFFF)<<16;
rtc_EN=0;
RealTimeClock &= 0xFFFF;
RealTimeClock |= (data & 0xFFFF) << 16;
rtc_EN = 0;
}
return;
break;
case 4:
if (rtc_EN)
{
RealTimeClock&=0xFFFF0000;
RealTimeClock|= data&0xFFFF;
RealTimeClock &= 0xFFFF0000;
RealTimeClock |= data & 0xFFFF;
//TODO: Clean the internal timer ?
}
return;
break;
case 8:
rtc_EN=data&1;
return;
rtc_EN = data & 1;
break;
default:
WARN_LOG(AICA, "WriteMem_aica_rtc: invalid address %x sz %d data %x", addr, sz, data);
break;
}
}
u32 ReadMem_aica_reg(u32 addr,u32 sz)
u32 ReadMem_aica_reg(u32 addr, u32 sz)
{
addr&=0x7FFF;
if (sz==1)
addr &= 0x7FFF;
if (sz == 1)
{
if (addr==0x2C01)
{
return VREG;
}
else if (addr==0x2C00)
switch (addr)
{
case 0x2C00:
return ARMRST;
}
else
{
return libAICA_ReadReg(addr, sz);
}
}
else
{
if (addr==0x2C00)
{
return (VREG<<8) | ARMRST;
}
else
{
return libAICA_ReadReg(addr, sz);
case 0x2C01:
return VREG;
default:
break;
}
}
else if (addr == 0x2C00)
return (VREG << 8) | ARMRST;
return libAICA_ReadReg(addr, sz);
}
static void ArmSetRST()
@ -121,40 +115,34 @@ static void ArmSetRST()
void WriteMem_aica_reg(u32 addr,u32 data,u32 sz)
{
addr&=0x7FFF;
addr &= 0x7FFF;
if (sz==1)
if (sz == 1)
{
if (addr==0x2C01)
switch (addr)
{
VREG=data;
INFO_LOG(AICA_ARM, "VREG = %02X", VREG);
}
else if (addr==0x2C00)
{
ARMRST=data;
case 0x2C00:
ARMRST = data;
INFO_LOG(AICA_ARM, "ARMRST = %02X", ARMRST);
ArmSetRST();
}
else
{
libAICA_WriteReg(addr,data,sz);
return;
case 0x2C01:
VREG = data;
INFO_LOG(AICA_ARM, "VREG = %02X", VREG);
return;
default:
break;
}
}
else
else if (addr == 0x2C00)
{
if (addr==0x2C00)
{
VREG=(data>>8)&0xFF;
ARMRST=data&0xFF;
INFO_LOG(AICA_ARM, "VREG = %02X ARMRST %02X", VREG, ARMRST);
ArmSetRST();
}
else
{
libAICA_WriteReg(addr,data,sz);
}
VREG = (data >> 8) & 0xFF;
ARMRST = data & 0xFF;
INFO_LOG(AICA_ARM, "VREG = %02X ARMRST %02X", VREG, ARMRST);
ArmSetRST();
return;
}
libAICA_WriteReg(addr, data, sz);
}
static int DreamcastSecond(int tag, int c, int j)
@ -196,15 +184,15 @@ void aica_Term()
static int dma_end_sched(int tag, int cycl, int jitt)
{
u32 len=SB_ADLEN & 0x7FFFFFFF;
u32 len = SB_ADLEN & 0x7FFFFFFF;
if (SB_ADLEN & 0x80000000)
SB_ADEN = 0;
else
SB_ADEN = 1;
SB_ADSTAR+=len;
SB_ADSTAG+=len;
SB_ADSTAR += len;
SB_ADSTAG += len;
SB_ADST = 0; // dma done
SB_ADLEN = 0;
@ -251,7 +239,9 @@ static bool check_STAR_overrun(u32 addr)
#endif
}
template<u32 ENABLE, u32 START, u32 SRC, u32 DEST, u32 LEN, u32 DIR, HollyInterruptID interrupt, HollyInterruptID iainterrupt, HollyInterruptID ovinterrupt, const char *LogTag>
template<u32 ENABLE, u32 START, u32 SRC, u32 DEST, u32 LEN, u32 DIR,
HollyInterruptID interrupt, HollyInterruptID iainterrupt, HollyInterruptID ovinterrupt,
const char *LogTag>
void Write_DmaStart(u32 addr, u32 data)
{
u32& enableReg = SB_REGN_32(ENABLE);
@ -261,7 +251,7 @@ void Write_DmaStart(u32 addr, u32 data)
u32& lenReg = SB_REGN_32(LEN);
const u32 dirReg = SB_REGN_32(DIR);
if (!(data & 1) || !(enableReg & 1))
if (!(data & 1) || enableReg == 0)
return;
u32 src = sourceReg;
u32 dst = destReg;
@ -296,14 +286,8 @@ void Write_DmaStart(u32 addr, u32 data)
}
if (dirReg == 1)
{
u32 t = src;
src = dst;
dst = t;
DEBUG_LOG(AICA, "%s: DIR == 1 DMA Read to 0x%X from 0x%X %d bytes", LogTag, dst, src, len);
}
else
DEBUG_LOG(AICA, "%s: DIR == 0 DMA Write to 0x%X from 0x%X %d bytes", LogTag, dst, src, len);
std::swap(src, dst);
DEBUG_LOG(AICA, "%s: DMA Write to %X from %X %d bytes", LogTag, dst, src, len);
WriteMemBlock_nommu_dma(dst, src, len);
@ -333,7 +317,7 @@ static void Write_SB_ADST(u32 addr, u32 data)
if ((data & 1) == 1 && (SB_ADST & 1) == 0)
{
if (SB_ADEN&1)
if (SB_ADEN == 1)
{
u32 src = SB_ADSTAR;
u32 dst = SB_ADSTAG;
@ -365,18 +349,16 @@ static void Write_SB_ADST(u32 addr, u32 data)
return;
}
if ((SB_ADDIR&1)==1)
if (SB_ADDIR == 1)
{
//swap direction
u32 tmp=src;
src=dst;
dst=tmp;
std::swap(src, dst);
DEBUG_LOG(AICA, "AICA-DMA : SB_ADDIR==1 DMA Read to 0x%X from 0x%X %x bytes", dst, src, SB_ADLEN);
}
else
DEBUG_LOG(AICA, "AICA-DMA : SB_ADDIR==0:DMA Write to 0x%X from 0x%X %x bytes", dst, src, SB_ADLEN);
WriteMemBlock_nommu_dma(dst,src,len);
WriteMemBlock_nommu_dma(dst, src, len);
// indicate that dma is in progress
SB_ADST = 1;

12
core/hw/maple/maple_if.cpp
View File

@ -42,7 +42,7 @@ void maple_vblank()
{
if (SB_MDEN & 1)
{
if (SB_MDTSEL & 1)
if (SB_MDTSEL == 1)
{
if (maple_ddt_pending_reset)
{
@ -321,13 +321,13 @@ void maple_Init()
void maple_Reset(bool hard)
{
maple_ddt_pending_reset=false;
SB_MDTSEL = 0x00000000;
SB_MDEN = 0x00000000;
SB_MDST = 0x00000000;
SB_MDTSEL = 0;
SB_MDEN = 0;
SB_MDST = 0;
SB_MSYS = 0x3A980000;
SB_MSHTCL = 0x00000000;
SB_MSHTCL = 0;
SB_MDAPRO = 0x00007F00;
SB_MMSEL = 0x00000001;
SB_MMSEL = 1;
}
void maple_Term()

100
core/hw/pvr/pvr_sb_regs.cpp
View File

@ -10,120 +10,105 @@
#include "hw/sh4/modules/dmac.h"
#include "hw/sh4/sh4_mem.h"
void RegWrite_SB_C2DST(u32 addr, u32 data)
static void RegWrite_SB_C2DST(u32 addr, u32 data)
{
if(1&data)
if (data & 1)
{
SB_C2DST=1;
SB_C2DST = 1;
DMAC_Ch2St();
}
}
//PVR-DMA
void do_pvr_dma()
{
u32 dmaor = DMAC_DMAOR.full;
//PVR-DMA
static void do_pvr_dma()
{
u32 src = SB_PDSTAR; // System RAM address
u32 dst = SB_PDSTAP; // VRAM address
u32 len = SB_PDLEN;
if(0x8201 != (dmaor &DMAOR_MASK))
if (0x8201 != (DMAC_DMAOR.full & DMAOR_MASK))
{
INFO_LOG(PVR, "DMAC: DMAOR has invalid settings (%X) !", dmaor);
return;
}
if (len & 0x1F)
{
INFO_LOG(PVR, "DMAC: SB_C2DLEN has invalid size (%X) !", len);
INFO_LOG(PVR, "DMAC: DMAOR has invalid settings (%X) !", DMAC_DMAOR.full);
return;
}
DEBUG_LOG(PVR, "PVR-DMA %x %s %x len %x", src, SB_PDDIR ? "<-" : "->", dst, len);
if (SB_PDDIR)
{
//PVR -> System
WriteMemBlock_nommu_dma(src, dst, len);
}
else
{
//System -> PVR
WriteMemBlock_nommu_dma(dst,src,len);
}
DMAC_SAR(0) = (src + len);
DMAC_SAR(0) = src + len;
DMAC_CHCR(0).TE = 1;
DMAC_DMATCR(0) = 0x00000000;
DMAC_DMATCR(0) = 0;
SB_PDST = 0x00000000;
SB_PDST = 0;
//TODO : *CHECKME* is that ok here ? the docs don't say here it's used [PVR-DMA , bit 11]
asic_RaiseInterrupt(holly_PVR_DMA);
}
void RegWrite_SB_PDST(u32 addr, u32 data)
static void RegWrite_SB_PDST(u32 addr, u32 data)
{
if(1&data)
if (data & 1)
{
SB_PDST=1;
SB_PDST = 1;
do_pvr_dma();
}
}
u32 calculate_start_link_addr()
// Auto sort DMA
static u32 calculate_start_link_addr()
{
u8* base = &mem_b[SB_SDSTAW & (RAM_MASK - 31)];
u8* base = &mem_b[SB_SDSTAW & RAM_MASK];
u32 rv;
if (SB_SDWLT==0)
{
if (SB_SDWLT == 0)
//16b width
rv=((u16*)base)[SB_SDDIV];
}
rv = ((u16*)base)[SB_SDDIV];
else
{
//32b width
rv=((u32*)base)[SB_SDDIV];
}
rv = ((u32*)base)[SB_SDDIV];
SB_SDDIV++; //next index
return rv;
}
void pvr_do_sort_dma()
{
SB_SDDIV=0;//index is 0 now :)
u32 link_addr=calculate_start_link_addr();
static void pvr_do_sort_dma()
{
DEBUG_LOG(PVR, "Sort-DMA SB_SDSTAW %x SB_SDDIV %x SB_SDBAAW %x", SB_SDSTAW, SB_SDDIV, SB_SDBAAW);
SB_SDDIV = 0; // index is 0 now
u32 link_addr = calculate_start_link_addr();
while (link_addr != 2)
{
if (SB_SDLAS==1)
link_addr*=32;
if (SB_SDLAS == 1)
link_addr *= 32;
else
link_addr &= ~31;
u32 ea = (SB_SDBAAW + link_addr) & RAM_MASK & ~31;
u32* ea_ptr=(u32*)&mem_b[ea];
u32 ea = (SB_SDBAAW + link_addr) & RAM_MASK;
u32* ea_ptr = (u32 *)&mem_b[ea];
link_addr=ea_ptr[0x1C>>2];//Next link
link_addr = ea_ptr[0x1C >> 2];//Next link
//transfer global param
ta_vtx_data((const SQBuffer *)ea_ptr, ea_ptr[0x18 >> 2]);
if (link_addr == 1)
{
link_addr=calculate_start_link_addr();
}
link_addr = calculate_start_link_addr();
}
// End of DMA :)
SB_SDST=0;
// End of DMA
SB_SDST = 0;
SB_SDSTAW += 32;
asic_RaiseInterrupt(holly_PVR_SortDMA);
}
// Auto sort DMA :|
void RegWrite_SB_SDST(u32 addr, u32 data)
static void RegWrite_SB_SDST(u32 addr, u32 data)
{
if(1&data)
{
if (data & 1)
pvr_do_sort_dma();
}
}
//Init/Term , global
void pvr_sb_Init()
{
//0x005F7C18 SB_PDST RW PVR-DMA start
@ -135,10 +120,11 @@ void pvr_sb_Init()
//0x005F6820 SB_SDST RW Sort-DMA start
sb_rio_register(SB_SDST_addr,RIO_WF,0,&RegWrite_SB_SDST);
}
void pvr_sb_Term()
{
}
//Reset -> Reset - Initialise
void pvr_sb_Reset(bool hard)
{
}

2
core/hw/sh4/modules/dmac.cpp
View File

@ -19,7 +19,7 @@ void DMAC_Ch2St()
u32 src = DMAC_SAR(2) & 0x1fffffe0;
u32 dst = SB_C2DSTAT & 0x01ffffe0;
u32 len = SB_C2DLEN & 0x00ffffe0;
u32 len = SB_C2DLEN;
if (0x8201 != (dmaor & DMAOR_MASK))
{