Generic interpreted DSP
This commit is contained in:
Flyinghead
parent
63a70e0f62
commit
8c3247d1b2
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@ -1,4 +1,4 @@
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#include "dsp.h"
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#include "dsp.h"
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#include "aica_mem.h"
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#include "hw/aica/aica_if.h"
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#include "oslib/oslib.h"
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@ -22,6 +22,54 @@
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DECL_ALIGN(4096) dsp_t dsp;
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//float format is ?
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u16 DYNACALL PACK(s32 val)
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{
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u32 temp;
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int sign,exponent,k;
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sign = (val >> 23) & 0x1;
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temp = (val ^ (val << 1)) & 0xFFFFFF;
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exponent = 0;
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for (k=0; k<12; k++)
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{
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if (temp & 0x800000)
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break;
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temp <<= 1;
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exponent += 1;
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}
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if (exponent < 12)
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val = (val << exponent) & 0x3FFFFF;
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else
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val <<= 11;
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val >>= 11;
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val |= sign << 15;
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val |= exponent << 11;
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return (u16)val;
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}
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s32 DYNACALL UNPACK(u16 val)
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{
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int sign,exponent,mantissa;
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s32 uval;
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sign = (val >> 15) & 0x1;
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exponent = (val >> 11) & 0xF;
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mantissa = val & 0x7FF;
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uval = mantissa << 11;
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if (exponent > 11)
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exponent = 11;
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else
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uval |= (sign ^ 1) << 22;
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uval |= sign << 23;
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uval <<= 8;
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uval >>= 8;
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uval >>= exponent;
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return uval;
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}
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#if HOST_CPU == CPU_X86 && FEAT_DSPREC == DYNAREC_JIT
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#include "emitter/x86_emitter.h"
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@ -32,38 +80,6 @@ const bool SUPPORT_NOFL=false;
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#pragma warning(disable:4311)
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struct _INST
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{
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unsigned int TRA;
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unsigned int TWT;
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unsigned int TWA;
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unsigned int XSEL;
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unsigned int YSEL;
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unsigned int IRA;
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unsigned int IWT;
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unsigned int IWA;
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unsigned int EWT;
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unsigned int EWA;
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unsigned int ADRL;
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unsigned int FRCL;
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unsigned int SHIFT;
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unsigned int YRL;
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unsigned int NEGB;
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unsigned int ZERO;
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unsigned int BSEL;
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unsigned int NOFL; //MRQ set
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unsigned int TABLE; //MRQ set
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unsigned int MWT; //MRQ set
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unsigned int MRD; //MRQ set
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unsigned int MASA; //MRQ set
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unsigned int ADREB; //MRQ set
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unsigned int NXADR; //MRQ set
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};
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#define DYNBUF 0x10000
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/*
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//#define USEFLOATPACK
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@ -127,55 +143,6 @@ _negme:
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}
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}*/
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//float format is ?
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static u16 DYNACALL PACK(s32 val)
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{
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u32 temp;
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int sign,exponent,k;
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sign = (val >> 23) & 0x1;
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temp = (val ^ (val << 1)) & 0xFFFFFF;
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exponent = 0;
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for (k=0; k<12; k++)
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{
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if (temp & 0x800000)
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break;
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temp <<= 1;
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exponent += 1;
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}
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if (exponent < 12)
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val = (val << exponent) & 0x3FFFFF;
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else
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val <<= 11;
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val >>= 11;
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val |= sign << 15;
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val |= exponent << 11;
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return (u16)val;
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}
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static s32 DYNACALL UNPACK(u16 val)
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{
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int sign,exponent,mantissa;
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s32 uval;
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sign = (val >> 15) & 0x1;
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exponent = (val >> 11) & 0xF;
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mantissa = val & 0x7FF;
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uval = mantissa << 11;
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if (exponent > 11)
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exponent = 11;
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else
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uval |= (sign ^ 1) << 22;
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uval |= sign << 23;
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uval <<= 8;
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uval >>= 8;
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uval >>= exponent;
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return uval;
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}
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void dsp_init()
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{
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memset(&dsp,0,sizeof(dsp));
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@ -187,7 +154,7 @@ void dsp_init()
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dsp.regs.MDEC_CT=1;
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os_MakeExecutable(dsp.DynCode,sizeof(dsp.DynCode));
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//os_MakeExecutable(dsp.DynCode,sizeof(dsp.DynCode));
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}
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void dsp_recompile();
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void DecodeInst(u32 *IPtr,_INST *i)
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@ -252,8 +219,8 @@ void _dsp_debug_step_end()
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verify(dsp.regs_init.TEMPS);
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verify(dsp.regs_init.EFREG);
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}
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#define nwtn(x) verify(!dsp.regs_init.##x)
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#define wtn(x) nwtn(x);dsp.regs_init.##x=true;
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#define nwtn(x) verify(!dsp.regs_init.x)
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#define wtn(x) nwtn(x);dsp.regs_init.x=true;
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//sign extend to 32 bits
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void dsp_rec_se(x86_block& x86e,x86_gpr_reg reg,u32 src_sz,u32 dst_sz=0xFF)
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@ -864,10 +831,4 @@ void dsp_readmem(u32 addr)
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{
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//nothing ? :p
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}
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#else
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void dsp_init() { }
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void dsp_term() { }
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void dsp_step() { }
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void dsp_writenmem(u32 addr) { }
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#endif
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#endif
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@ -8,9 +8,9 @@ struct dsp_t
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//buffered DSP state
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//24 bit wide
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u32 TEMP[128];
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s32 TEMP[128];
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//24 bit wide
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u32 MEMS[32];
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s32 MEMS[32];
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//20 bit wide
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s32 MIXS[16];
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@ -59,7 +59,7 @@ struct dsp_t
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u32 NOFL_2;
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}regs;
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//DEC counter :)
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u32 DEC;
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//u32 DEC;
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//various dsp regs
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signed int ACC; //26 bit
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@ -81,6 +81,8 @@ struct dsp_t
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//EFREG *16
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//EXTS *2
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// Interpreter flags
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bool Stopped;
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//Dynarec flags
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bool dyndirty;
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@ -92,4 +94,39 @@ extern dsp_t dsp;
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void dsp_init();
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void dsp_term();
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void dsp_step();
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void dsp_writenmem(u32 addr);
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void dsp_writenmem(u32 addr);
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struct _INST
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{
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unsigned int TRA;
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unsigned int TWT;
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unsigned int TWA;
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unsigned int XSEL;
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unsigned int YSEL;
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unsigned int IRA;
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unsigned int IWT;
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unsigned int IWA;
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unsigned int EWT;
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unsigned int EWA;
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unsigned int ADRL;
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unsigned int FRCL;
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unsigned int SHIFT;
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unsigned int YRL;
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unsigned int NEGB;
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unsigned int ZERO;
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unsigned int BSEL;
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unsigned int NOFL; //MRQ set
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unsigned int TABLE; //MRQ set
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unsigned int MWT; //MRQ set
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unsigned int MRD; //MRQ set
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unsigned int MASA; //MRQ set
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unsigned int ADREB; //MRQ set
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unsigned int NXADR; //MRQ set
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};
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void DecodeInst(u32 *IPtr,_INST *i);
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u16 DYNACALL PACK(s32 val);
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s32 DYNACALL UNPACK(u16 val);
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@ -0,0 +1,326 @@
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//
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// Audio Overload SDK
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//
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// Copyright (c) 2007-2009 R. Belmont and Richard Bannister, and others.
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// All rights reserved.
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//
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#include "dsp.h"
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#include "aica_if.h"
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#include "aica_mem.h"
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#if FEAT_DSPREC == DYNAREC_NONE
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void AICADSP_Init(struct dsp_t *DSP)
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{
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memset(DSP, 0, sizeof(*DSP));
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DSP->RBL = 0x8000 - 1;
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DSP->Stopped = 1;
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dsp.regs.MDEC_CT = 1;
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}
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void AICADSP_Step(struct dsp_t *DSP)
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{
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s32 ACC = 0; //26 bit
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s32 SHIFTED = 0; //24 bit
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s32 X = 0; //24 bit
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s32 Y = 0; //13 bit
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s32 B = 0; //26 bit
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s32 INPUTS = 0; //24 bit
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s32 MEMVAL[4] = {0};
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s32 FRC_REG = 0; //13 bit
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s32 Y_REG = 0; //24 bit
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u32 ADDR = 0;
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u32 ADRS_REG = 0; //13 bit
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int step;
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memset(DSPData->EFREG, 0, sizeof(DSPData->EFREG));
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if (DSP->Stopped)
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return;
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#if 0
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int dump = 0;
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FILE *f = NULL;
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if (dump)
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f = fopen("dsp.txt", "wt");
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#endif
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for (step = 0; step < 128; ++step)
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{
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u32 *IPtr = DSPData->MPRO + step * 4;
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u32 TRA = (IPtr[0] >> 9) & 0x7F;
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u32 TWT = (IPtr[0] >> 8) & 0x01;
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u32 TWA = (IPtr[0] >> 1) & 0x7F;
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u32 XSEL = (IPtr[1] >> 15) & 0x01;
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u32 YSEL = (IPtr[1] >> 13) & 0x03;
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u32 IRA = (IPtr[1] >> 7) & 0x3F;
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u32 IWT = (IPtr[1] >> 6) & 0x01;
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u32 IWA = (IPtr[1] >> 1) & 0x1F;
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u32 TABLE = (IPtr[2] >> 15) & 0x01;
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u32 MWT = (IPtr[2] >> 14) & 0x01;
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u32 MRD = (IPtr[2] >> 13) & 0x01;
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u32 EWT = (IPtr[2] >> 12) & 0x01;
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u32 EWA = (IPtr[2] >> 8) & 0x0F;
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u32 ADRL = (IPtr[2] >> 7) & 0x01;
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u32 FRCL = (IPtr[2] >> 6) & 0x01;
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u32 SHIFT = (IPtr[2] >> 4) & 0x03;
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u32 YRL = (IPtr[2] >> 3) & 0x01;
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u32 NEGB = (IPtr[2] >> 2) & 0x01;
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u32 ZERO = (IPtr[2] >> 1) & 0x01;
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u32 BSEL = (IPtr[2] >> 0) & 0x01;
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u32 NOFL = (IPtr[3] >> 15) & 1; //????
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verify(!NOFL);
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u32 COEF = step;
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u32 MASA = (IPtr[3] >> 9) & 0x3f; //???
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u32 ADREB = (IPtr[3] >> 8) & 0x1;
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u32 NXADR = (IPtr[3] >> 7) & 0x1;
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// operations are done at 24 bit precision
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#if 0
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#define DUMP(v) printf(" " #v ": %04X",v);
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printf("%d: ",step);
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DUMP(ACC);
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DUMP(SHIFTED);
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DUMP(X);
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DUMP(Y);
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DUMP(B);
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DUMP(INPUTS);
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DUMP(MEMVAL);
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DUMP(FRC_REG);
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DUMP(Y_REG);
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DUMP(ADDR);
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DUMP(ADRS_REG);
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printf("\n");
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#endif
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// INPUTS RW
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verify(IRA < 0x38);
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if (IRA <= 0x1f)
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INPUTS = DSP->MEMS[IRA];
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else if (IRA <= 0x2F)
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INPUTS = DSP->MIXS[IRA - 0x20] << 4; // MIXS is 20 bit
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else if (IRA <= 0x31)
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INPUTS = DSPData->EXTS[IRA - 0x30] << 8; // EXTS is 16 bits
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else
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INPUTS = 0;
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INPUTS <<= 8;
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INPUTS >>= 8;
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if (IWT)
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{
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DSP->MEMS[IWA] = MEMVAL[step & 3]; // MEMVAL was selected in previous MRD
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// "When read and write are specified simultaneously in the same step for INPUTS, TEMP, etc., write is executed after read."
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//if (IRA == IWA)
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// INPUTS = MEMVAL[step & 3];
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}
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// Operand sel
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// B
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if (!ZERO)
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{
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if (BSEL)
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B = ACC;
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else
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{
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B = DSP->TEMP[(TRA + DSP->regs.MDEC_CT) & 0x7F];
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B <<= 8; //Sign extend
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B >>= 8;
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}
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if (NEGB)
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B = 0 - B;
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}
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else
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B = 0;
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// X
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if (XSEL)
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X = INPUTS;
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else
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{
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X = DSP->TEMP[(TRA + DSP->regs.MDEC_CT) & 0x7F];
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X <<= 8;
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X >>= 8;
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}
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// Y
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if (YSEL == 0)
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Y = FRC_REG;
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else if (YSEL == 1)
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Y = DSPData->COEF[COEF] >> 3; //COEF is 16 bits
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else if (YSEL == 2)
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Y = (Y_REG >> 11) & 0x1FFF;
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else if (YSEL == 3)
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Y = (Y_REG >> 4) & 0x0FFF;
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if (YRL)
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Y_REG = INPUTS;
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// Shifter
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// There's a 1-step delay at the output of the X*Y + B adder. So we use the ACC value from the previous step.
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if (SHIFT == 0)
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{
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SHIFTED = ACC >> 2; // 26 bits -> 24 bits
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if (SHIFTED > 0x0007FFFF)
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SHIFTED = 0x0007FFFF;
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if (SHIFTED < (-0x00080000))
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SHIFTED = -0x00080000;
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}
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else if (SHIFT == 1)
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{
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SHIFTED = ACC >> 1; // 26 bits -> 24 bits and x2 scale
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if (SHIFTED > 0x0007FFFF)
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SHIFTED = 0x0007FFFF;
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if (SHIFTED < (-0x00080000))
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SHIFTED = -0x00080000;
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}
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else if (SHIFT == 2)
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{
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SHIFTED = ACC >> 1;
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SHIFTED <<= 8;
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SHIFTED >>= 8;
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}
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else if (SHIFT == 3)
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{
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SHIFTED = ACC >> 2;
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SHIFTED <<= 8;
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SHIFTED >>= 8;
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}
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// ACCUM
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Y <<= 19;
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Y >>= 19;
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s64 v = ((s64)X * (s64)Y) >> 10; // magic value from dynarec. 1 sign bit + 24-1 bits + 13-1 bits -> 26 bits?
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v <<= 6; // 26 bits only
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v >>= 6;
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ACC = v + B;
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ACC <<= 6; // 26 bits only
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ACC >>= 6;
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if (TWT)
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DSP->TEMP[(TWA + DSP->regs.MDEC_CT) & 0x7F] = SHIFTED;
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if (FRCL)
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{
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if (SHIFT == 3)
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FRC_REG = SHIFTED & 0x0FFF;
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else
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FRC_REG = (SHIFTED >> 11) & 0x1FFF;
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}
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if ((MRD || MWT) && (step & 1))
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{
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ADDR = DSPData->MADRS[MASA];
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if (ADREB)
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ADDR += ADRS_REG & 0x0FFF;
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if (NXADR)
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ADDR++;
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if (!TABLE)
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ADDR += DSP->regs.MDEC_CT;
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if (!TABLE)
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ADDR &= DSP->RBL; // RBL is ring buffer length - 1
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else
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ADDR &= 0xFFFF;
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// ADDR <<= 1;
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// ADDR += DSP->RBP << 13;
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// MEMVAL = DSP->AICARAM[ADDR >> 1];
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ADDR <<= 1; // Word -> byte address
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ADDR += DSP->RBP; // RBP is already a byte address
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if (MRD) // memory only allowed on odd. DoA inserts NOPs on even
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{
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if (NOFL)
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||||
MEMVAL[(step + 2) & 3] = (*(s16 *)&aica_ram[ADDR]) << 8;
|
||||
else
|
||||
MEMVAL[(step + 2) & 3] = UNPACK(*(u16 *)&aica_ram[ADDR]);
|
||||
}
|
||||
if (MWT)
|
||||
{
|
||||
// FIXME We should wait for the next step to copy stuff to SRAM (same as read)
|
||||
if (NOFL)
|
||||
*(s16 *)&aica_ram[ADDR] = SHIFTED >> 8;
|
||||
else
|
||||
*(u16 *)&aica_ram[ADDR] = PACK(SHIFTED);
|
||||
}
|
||||
}
|
||||
|
||||
if (ADRL)
|
||||
{
|
||||
if (SHIFT == 3)
|
||||
ADRS_REG = (SHIFTED >> 12) & 0xFFF;
|
||||
else
|
||||
ADRS_REG = (INPUTS >> 16);
|
||||
}
|
||||
|
||||
if (EWT)
|
||||
// 4 ????
|
||||
DSPData->EFREG[EWA] += SHIFTED >> 4; // dynarec uses = instead of +=
|
||||
|
||||
}
|
||||
--DSP->regs.MDEC_CT;
|
||||
if (dsp.regs.MDEC_CT == 0)
|
||||
dsp.regs.MDEC_CT = dsp.RBL + 1; // RBL is ring buffer length - 1
|
||||
|
||||
// memset(DSP->MIXS, 0, sizeof(DSP->MIXS));
|
||||
// if(f)
|
||||
// fclose(f);
|
||||
}
|
||||
|
||||
void AICADSP_Start(struct dsp_t *DSP)
|
||||
{
|
||||
dsp.Stopped = 1;
|
||||
for (int i = 127; i >= 0; --i)
|
||||
{
|
||||
u32 *IPtr = DSPData->MPRO + i * 4;
|
||||
|
||||
if (IPtr[0] != 0 || IPtr[1] != 0 || IPtr[2 ]!= 0 || IPtr[3] != 0)
|
||||
{
|
||||
DSP->Stopped = 0;
|
||||
//printf("DSP: starting %d steps\n", i + 1);
|
||||
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void dsp_init()
|
||||
{
|
||||
AICADSP_Init(&dsp);
|
||||
AICADSP_Start(&dsp);
|
||||
}
|
||||
|
||||
void dsp_term()
|
||||
{
|
||||
dsp.Stopped = 1;
|
||||
}
|
||||
|
||||
void dsp_step()
|
||||
{
|
||||
AICADSP_Step(&dsp);
|
||||
}
|
||||
|
||||
void dsp_writenmem(u32 addr)
|
||||
{
|
||||
if (addr >= 0x3400 && addr < 0x3C00)
|
||||
{
|
||||
AICADSP_Start(&dsp);
|
||||
}
|
||||
else if (addr >= 0x4000 && addr < 0x4400)
|
||||
{
|
||||
// TODO proper sharing of memory with sh4 through DSPData
|
||||
memset(dsp.TEMP, 0, sizeof(dsp.TEMP));
|
||||
}
|
||||
else if (addr >= 0x4400 && addr < 0x4500)
|
||||
{
|
||||
// TODO proper sharing of memory with sh4 through DSPData
|
||||
memset(dsp.MEMS, 0, sizeof(dsp.MEMS));
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
#include "sgc_if.h"
|
||||
#include "sgc_if.h"
|
||||
#include "dsp.h"
|
||||
#include "aica_mem.h"
|
||||
#include "hw/aica/aica_if.h"
|
||||
|
|
@ -1359,8 +1359,16 @@ void AICA_Sample()
|
|||
{
|
||||
VOLPAN(EXTS0L,dsp_out_vol[16].EFSDL,dsp_out_vol[16].EFPAN,mixl,mixr);
|
||||
VOLPAN(EXTS0R,dsp_out_vol[17].EFSDL,dsp_out_vol[17].EFPAN,mixl,mixr);
|
||||
|
||||
DSPData->EXTS[0] = EXTS0L;
|
||||
DSPData->EXTS[1] = EXTS0R;
|
||||
}
|
||||
if (settings.aica.DSPEnabled)
|
||||
else
|
||||
{
|
||||
DSPData->EXTS[0] = 0;
|
||||
DSPData->EXTS[1] = 0;
|
||||
}
|
||||
//if (settings.aica.DSPEnabled)
|
||||
{
|
||||
dsp_step();
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue