fix all known div32 issues
support libretro naomi and aw savestates
This commit is contained in:
Flyinghead
parent
0fd51fb52a
commit
8740f22c0a
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@ -907,10 +907,14 @@ static bool dec_generic(u32 op)
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{
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verify(!state.cpu.is_delayslot);
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//div32s
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Emit(shop_xor, mk_reg(reg_sr_T), mk_reg(div_som_reg3), mk_reg(div_som_reg2)); // get quotient sign
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Emit(shop_and, mk_reg(reg_sr_T), mk_reg(reg_sr_T), mk_imm(1 << 31)); // isolate sign bit
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Emit(shop_div32s, mk_reg(div_som_reg1), mk_reg(div_som_reg1), mk_reg(div_som_reg2), 0, mk_reg(div_som_reg3), mk_reg(div_som_reg3));
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Emit(shop_and, mk_reg(reg_sr_T), mk_reg(div_som_reg1), mk_imm((1 << 31) | 1)); // set lsb and sign of quotient in T
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Emit(shop_and, mk_reg(reg_temp), mk_reg(div_som_reg1), mk_imm(1)); // set quotient lsb in temp reg
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Emit(shop_sar, mk_reg(div_som_reg1), mk_reg(div_som_reg1), mk_imm(1)); // shift quotient right
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Emit(shop_or, mk_reg(reg_sr_T), mk_reg(reg_sr_T), mk_reg(reg_temp)); // store quotient lsb in T
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Emit(shop_div32p2, mk_reg(div_som_reg3), mk_reg(div_som_reg3), mk_reg(div_som_reg2), 0, mk_reg(reg_sr_T));
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@ -922,29 +926,22 @@ static bool dec_generic(u32 op)
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}
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else
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{
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//sr.Q=r[n]>>31;
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//sr.M=r[m]>>31;
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//sr.T=sr.M^sr.Q;
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//This is nasty because there isn't a temp reg ..
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//VERY NASTY
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//Clear Q & M
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Emit(shop_and,mk_reg(reg_sr_status),mk_reg(reg_sr_status),mk_imm(~((1<<8)|(1<<9))));
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Emit(shop_and, mk_reg(reg_sr_status), mk_reg(reg_sr_status), mk_imm(~((1 << 8) | (1 << 9))));
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//sr.Q=r[n]>>31;
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Emit(shop_sar,mk_reg(reg_sr_T),rs1,mk_imm(31));
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Emit(shop_and,mk_reg(reg_sr_T),mk_reg(reg_sr_T),mk_imm(1<<8));
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Emit(shop_or,mk_reg(reg_sr_status),mk_reg(reg_sr_status),mk_reg(reg_sr_T));
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Emit(shop_sar, mk_reg(reg_sr_T),rs1,mk_imm(31));
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Emit(shop_and, mk_reg(reg_sr_T), mk_reg(reg_sr_T), mk_imm(1 << 8));
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Emit(shop_or, mk_reg(reg_sr_status), mk_reg(reg_sr_status), mk_reg(reg_sr_T));
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//sr.M=r[m]>>31;
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Emit(shop_sar,mk_reg(reg_sr_T),rs2,mk_imm(31));
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Emit(shop_and,mk_reg(reg_sr_T),mk_reg(reg_sr_T),mk_imm(1<<9));
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Emit(shop_or,mk_reg(reg_sr_status),mk_reg(reg_sr_status),mk_reg(reg_sr_T));
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Emit(shop_sar, mk_reg(reg_sr_T), rs2, mk_imm(31));
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Emit(shop_and, mk_reg(reg_sr_T), mk_reg(reg_sr_T), mk_imm(1 << 9));
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Emit(shop_or, mk_reg(reg_sr_status), mk_reg(reg_sr_status), mk_reg(reg_sr_T));
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//sr.T=sr.M^sr.Q;
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Emit(shop_xor,mk_reg(reg_sr_T),rs1,rs2);
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Emit(shop_shr,mk_reg(reg_sr_T),mk_reg(reg_sr_T),mk_imm(31));
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Emit(shop_xor, mk_reg(reg_sr_T), rs1, rs2);
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Emit(shop_shr, mk_reg(reg_sr_T), mk_reg(reg_sr_T), mk_imm(31));
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}
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}
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}
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@ -609,28 +609,36 @@ shil_opc_end()
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shil_opc(div32s)
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shil_canonical
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(
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u64,f1,(u32 r1, u32 r2, s32 r3),
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u64,f1,(u32 r1, s32 r2, s32 r3),
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s64 dividend = ((s64)r3 << 32) | r1;
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bool negative;
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if (dividend < 0)
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if ((r3 ^ r2) & 0x80000000)
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{
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// 1's complement -> 2's complement
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dividend++;
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if (dividend < 0)
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dividend++;
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negative = true;
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}
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else
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{
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negative = false;
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}
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s32 quo = dividend / r2;
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s32 rem = dividend % r2;
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s32 quo = (s32)(dividend / r2);
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s32 rem = dividend - quo * r2;
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// 2's complement -> 1's complement
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if (negative)
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{
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if (quo <= 0)
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quo--;
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if (rem <= 0)
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if (rem < 0 || (rem == 0 && r2 > 0))
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rem--;
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quo--;
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}
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else
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{
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// edge case
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if (rem == 0 && dividend < 0 && !(quo & 1))
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{
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quo--;
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rem += r2;
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}
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}
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u64 rv;
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@ -655,19 +663,17 @@ shil_opc(div32p2)
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shil_canonical
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(
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u32,f1,(s32 a,s32 b,u32 T),
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a += b * (((T >> 31) ^ ~T) & 1) * (2 * (T & 1) - 1);
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// This is equivalent to this:
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// (the sign of the quotient is stored in bit 31 of T)
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// if (quo >= 0)
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// {
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// if (!T)
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// rem -= divisor;
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// }
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// else
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// {
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// if (T)
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// rem += divisor;
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// }
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// the sign of the quotient is stored in bit 31 of T
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if (!(T & 0x80000000))
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{
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if (!(T & 1))
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a -= b;
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}
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else
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{
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if (T & 1)
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a += b;
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}
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return a;
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)
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@ -239,6 +239,9 @@ static u32* Sh4_int_GetRegisterPtr(Sh4RegType reg)
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case reg_pc_dyn:
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return &Sh4cntx.jdyn;
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case reg_temp:
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return &Sh4cntx.temp_reg;
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default:
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ERROR_LOG(SH4, "Unknown register ID %d", reg);
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die("Invalid reg");
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@ -88,6 +88,7 @@ enum Sh4RegType
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reg_fpscr,
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reg_pc_dyn, //Write only, for dynarec only (dynamic block exit address)
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reg_temp,
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sh4_reg_count,
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@ -286,6 +287,7 @@ struct Sh4Context
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u32 interrupt_pend;
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u32 exception_pc;
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u32 temp_reg;
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};
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u64 raw[64-8];
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};
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@ -22,6 +22,7 @@
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#include "hw/sh4/sh4_if.h"
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#include "hw/pvr/Renderer_if.h"
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#include "hw/pvr/spg.h"
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#include "hw/aica/aica_if.h"
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#include "hw/aica/dsp.h"
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#include "imgread/common.h"
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#include "rend/gui.h"
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@ -155,41 +156,6 @@ static void LoadSpecialSettings()
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settings.rend.TranslucentPolygonDepthMask = 1;
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tr_poly_depth_mask_game = true;
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}
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// Demolition Racer
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if (!strncmp("T15112N", prod_id, 7)
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// Ducati World - Racing Challenge (NTSC)
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|| !strncmp("T-8113N", prod_id, 7)
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// Ducati World (PAL)
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|| !strncmp("T-8121D-50", prod_id, 10)
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// Aqua GT
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|| !strncmp("T40509D 50", prod_id, 10)
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// Rayman 2 (NTSC)
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|| !strncmp("17707N", prod_id, 6)
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// Rayman 2 (PAL)
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|| !strncmp("17707D", prod_id, 6)
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// Elysion
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|| !strncmp("T20116M", prod_id, 7)
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// Silent Scope (NTSC)
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|| !strncmp("T9507N", prod_id, 6)
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// Silent Scope (PAL)
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|| !strncmp("T9505D", prod_id, 6)
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// Power Stone (US)
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|| !strncmp("T1201N", prod_id, 6)
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// Power Stone (JP)
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|| !strncmp("T1201M", prod_id, 6)
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// Power Stone (PAL)
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|| !strncmp("T36801D 50", prod_id, 10)
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// Metropolis Street Racer (NTSC)
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|| !strncmp("MK-51012", prod_id, 8)
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// Metropolis Street Racer (PAL)
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|| !strncmp("MK-5102250", prod_id, 10)
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// Donald Duck Goin' Quackers
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|| !strncmp("T17714D50", prod_id, 9))
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{
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INFO_LOG(BOOT, "Enabling Dynarec safe mode for game %s", prod_id);
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settings.dynarec.safemode = 1;
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safemode_game = true;
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}
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// NHL 2K2
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if (!strncmp("MK-51182", prod_id, 8))
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{
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@ -307,16 +273,6 @@ static void LoadSpecialSettings()
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else if (settings.platform.system == DC_PLATFORM_NAOMI || settings.platform.system == DC_PLATFORM_ATOMISWAVE)
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{
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NOTICE_LOG(BOOT, "Game ID is [%s]", naomi_game_id);
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if (!strcmp("METAL SLUG 6", naomi_game_id)
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|| !strcmp("WAVE RUNNER GP", naomi_game_id)
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|| !strcmp("STREET FIGHTER ZERO3 UPPER", naomi_game_id)
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|| !strcmp("ALIEN FRONT", naomi_game_id))
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{
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INFO_LOG(BOOT, "Enabling Dynarec safe mode for game %s", naomi_game_id);
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settings.dynarec.safemode = 1;
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safemode_game = true;
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}
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if (!strcmp("SAMURAI SPIRITS 6", naomi_game_id))
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{
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INFO_LOG(BOOT, "Enabling Extra depth scaling for game %s", naomi_game_id);
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@ -417,7 +373,8 @@ static void LoadSpecialSettings()
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INFO_LOG(BOOT, "Enabling specific JVS setup for game %s", naomi_game_id);
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settings.input.JammaSetup = JVS::DogWalking;
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}
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else if (!strcmp(" TOUCH DE UNOH -------------", naomi_game_id))
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else if (!strcmp(" TOUCH DE UNOH -------------", naomi_game_id)
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|| !strcmp("POKASUKA GHOST (JAPANESE)", naomi_game_id))
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{
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INFO_LOG(BOOT, "Enabling specific JVS setup for game %s", naomi_game_id);
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settings.input.JammaSetup = JVS::TouchDeUno;
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@ -819,12 +776,12 @@ void InitSettings()
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settings.network.server = "";
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#if SUPPORT_DISPMANX
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settings.dispmanx.Width = 640;
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settings.dispmanx.Height = 480;
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settings.dispmanx.Width = 0;
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settings.dispmanx.Height = 0;
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settings.dispmanx.Keep_Aspect = true;
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#endif
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#if defined(__ANDROID__) || defined(TARGET_PANDORA)
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#if HOST_CPU == CPU_ARM
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settings.aica.BufferSize = 5644; // 128 ms
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#else
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settings.aica.BufferSize = 2822; // 64 ms
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@ -571,19 +571,31 @@ static bool dc_unserialize_libretro(void **data, unsigned int *total_size)
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REICAST_US(SB_FFST_rc);
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REICAST_US(SB_FFST);
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REICAST_US(i); //LIBRETRO_S(sys_nvmem_sram.size);
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verify(i == 0);
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REICAST_US(i); //LIBRETRO_S(sys_nvmem_sram.mask);
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//LIBRETRO_SA(sys_nvmem_sram.data,sys_nvmem_sram.size);
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REICAST_US(sys_nvmem->size);
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REICAST_US(sys_nvmem->mask);
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if (settings.platform.system == DC_PLATFORM_DREAMCAST)
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REICAST_US(static_cast<DCFlashChip*>(sys_nvmem)->state);
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if (settings.platform.system == DC_PLATFORM_NAOMI)
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{
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REICAST_US(sys_nvmem->size); // Naomi
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REICAST_US(sys_nvmem->mask);
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REICAST_USA(sys_nvmem->data, sys_nvmem->size);
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}
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else
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// FIXME
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die("Naomi/Atomiswave libretro savestates are not supported");
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REICAST_USA(sys_nvmem->data, sys_nvmem->size);
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{
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REICAST_US(i);
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REICAST_US(i);
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}
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if (settings.platform.system == DC_PLATFORM_DREAMCAST)
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{
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REICAST_US(sys_nvmem->size);
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REICAST_US(sys_nvmem->mask);
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REICAST_US(static_cast<DCFlashChip*>(sys_nvmem)->state);
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REICAST_USA(sys_nvmem->data, sys_nvmem->size);
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}
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else
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{
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REICAST_US(i);
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REICAST_US(i);
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REICAST_US(i);
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}
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REICAST_US(GD_HardwareInfo);
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@ -0,0 +1,196 @@
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#include "gtest/gtest.h"
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#include "types.h"
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#include "hw/mem/_vmem.h"
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#include "emulator.h"
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#include "hw/sh4/sh4_core.h"
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#include "hw/sh4/dyna/shil.h"
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#define SHIL_MODE 2
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#include "hw/sh4/dyna/shil_canonical.h"
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void div32s_slow(u32& r1, u32 r2, u32& r3)
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{
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sr.Q = r3 >> 31;
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sr.M = r2 >> 31;
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sr.T = sr.Q ^ sr.M;
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for (int i = 0; i < 32; i++)
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{
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u64 rv = shil_opcl_rocl::f1::impl(r1, sr.T);
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r1 = (u32)rv;
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sr.T = rv >> 32;
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// DIV1
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unsigned char old_q = sr.Q;
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sr.Q = (u8)((0x80000000 & r3) !=0);
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r3 <<= 1;
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r3 |= (unsigned long)sr.T;
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u32 tmp0 = r3;
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r3 += (2 * (old_q ^ sr.M) - 1) * r2;
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sr.Q ^= old_q ^ (sr.M ? r3 > tmp0 : r3 >= tmp0);
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sr.T = (sr.Q == sr.M);
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}
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}
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void div32s_fast(u32& r1, u32 r2, u32& r3)
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{
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sr.T = (r3 ^ r2) & 0x80000000;
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u64 rv = shil_opcl_div32s::f1::impl(r1, r2, r3);
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r1 = (u32)rv;
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r3 = rv >> 32;
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sr.T |= r1 & 1;
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r1 = (s32)r1 >> 1;
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r3 = shil_opcl_div32p2::f1::impl(r3, r2, sr.T);
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sr.T &= 1;
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}
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void div32u_fast(u32& r1, u32 r2, u32& r3)
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{
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u64 rv = shil_opcl_div32u::f1::impl(r1, r2, r3);
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r1 = (u32)rv;
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r3 = rv >> 32;
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sr.T = r1 & 1;
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r1 = r1 >> 1;
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r3 = shil_opcl_div32p2::f1::impl(r3, r2, sr.T);
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}
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void div32u_slow(u32& r1, u32 r2, u32& r3)
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{
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sr.Q = 0;
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sr.M = 0;
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sr.T = 0;
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for (int i = 0; i < 32; i++)
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{
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u64 rv = shil_opcl_rocl::f1::impl(r1, sr.T);
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r1 = (u32)rv;
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sr.T = rv >> 32;
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// DIV1
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unsigned char old_q = sr.Q;
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sr.Q = (u8)((0x80000000 & r3) !=0);
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r3 <<= 1;
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r3 |= (unsigned long)sr.T;
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u32 tmp0 = r3;
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r3 += (2 * (old_q ^ sr.M) - 1) * r2;
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sr.Q ^= old_q ^ (sr.M ? r3 > tmp0 : r3 >= tmp0);
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sr.T = (sr.Q == sr.M);
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}
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}
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class Div32Test : public ::testing::Test {
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protected:
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void SetUp() override {
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if (!_vmem_reserve())
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die("_vmem_reserve failed");
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dc_init();
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dc_reset(true);
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}
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void div32s(u32 n1, u32 n2, u32 n3)
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{
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const long long int dividend = (long long)n3 << 32 | n1;
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//printf("%lld / %d = ", dividend, n2);
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int r1s = n1;
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int r2 = n2;
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int r3s = n3;
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int r1f = r1s;
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int r3f = r3s;
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div32s_slow((u32&)r1s, r2, (u32&)r3s);
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div32s_fast((u32&)r1f, r2, (u32&)r3f);
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//printf("%d %% %d\n", (r1s << 1) | sr.T, r3s);
|
||||
ASSERT_EQ(r1s, r1f);
|
||||
ASSERT_EQ(r3s, r3f);
|
||||
}
|
||||
|
||||
void div32u(u32 n1, u32 n2, u32 n3)
|
||||
{
|
||||
const long long int dividend = (long long)n3 << 32 | n1;
|
||||
//printf("%lld / %d = ", dividend, n2);
|
||||
int r1s = n1;
|
||||
int r2 = n2;
|
||||
int r3s = n3;
|
||||
int r1f = r1s;
|
||||
int r3f = r3s;
|
||||
div32u_slow((u32&)r1s, r2, (u32&)r3s);
|
||||
div32u_fast((u32&)r1f, r2, (u32&)r3f);
|
||||
//printf("%d %% %d\n", (r1s << 1) | sr.T, r3s);
|
||||
ASSERT_EQ(r3s, r3f);
|
||||
}
|
||||
};
|
||||
|
||||
TEST_F(Div32Test, Div32sTest)
|
||||
{
|
||||
div32s(0, 1, 0);
|
||||
div32s(1, 1, 0);
|
||||
div32s(2, 1, 0);
|
||||
div32s(4, 2, 0);
|
||||
div32s(5, 2, 0);
|
||||
|
||||
div32s(1000, 100, 0);
|
||||
div32s(1001, 100, 0);
|
||||
div32s(1099, 100, 0);
|
||||
div32s(1100, 100, 0);
|
||||
|
||||
div32s(37, 5, 0);
|
||||
div32s(-37, 5, -1);
|
||||
div32s(-37, -5, -1);
|
||||
div32s(37, -5, 0);
|
||||
|
||||
div32s(42, 5, 0);
|
||||
div32s(42, -5, 0);
|
||||
div32s(-42, 5, -1);
|
||||
div32s(-42, -5, -1);
|
||||
|
||||
div32s(5, 7, 0);
|
||||
div32s(5, -7, 0);
|
||||
div32s(-5, 7, -1);
|
||||
div32s(-5, -7, -1);
|
||||
|
||||
div32s(-1846, -1643, -1);
|
||||
div32s(-496138, -1042, -1);
|
||||
div32s(-416263, -1037, -1);
|
||||
div32s(-270831, -13276, -1);
|
||||
div32s(-3338802, -7266, -1);
|
||||
div32s(-3106, -354865, -1);
|
||||
div32s(-4446, -4095, -1);
|
||||
|
||||
div32s(-64, -8, -1);
|
||||
div32s(-72, -8, -1);
|
||||
|
||||
div32s(217781009, -45, 0);
|
||||
div32s(1858552, -8, 0);
|
||||
div32s(64, -8, 0);
|
||||
div32s(-64, 8, -1);
|
||||
div32s(-9415081, 130765, -1);
|
||||
div32s(-3639715, 78, -1);
|
||||
div32s(-11361399, 107183, -1);
|
||||
}
|
||||
|
||||
TEST_F(Div32Test, Div32uTest)
|
||||
{
|
||||
div32u(0, 1, 0);
|
||||
div32u(1, 1, 0);
|
||||
div32u(2, 1, 0);
|
||||
div32u(4, 2, 0);
|
||||
div32u(5, 2, 0);
|
||||
|
||||
div32u(1000, 100, 0);
|
||||
div32u(1001, 100, 0);
|
||||
div32u(1099, 100, 0);
|
||||
div32u(1100, 100, 0);
|
||||
|
||||
div32u(1964671145, 123383161, 0);
|
||||
div32u(1867228769, 653467280, 0);
|
||||
div32u(1523687288, 32181601, 0);
|
||||
|
||||
div32u(3499805483, 1401792939, 29611);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue