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sh4 interp: add IsFloatingPoint() to op desc. Add delay slot 0 hack 

Add UsesFPU flag to floating point ops. Use flag instead of specific
test cases in op handlers.
Adjust thrown exception in delay slot (slot illegal exception and slot
fpu disable)
Re-add delay slot 0 hack (Looney Tunes Space Race)
This commit is contained in:
Flyinghead 2019-03-20 13:45:35 +01:00
parent d0f65b19d3
commit 8564f497d4
6 changed files with 64 additions and 140 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
core/hw/sh4/interpr/sh4_interpreter.cpp
View File

@ -35,7 +35,7 @@ static s32 l;
static void ExecuteOpcode(u16 op)
{
if ((op & 0xF000) == 0xF000 && op != 0xFFFD && sr.FD == 1)
if (sr.FD == 1 && OpDesc[op]->IsFloatingPoint())
RaiseFPUDisableException();
OpPtr[op](op);
l -= CPU_RATIO;
@ -168,13 +168,16 @@ void ExecuteDelayslot()
next_pc += 2;
u32 op = IReadMem16(addr);
ExecuteOpcode(op);
if (op != 0) // Looney Tunes: Space Race hack
ExecuteOpcode(op);
#if !defined(NO_MMU)
}
catch (SH4ThrownException& ex) {
ex.epc -= 2;
if (ex.callVect == 0x800) // FPU disable exception
ex.callVect = 0x820; // Slot FPU disable exception
if (ex.expEvn == 0x800) // FPU disable exception
ex.expEvn = 0x820; // Slot FPU disable exception
else if (ex.expEvn == 0x180) // Illegal instruction exception
ex.expEvn = 0x1A0; // Slot illegal instruction exception
//printf("Delay slot exception\n");
throw ex;
}

97
core/hw/sh4/interpr/sh4_opcodes.cpp
View File

@ -80,7 +80,6 @@ void cpu_iWarn(u32 op, const char* info)
//stc GBR,<REG_N>
sh4op(i0000_nnnn_0001_0010)
{
//iNimp("stc GBR,<REG_N>");
u32 n = GetN(op);
r[n] = gbr;
}
@ -89,7 +88,6 @@ sh4op(i0000_nnnn_0001_0010)
//stc VBR,<REG_N>
sh4op(i0000_nnnn_0010_0010)
{
//iNimp("stc VBR,<REG_N> ");
u32 n = GetN(op);
r[n] = vbr;
}
@ -98,7 +96,6 @@ sh4op(i0000_nnnn_0010_0010)
//stc SSR,<REG_N>
sh4op(i0000_nnnn_0011_0010)
{
//iNimp("stc SSR,<REG_N>");
u32 n = GetN(op);
r[n] = ssr;
}
@ -106,7 +103,6 @@ sh4op(i0000_nnnn_0011_0010)
//stc SGR,<REG_N>
sh4op(i0000_nnnn_0011_1010)
{
//iNimp("stc SGR,<REG_N>");
u32 n = GetN(op);
r[n] = sgr;
}
@ -114,7 +110,6 @@ sh4op(i0000_nnnn_0011_1010)
//stc SPC,<REG_N>
sh4op(i0000_nnnn_0100_0010)
{
//iNimp("stc SPC,<REG_N> ");
u32 n = GetN(op);
r[n] = spc;
}
@ -123,7 +118,6 @@ sh4op(i0000_nnnn_0100_0010)
//stc RM_BANK,<REG_N>
sh4op(i0000_nnnn_1mmm_0010)
{
//iNimp(op,"stc R0_BANK,<REG_N>\n");
u32 n = GetN(op);
u32 m = GetM(op) & 0x7;
r[n] = r_bank[m];
@ -132,8 +126,6 @@ sh4op(i0000_nnnn_1mmm_0010)
//sts FPUL,<REG_N>
sh4op(i0000_nnnn_0101_1010)
{
if (sr.FD == 1)
RaiseFPUDisableException();
u32 n = GetN(op);
r[n] = fpul;
}
@ -165,7 +157,6 @@ sh4op(i0000_nnnn_0001_1010)
//sts PR,<REG_N>
sh4op(i0000_nnnn_0010_1010)
{
//iNimp("sts PR,<REG_N>");
u32 n = GetN(op);
r[n] = pr;
}
@ -184,7 +175,6 @@ sh4op(i0000_nnnn_mmmm_1100)
//mov.w @(R0,<REG_M>),<REG_N>
sh4op(i0000_nnnn_mmmm_1101)
{//ToDo : Check This [26/4/05]
//iNimp("mov.w @(R0,<REG_M>),<REG_N>");
u32 n = GetN(op);
u32 m = GetM(op);
ReadMemBOS16(r[n],r[0],r[m]);
@ -195,7 +185,6 @@ sh4op(i0000_nnnn_mmmm_1101)
//mov.l @(R0,<REG_M>),<REG_N>
sh4op(i0000_nnnn_mmmm_1110)
{
//iNimp("mov.l @(R0,<REG_M>),<REG_N>");
u32 n = GetN(op);
u32 m = GetM(op);
@ -205,7 +194,6 @@ sh4op(i0000_nnnn_mmmm_1110)
//mov.b <REG_M>,@(R0,<REG_N>)
sh4op(i0000_nnnn_mmmm_0100)
{
//iNimp("mov.b <REG_M>,@(R0,<REG_N>)");
u32 n = GetN(op);
u32 m = GetM(op);
@ -226,7 +214,6 @@ sh4op(i0000_nnnn_mmmm_0101)
//mov.l <REG_M>,@(R0,<REG_N>)
sh4op(i0000_nnnn_mmmm_0110)
{
//iNimp("mov.l <REG_M>,@(R0,<REG_N>)");
u32 n = GetN(op);
u32 m = GetM(op);
WriteMemBOU32(r[0], r[n], r[m]);
@ -276,7 +263,6 @@ sh4op(i0010_nnnn_mmmm_0010)
// mov.b <REG_M>,@-<REG_N>
sh4op(i0010_nnnn_mmmm_0100)
{
//iNimp("mov.b <REG_M>,@-<REG_N>");
u32 n = GetN(op);
u32 m = GetM(op);
@ -288,7 +274,6 @@ sh4op(i0010_nnnn_mmmm_0100)
//mov.w <REG_M>,@-<REG_N>
sh4op(i0010_nnnn_mmmm_0101)
{
//iNimp("mov.w <REG_M>,@-<REG_N>");
u32 n = GetN(op);
u32 m = GetM(op);
@ -313,8 +298,6 @@ sh4op(i0010_nnnn_mmmm_0110)
//sts.l FPUL,@-<REG_N>
sh4op(i0100_nnnn_0101_0010)
{
if (sr.FD == 1)
RaiseFPUDisableException();
u32 n = GetN(op);
u32 addr = r[n] - 4;
@ -367,7 +350,6 @@ sh4op(i0100_nnnn_1111_0010)
//stc.l GBR,@-<REG_N>
sh4op(i0100_nnnn_0001_0011)
{
//iNimp("stc.l GBR,@-<REG_N>");
u32 n = GetN(op);
u32 addr = r[n] - 4;
@ -379,7 +361,6 @@ sh4op(i0100_nnnn_0001_0011)
//stc.l VBR,@-<REG_N>
sh4op(i0100_nnnn_0010_0011)
{
//iNimp("stc.l VBR,@-<REG_N>");
u32 n = GetN(op);
u32 addr = r[n] - 4;
@ -391,7 +372,6 @@ sh4op(i0100_nnnn_0010_0011)
//stc.l SSR,@-<REG_N>
sh4op(i0100_nnnn_0011_0011)
{
//iNimp("stc.l SSR,@-<REG_N>");
u32 n = GetN(op);
u32 addr = r[n] - 4;
@ -401,7 +381,6 @@ sh4op(i0100_nnnn_0011_0011)
//stc.l SGR,@-<REG_N>
sh4op(i0100_nnnn_0011_0010)
{
//iNimp("stc.l SGR,@-<REG_N>");
u32 n = GetN(op);
u32 addr = r[n] - 4;
@ -413,7 +392,6 @@ sh4op(i0100_nnnn_0011_0010)
//stc.l SPC,@-<REG_N>
sh4op(i0100_nnnn_0100_0011)
{
//iNimp("stc.l SPC,@-<REG_N>");
u32 n = GetN(op);
u32 addr = r[n] - 4;
@ -424,7 +402,6 @@ sh4op(i0100_nnnn_0100_0011)
//stc RM_BANK,@-<REG_N>
sh4op(i0100_nnnn_1mmm_0011)
{
//iNimp("stc RM_BANK,@-<REG_N>");
u32 n = GetN(op);
u32 m = GetM(op) & 0x07;
@ -448,7 +425,6 @@ sh4op(i0100_nnnn_0000_0110)
//lds.l @<REG_N>+,MACL
sh4op(i0100_nnnn_0001_0110)
{
//iNimp("lds.l @<REG_N>+,MACL ");
u32 n = GetN(op);
ReadMemU32(mac.l,r[n]);
@ -469,8 +445,6 @@ sh4op(i0100_nnnn_0010_0110)
//lds.l @<REG_N>+,FPUL
sh4op(i0100_nnnn_0101_0110)
{
if (sr.FD == 1)
RaiseFPUDisableException();
u32 n = GetN(op);
ReadMemU32(fpul,r[n]);
@ -490,7 +464,6 @@ sh4op(i0100_nnnn_1111_0110)
//ldc.l @<REG_N>+,GBR
sh4op(i0100_nnnn_0001_0111)
{
//iNimp("ldc.l @<REG_N>+,GBR");
u32 n = GetN(op);
ReadMemU32(gbr,r[n]);
@ -501,7 +474,6 @@ sh4op(i0100_nnnn_0001_0111)
//ldc.l @<REG_N>+,VBR
sh4op(i0100_nnnn_0010_0111)
{
//iNimp("ldc.l @<REG_N>+,VBR");
u32 n = GetN(op);
ReadMemU32(vbr,r[n]);
@ -512,7 +484,6 @@ sh4op(i0100_nnnn_0010_0111)
//ldc.l @<REG_N>+,SSR
sh4op(i0100_nnnn_0011_0111)
{
//iNimp("ldc.l @<REG_N>+,SSR");
u32 n = GetN(op);
ReadMemU32(ssr,r[n]);
@ -522,7 +493,6 @@ sh4op(i0100_nnnn_0011_0111)
//ldc.l @<REG_N>+,SGR
sh4op(i0100_nnnn_0011_0110)
{
//iNimp("ldc.l @<REG_N>+,SGR");
u32 n = GetN(op);
ReadMemU32(sgr,r[n]);
@ -532,7 +502,6 @@ sh4op(i0100_nnnn_0011_0110)
//ldc.l @<REG_N>+,SPC
sh4op(i0100_nnnn_0100_0111)
{
//iNimp("ldc.l @<REG_N>+,SPC");
u32 n = GetN(op);
ReadMemU32(spc,r[n]);
@ -543,7 +512,6 @@ sh4op(i0100_nnnn_0100_0111)
//ldc.l @<REG_N>+,RM_BANK
sh4op(i0100_nnnn_1mmm_0111)
{
//iNimp("ldc.l @<REG_N>+,R0_BANK");
u32 n = GetN(op);
u32 m = GetM(op) & 7;
@ -578,8 +546,6 @@ sh4op(i0100_nnnn_0010_1010)
//lds <REG_N>,FPUL
sh4op(i0100_nnnn_0101_1010)
{
if (sr.FD == 1)
RaiseFPUDisableException();
u32 n = GetN(op);
fpul =r[n];
}
@ -608,7 +574,6 @@ sh4op(i0100_nnnn_0001_1110)
//ldc <REG_N>,VBR
sh4op(i0100_nnnn_0010_1110)
{
//iNimp("ldc <REG_N>,VBR");
u32 n = GetN(op);
vbr = r[n];
@ -618,7 +583,6 @@ sh4op(i0100_nnnn_0010_1110)
//ldc <REG_N>,SSR
sh4op(i0100_nnnn_0011_1110)
{
//iNimp("ldc <REG_N>,SSR");
u32 n = GetN(op);
ssr = r[n];
@ -627,7 +591,6 @@ sh4op(i0100_nnnn_0011_1110)
//ldc <REG_N>,SGR
sh4op(i0100_nnnn_0011_1010)
{
//iNimp("ldc <REG_N>,SGR");
u32 n = GetN(op);
sgr = r[n];
@ -636,7 +599,6 @@ sh4op(i0100_nnnn_0011_1010)
//ldc <REG_N>,SPC
sh4op(i0100_nnnn_0100_1110)
{
//iNimp("ldc <REG_N>,SPC");
u32 n = GetN(op);
spc = r[n];
@ -646,7 +608,6 @@ sh4op(i0100_nnnn_0100_1110)
//ldc <REG_N>,RM_BANK
sh4op(i0100_nnnn_1mmm_1110)
{
//iNimp(op, "ldc <REG_N>,RM_BANK");
u32 n = GetN(op);
u32 m = GetM(op) & 7;
@ -681,7 +642,6 @@ sh4op(i0110_nnnn_mmmm_0000)
//mov.w @<REG_M>,<REG_N>
sh4op(i0110_nnnn_mmmm_0001)
{
//iNimp("mov.w @<REG_M>,<REG_N>");
u32 n = GetN(op);
u32 m = GetM(op);
//r[n] = (u32)(s32)(s16)ReadMem16(r[m]);
@ -711,7 +671,6 @@ sh4op(i0110_nnnn_mmmm_0011)
//mov.b @<REG_M>+,<REG_N>
sh4op(i0110_nnnn_mmmm_0100)
{
//iNimp("mov.b @<REG_M>+,<REG_N>");
u32 n = GetN(op);
u32 m = GetM(op);
//r[n] = (u32)(s32)(s8)ReadMem8(r[m]);
@ -724,7 +683,6 @@ sh4op(i0110_nnnn_mmmm_0100)
//mov.w @<REG_M>+,<REG_N>
sh4op(i0110_nnnn_mmmm_0101)
{
//iNimp("mov.w @<REG_M>+,<REG_N>");
u32 n = GetN(op);
u32 m = GetM(op);
//r[n] = (u32)(s16)(u16)ReadMem16(r[m]);
@ -751,7 +709,6 @@ sh4op(i0110_nnnn_mmmm_0110)
// mov.b R0,@(<disp>,<REG_M>)
sh4op(i1000_0000_mmmm_iiii)
{
//iNimp("mov.b R0,@(<disp>,<REG_M>)");
u32 n = GetM(op);
u32 disp = GetImm4(op);
WriteMemBOU8(r[n],disp,r[0]);
@ -761,7 +718,6 @@ sh4op(i1000_0000_mmmm_iiii)
// mov.w R0,@(<disp>,<REG_M>)
sh4op(i1000_0001_mmmm_iiii)
{
//iNimp("mov.w R0,@(<disp>,<REG_M>)");
u32 disp = GetImm4(op);
u32 m = GetM(op);
WriteMemBOU16(r[m] , (disp << 1),r[0]);
@ -771,7 +727,6 @@ sh4op(i1000_0001_mmmm_iiii)
// mov.b @(<disp>,<REG_M>),R0
sh4op(i1000_0100_mmmm_iiii)
{
//iNimp("mov.b @(<disp>,<REG_M>),R0");
u32 disp = GetImm4(op);
u32 m = GetM(op);
//r[0] = (u32)(s8)ReadMem8(r[m] + disp);
@ -782,7 +737,6 @@ sh4op(i1000_0100_mmmm_iiii)
// mov.w @(<disp>,<REG_M>),R0
sh4op(i1000_0101_mmmm_iiii)
{
//iNimp("mov.w @(<disp>,<REG_M>),R0");
u32 disp = GetImm4(op);
u32 m = GetM(op);
//r[0] = (u32)(s16)ReadMem16(r[m] + (disp << 1));
@ -807,7 +761,6 @@ sh4op(i1001_nnnn_iiii_iiii)
// mov.b R0,@(<disp>,GBR)
sh4op(i1100_0000_iiii_iiii)
{
// iNimp(op, "mov.b R0,@(<disp>,GBR)");
u32 disp = GetImm8(op);
WriteMemBOU8(gbr, disp, r[0]);
}
@ -816,7 +769,6 @@ sh4op(i1100_0000_iiii_iiii)
// mov.w R0,@(<disp>,GBR)
sh4op(i1100_0001_iiii_iiii)
{
//iNimp("mov.w R0,@(<disp>,GBR)");
u32 disp = GetImm8(op);
//Write_Word(GBR+(disp<<1),R[0]);
WriteMemBOU16(gbr , (disp << 1), r[0]);
@ -826,7 +778,6 @@ sh4op(i1100_0001_iiii_iiii)
// mov.l R0,@(<disp>,GBR)
sh4op(i1100_0010_iiii_iiii)
{
// iNimp("mov.l R0,@(<disp>,GBR)");
u32 disp = (GetImm8(op));
//u32 source = (disp << 2) + gbr;
@ -836,7 +787,6 @@ sh4op(i1100_0010_iiii_iiii)
// mov.b @(<disp>,GBR),R0
sh4op(i1100_0100_iiii_iiii)
{
// iNimp(op, "mov.b @(<disp>,GBR),R0");
u32 disp = GetImm8(op);
//r[0] = (u32)(s8)ReadMem8(gbr+disp);
ReadMemBOS8(r[0],gbr,disp);
@ -846,7 +796,6 @@ sh4op(i1100_0100_iiii_iiii)
// mov.w @(<disp>,GBR),R0
sh4op(i1100_0101_iiii_iiii)
{
// iNimp(op, "mov.w @(<disp>,GBR),R0");
u32 disp = GetImm8(op);
//r[0] = (u32)(s16)ReadMem16(gbr+(disp<<1) );
ReadMemBOS16(r[0],gbr,(disp<<1));
@ -856,7 +805,6 @@ sh4op(i1100_0101_iiii_iiii)
// mov.l @(<disp>,GBR),R0
sh4op(i1100_0110_iiii_iiii)
{
// iNimp(op, "mov.l @(<disp>,GBR),R0");
u32 disp = GetImm8(op);
ReadMemBOU32(r[0],gbr,(disp<<2));
@ -903,7 +851,6 @@ sh4op(i0000_nnnn_1100_0011)
//clrmac
sh4op(i0000_0000_0010_1000)
{
//iNimp(op, "clrmac");
mac.full=0;
}
@ -940,10 +887,9 @@ sh4op(i0000_0000_0010_1011)
// The other bits—S, T, M, Q, FD, BL, and RB—after modification are used for delay slot
// instruction execution. The STC and STC.L SR instructions access all SR bits after modification.
sh4_sr_SetFull(ssr);
bool interrupt_pending = UpdateSR();
ExecuteDelayslot_RTE();
next_pc = newpc;
if (interrupt_pending)
if (UpdateSR())
{
UpdateINTC();
}
@ -1070,7 +1016,6 @@ sh4op(i0100_nnnn_0000_1011)
//sleep
sh4op(i0000_0000_0001_1011)
{
//iNimp("Sleep");
//just wait for an Interrupt
int i=0,s=1;
@ -1183,7 +1128,6 @@ sh4op(i0100_nnnn_0000_1001)
//shlr8 <REG_N>
sh4op(i0100_nnnn_0001_1001)
{
//iNimp("shlr8 <REG_N>");
u32 n = GetN(op);
r[n] >>= 8;
}
@ -1199,7 +1143,6 @@ sh4op(i0100_nnnn_0010_1001)
// and #<imm>,R0
sh4op(i1100_1001_iiii_iiii)
{//ToDo : Check This [26/4/05]
//iNimp("and #<imm>,R0");
u32 imm = GetImm8(op);
r[0] &= imm;
}
@ -1208,7 +1151,6 @@ sh4op(i1100_1001_iiii_iiii)
// xor #<imm>,R0
sh4op(i1100_1010_iiii_iiii)
{
//iNimp("xor #<imm>,R0");
u32 imm = GetImm8(op);
r[0] ^= imm;
}
@ -1217,7 +1159,6 @@ sh4op(i1100_1010_iiii_iiii)
// or #<imm>,R0
sh4op(i1100_1011_iiii_iiii)
{//ToDo : Check This [26/4/05]
//iNimp("or #<imm>,R0");
u32 imm = GetImm8(op);
r[0] |= imm;
}
@ -1390,7 +1331,6 @@ sh4op(i0100_nnnn_0001_0001)
//cmp/pl <REG_N>
sh4op(i0100_nnnn_0001_0101)
{
//iNimp("cmp/pl <REG_N>");
u32 n = GetN(op);
if ((s32)r[n] > 0)
sr.T = 1;
@ -1411,7 +1351,6 @@ sh4op(i1000_1000_iiii_iiii)
//cmp/eq <REG_M>,<REG_N>
sh4op(i0011_nnnn_mmmm_0000)
{
//iNimp("cmp/eq <REG_M>,<REG_N>");
u32 n = GetN(op);
u32 m = GetM(op);
@ -1435,7 +1374,6 @@ sh4op(i0011_nnnn_mmmm_0010)
//cmp/ge <REG_M>,<REG_N>
sh4op(i0011_nnnn_mmmm_0011)
{
//iNimp("cmp/ge <REG_M>,<REG_N>");
u32 n = GetN(op);
u32 m = GetM(op);
if ((s32)r[n] >= (s32)r[m])
@ -1459,7 +1397,6 @@ sh4op(i0011_nnnn_mmmm_0110)
//cmp/gt <REG_M>,<REG_N>
sh4op(i0011_nnnn_mmmm_0111)
{
//iNimp("cmp/gt <REG_M>,<REG_N>");
u32 n = GetN(op);
u32 m = GetM(op);
@ -1495,7 +1432,6 @@ sh4op(i0010_nnnn_mmmm_1100)
//tst #<imm>,R0
sh4op(i1100_1000_iiii_iiii)
{
//iNimp("tst #<imm>,R0");
u32 utmp1 = r[0] & GetImm8(op);
if (utmp1 == 0)
sr.T = 1;
@ -1518,7 +1454,7 @@ sh4op(i0010_nnnn_mmmm_1000)
//mulu.w <REG_M>,<REG_N>
sh4op(i0010_nnnn_mmmm_1110)
{
//iNimp("mulu.w <REG_M>,<REG_N>");//check ++
//check ++
u32 n = GetN(op);
u32 m = GetM(op);
mac.l=((u16)r[n])*
@ -1528,7 +1464,6 @@ sh4op(i0010_nnnn_mmmm_1110)
//muls.w <REG_M>,<REG_N>
sh4op(i0010_nnnn_mmmm_1111)
{
//iNimp("muls <REG_M>,<REG_N>");
u32 n = GetN(op);
u32 m = GetM(op);
@ -1537,7 +1472,6 @@ sh4op(i0010_nnnn_mmmm_1111)
//dmulu.l <REG_M>,<REG_N>
sh4op(i0011_nnnn_mmmm_0101)
{
//iNimp("dmulu.l <REG_M>,<REG_N>");
u32 n = GetN(op);
u32 m = GetM(op);
@ -1547,7 +1481,7 @@ sh4op(i0011_nnnn_mmmm_0101)
//dmuls.l <REG_M>,<REG_N>
sh4op(i0011_nnnn_mmmm_1101)
{
//iNimp("dmuls.l <REG_M>,<REG_N>");//check ++
//check ++
u32 n = GetN(op);
u32 m = GetM(op);
@ -1586,7 +1520,6 @@ sh4op(i0100_nnnn_mmmm_1111)
//mac.l @<REG_M>+,@<REG_N>+
sh4op(i0000_nnnn_mmmm_1111)
{
//iNimp("mac.l @<REG_M>+,@<REG_N>+");
u32 n = GetN(op);
u32 m = GetM(op);
s32 rm, rn;
@ -1723,7 +1656,6 @@ sh4op(i0011_nnnn_mmmm_1111)
{
//printf("WARN: addv <REG_M>,<REG_N> used, %04X\n",op);
//Retail game "Twinkle Star Sprites" "uses" this opcode.
//iNimp(op, "addv <REG_M>,<REG_N>");
u32 n = GetN(op);
u32 m = GetM(op);
s64 br=(s64)(s32)r[n]+(s64)(s32)r[m];
@ -1756,7 +1688,6 @@ sh4op(i0011_nnnn_mmmm_1111)
//subc <REG_M>,<REG_N>
sh4op(i0011_nnnn_mmmm_1010)
{//ToDo : Check This [26/4/05]
//iNimp(op,"subc <REG_M>,<REG_N>");
u32 n = GetN(op);
u32 m = GetM(op);
@ -1778,7 +1709,6 @@ sh4op(i0011_nnnn_mmmm_1011)
{
//printf("WARN: subv <REG_M>,<REG_N> used, %04X\n",op);
//Retail game "Twinkle Star Sprites" "uses" this opcode.
//iNimp(op, "subv <REG_M>,<REG_N>");
u32 n = GetN(op);
u32 m = GetM(op);
s64 br=(s64)(s32)r[n]-(s64)(s32)r[m];
@ -1821,7 +1751,6 @@ sh4op(i0100_nnnn_0001_0000)
//negc <REG_M>,<REG_N>
sh4op(i0110_nnnn_mmmm_1010)
{
//iNimp("negc <REG_M>,<REG_N>");
u32 n = GetN(op);
u32 m = GetM(op);
@ -1850,7 +1779,6 @@ sh4op(i0110_nnnn_mmmm_1011)
//not <REG_M>,<REG_N>
sh4op(i0110_nnnn_mmmm_0111)
{
//iNimp("not <REG_M>,<REG_N>");
u32 n = GetN(op);
u32 m = GetM(op);
@ -1887,7 +1815,6 @@ sh4op(i0100_nnnn_0000_0001)
//shar <REG_N>
sh4op(i0100_nnnn_0010_0001)
{//ToDo : Check This [26/4/05] x2
//iNimp("shar <REG_N>");
u32 n = GetN(op);
sr.T=r[n] & 1;
@ -1897,7 +1824,6 @@ sh4op(i0100_nnnn_0010_0001)
//shad <REG_M>,<REG_N>
sh4op(i0100_nnnn_mmmm_1100)
{
//iNimp(op,"shad <REG_M>,<REG_N>");
u32 n = GetN(op);
u32 m = GetM(op);
u32 sgn = r[m] & 0x80000000;
@ -1915,8 +1841,6 @@ sh4op(i0100_nnnn_mmmm_1100)
//shld <REG_M>,<REG_N>
sh4op(i0100_nnnn_mmmm_1101)
{
//iNimp("shld <REG_M>,<REG_N>");
u32 n = GetN(op);
u32 m = GetM(op);
u32 sgn = r[m] & 0x80000000;
@ -1935,7 +1859,6 @@ sh4op(i0100_nnnn_mmmm_1101)
//rotcl <REG_N>
sh4op(i0100_nnnn_0010_0100)
{
//iNimp("rotcl <REG_N>");
u32 n = GetN(op);
u32 t;
@ -1952,7 +1875,6 @@ sh4op(i0100_nnnn_0010_0100)
//rotl <REG_N>
sh4op(i0100_nnnn_0000_0100)
{
//iNimp("rotl <REG_N>");
u32 n = GetN(op);
sr.T=r[n]>>31;
@ -1965,7 +1887,6 @@ sh4op(i0100_nnnn_0000_0100)
//rotcr <REG_N>
sh4op(i0100_nnnn_0010_0101)
{
//iNimp("rotcr <REG_N>");
u32 n = GetN(op);
u32 t;
@ -1983,7 +1904,6 @@ sh4op(i0100_nnnn_0010_0101)
//rotr <REG_N>
sh4op(i0100_nnnn_0000_0101)
{
//iNimp("rotr <REG_N>");
u32 n = GetN(op);
sr.T = r[n] & 0x1;
r[n] >>= 1;
@ -1993,7 +1913,6 @@ sh4op(i0100_nnnn_0000_0101)
//swap.b <REG_M>,<REG_N>
sh4op(i0110_nnnn_mmmm_1000)
{
//iNimp("swap.b <REG_M>,<REG_N>");
u32 m = GetM(op);
u32 n = GetN(op);
@ -2116,7 +2035,6 @@ sh4op(i1100_1111_iiii_iiii)
//tas.b @<REG_N>
sh4op(i0100_nnnn_0001_1011)
{
//iNimp("tas.b @<REG_N>");
u32 n = GetN(op);
u8 val;
@ -2146,8 +2064,6 @@ sh4op(i0000_nnnn_0000_0010)//0002
//sts FPSCR,<REG_N>
sh4op(i0000_nnnn_0110_1010)
{
if (sr.FD == 1)
RaiseFPUDisableException();
u32 n = GetN(op);
r[n] = fpscr.full;
UpdateFPSCR();
@ -2156,8 +2072,6 @@ sh4op(i0000_nnnn_0110_1010)
//sts.l FPSCR,@-<REG_N>
sh4op(i0100_nnnn_0110_0010)
{
if (sr.FD == 1)
RaiseFPUDisableException();
u32 n = GetN(op);
WriteMemU32(r[n] - 4, fpscr.full);
r[n] -= 4;
@ -2174,8 +2088,6 @@ sh4op(i0100_nnnn_0000_0011)
//lds.l @<REG_N>+,FPSCR
sh4op(i0100_nnnn_0110_0110)
{
if (sr.FD == 1)
RaiseFPUDisableException();
u32 n = GetN(op);
ReadMemU32(fpscr.full,r[n]);
@ -2187,7 +2099,6 @@ sh4op(i0100_nnnn_0110_0110)
//ldc.l @<REG_N>+,SR
sh4op(i0100_nnnn_0000_0111)
{
//iNimp("ldc.l @<REG_N>+,SR");
u32 n = GetN(op);
u32 sr_t;
@ -2204,8 +2115,6 @@ sh4op(i0100_nnnn_0000_0111)
//lds <REG_N>,FPSCR
sh4op(i0100_nnnn_0110_1010)
{
if (sr.FD == 1)
RaiseFPUDisableException();
u32 n = GetN(op);
fpscr.full = r[n];
UpdateFPSCR();

2
core/hw/sh4/sh4_core.h
View File

@ -118,7 +118,7 @@ static INLINE void RaiseFPUDisableException()
throw ex;
}
#else
msgboxf("Can't raise exceptions yet", MBX_ICONERROR);
msgboxf("Full MMU support needed", MBX_ICONERROR);
#endif
}

3
core/hw/sh4/sh4_interpreter.h
View File

@ -22,6 +22,9 @@ enum OpcodeType
NO_GP = 512,
NO_SP = 1024,
UsesFPU = 2048, // Floating point op
FWritesFPSCR = UsesFPU | WritesFPSCR,
// Heh, not basic :P
ReadWritePC = ReadsPC|WritesPC, // Read and writes pc :P
WritesSRRWPC = WritesSR|ReadsPC|WritesPC,

87
core/hw/sh4/sh4_opcode_list.cpp
View File

@ -113,7 +113,7 @@ u64 dec_rz(...) { return 0; }
sh4_opcodelistentry missing_opcode = {0,iNotImplemented,0,0,ReadWritePC,"missing",0,0,CO,fix_none };
#define R_GP (NO_SP|NO_FP) //only general
#define R_FP (NO_SP|NO_FP) //only float
#define R_FP (NO_SP|NO_GP) //only float
#define R_SP (NO_GP|NO_FP) //only special
#define R_GSP (NO_FP) //general + special
#define R_GFP (NO_SP) //general + float
@ -222,8 +222,8 @@ sh4_opcodelistentry opcodes[]=
//Special register readm/writem/movs
//sts : @-rn
{0 ,i0100_nnnn_0101_0010 ,Mask_n ,0x4052 ,Normal ,"sts.l FPUL,@-<REG_N>" ,1,1,CO,rn_4 ,dec_STM(PRM_SREG)}, //sts.l FPUL,@-<REG_N>
{0 ,i0100_nnnn_0110_0010 ,Mask_n ,0x4062 ,Normal ,"sts.l FPSCR,@-<REG_N>" ,1,2,CO,rn_4 ,dec_STM(PRM_SREG)}, //sts.l FPSCR,@-<REG_N>
{0 ,i0100_nnnn_0101_0010 ,Mask_n ,0x4052 ,UsesFPU ,"sts.l FPUL,@-<REG_N>" ,1,1,CO,rn_4 ,dec_STM(PRM_SREG)}, //sts.l FPUL,@-<REG_N>
{0 ,i0100_nnnn_0110_0010 ,Mask_n ,0x4062 ,UsesFPU ,"sts.l FPSCR,@-<REG_N>" ,1,2,CO,rn_4 ,dec_STM(PRM_SREG)}, //sts.l FPSCR,@-<REG_N>
{0 ,i0100_nnnn_0000_0010 ,Mask_n ,0x4002 ,Normal ,"sts.l MACH,@-<REG_N>" ,1,3,CO,rn_4 ,dec_STM(PRM_SREG)}, //sts.l MACH,@-<REG_N>
{0 ,i0100_nnnn_0001_0010 ,Mask_n ,0x4012 ,Normal ,"sts.l MACL,@-<REG_N>" ,1,3,CO,rn_4 ,dec_STM(PRM_SREG)}, //sts.l MACL,@-<REG_N>
{0 ,i0100_nnnn_0010_0010 ,Mask_n ,0x4022 ,Normal ,"sts.l PR,@-<REG_N>" ,1,1,CO,rn_4 ,dec_STM(PRM_SREG)}, //sts.l PR,@-<REG_N>
@ -243,8 +243,8 @@ sh4_opcodelistentry opcodes[]=
{0 ,i0100_nnnn_0001_0110 ,Mask_n ,0x4016 ,Normal ,"lds.l @<REG_N>+,MAC" ,1,1,CO,fix_none ,dec_LDM(PRM_SREG)}, //lds.l @<REG_N>+,MACL
{0 ,i0100_nnnn_0010_0110 ,Mask_n ,0x4026 ,Normal ,"lds.l @<REG_N>+,PR" ,1,2,CO,fix_none ,dec_LDM(PRM_SREG)}, //lds.l @<REG_N>+,PR
{0 ,i0100_nnnn_0011_0110 ,Mask_n ,0x4036 ,Normal ,"ldc.l @<REG_N>+,SGR" ,3,3,CO,fix_none ,dec_LDM(PRM_SREG)}, //lds.l @<REG_N>+,SGR
{0 ,i0100_nnnn_0101_0110 ,Mask_n ,0x4056 ,Normal ,"lds.l @<REG_N>+,FPUL" ,1,1,CO,fix_none ,dec_LDM(PRM_SREG)}, //lds.l @<REG_N>+,FPUL
{0 ,i0100_nnnn_0110_0110 ,Mask_n ,0x4066 ,WritesFPSCR ,"lds.l @<REG_N>+,FPSCR" ,1,1,CO,fix_none}, //lds.l @<REG_N>+,FPSCR
{0 ,i0100_nnnn_0101_0110 ,Mask_n ,0x4056 ,UsesFPU ,"lds.l @<REG_N>+,FPUL" ,1,1,CO,fix_none ,dec_LDM(PRM_SREG)}, //lds.l @<REG_N>+,FPUL
{0 ,i0100_nnnn_0110_0110 ,Mask_n ,0x4066 ,FWritesFPSCR ,"lds.l @<REG_N>+,FPSCR" ,1,1,CO,fix_none}, //lds.l @<REG_N>+,FPSCR
{0 ,i0100_nnnn_1111_0110 ,Mask_n ,0x40F6 ,Normal ,"ldc.l @<REG_N>+,DBR" ,1,3,CO,fix_none ,dec_LDM(PRM_SREG)}, //lds.l @<REG_N>+,DBR
//ldc : @rn+
@ -269,8 +269,8 @@ sh4_opcodelistentry opcodes[]=
{0 ,i0000_nnnn_0001_1010 ,Mask_n ,0x001A ,Normal ,"sts MACL,<REG_N>" ,1,3,CO,fix_none ,dec_ST(PRM_SREG)}, //sts MACL,<REG_N>
{0 ,i0000_nnnn_0010_1010 ,Mask_n ,0x002A ,Normal ,"sts PR,<REG_N>" ,2,2,CO,fix_none ,dec_ST(PRM_SREG)}, //sts PR,<REG_N>
{0 ,i0000_nnnn_0011_1010 ,Mask_n ,0x003A ,Normal ,"sts SGR,<REG_N>" ,3,3,CO,fix_none ,dec_ST(PRM_SREG)}, //sts SGR,<REG_N>
{0 ,i0000_nnnn_0101_1010 ,Mask_n ,0x005A ,Normal ,"sts FPUL,<REG_N>" ,1,3,LS,fix_none ,dec_ST(PRM_SREG)}, //sts FPUL,<REG_N>
{0 ,i0000_nnnn_0110_1010 ,Mask_n ,0x006A ,Normal ,"sts FPSCR,<REG_N>" ,1,3,CO,fix_none ,dec_ST(PRM_SREG)}, //sts FPSCR,<REG_N>
{0 ,i0000_nnnn_0101_1010 ,Mask_n ,0x005A ,UsesFPU ,"sts FPUL,<REG_N>" ,1,3,LS,fix_none ,dec_ST(PRM_SREG)}, //sts FPUL,<REG_N>
{0 ,i0000_nnnn_0110_1010 ,Mask_n ,0x006A ,UsesFPU ,"sts FPSCR,<REG_N>" ,1,3,CO,fix_none ,dec_ST(PRM_SREG)}, //sts FPSCR,<REG_N>
{0 ,i0000_nnnn_1111_1010 ,Mask_n ,0x00FA ,Normal ,"sts DBR,<REG_N>" ,1,2,CO,fix_none ,dec_ST(PRM_SREG)}, //sts DBR,<REG_N>
//lds : rn
@ -278,8 +278,8 @@ sh4_opcodelistentry opcodes[]=
{0 ,i0100_nnnn_0001_1010 ,Mask_n ,0x401A ,Normal ,"lds <REG_N>,MAC" ,1,3,CO,fix_none ,dec_LD(PRM_SREG)}, //lds <REG_N>,MACL
{0 ,i0100_nnnn_0010_1010 ,Mask_n ,0x402A ,Normal ,"lds <REG_N>,PR" ,1,2,CO,fix_none ,dec_LD(PRM_SREG)}, //lds <REG_N>,PR
{0 ,i0100_nnnn_0011_1010 ,Mask_n ,0x403A ,Normal ,"ldc <REG_N>,SGR" ,3,3,CO,fix_none ,dec_LD(PRM_SREG)}, //lds <REG_N>,SGR
{0 ,i0100_nnnn_0101_1010 ,Mask_n ,0x405A ,Normal ,"lds <REG_N>,FPUL" ,1,1,CO,fix_none ,dec_LD(PRM_SREG)}, //lds <REG_N>,FPUL
{0 ,i0100_nnnn_0110_1010 ,Mask_n ,0x406A ,WritesFPSCR ,"lds <REG_N>,FPSCR" ,1,1,CO,fix_none}, //lds <REG_N>,FPSCR
{0 ,i0100_nnnn_0101_1010 ,Mask_n ,0x405A ,UsesFPU ,"lds <REG_N>,FPUL" ,1,1,CO,fix_none ,dec_LD(PRM_SREG)}, //lds <REG_N>,FPUL
{0 ,i0100_nnnn_0110_1010 ,Mask_n ,0x406A ,FWritesFPSCR ,"lds <REG_N>,FPSCR" ,1,1,CO,fix_none}, //lds <REG_N>,FPSCR
{0 ,i0100_nnnn_1111_1010 ,Mask_n ,0x40FA ,Normal ,"ldc <REG_N>,DBR" ,1,1,CO,fix_none ,dec_LD(PRM_SREG)}, //lds <REG_N>,DBR
//ldc : rn
@ -345,37 +345,37 @@ sh4_opcodelistentry opcodes[]=
{0 ,i1100_1111_iiii_iiii ,Mask_imm8 ,0xCF00 ,Normal ,"or.b #<imm8>,@(R0,GBR)" ,4,4,CO,fix_none}, // or.b #<imm>,@(R0,GBR)
//and here are the new ones :D
{0 ,i1111_nnnn_mmmm_0000 ,Mask_n_m ,0xF000,Normal ,"fadd <FREG_M_SD_F>,<FREG_N>" ,1,3,FE,fix_none ,dec_Bin_frNfrM(shop_fadd)}, //fadd <FREG_M>,<FREG_N>
{0 ,i1111_nnnn_mmmm_0001 ,Mask_n_m ,0xF001,Normal ,"fsub <FREG_M_SD_F>,<FREG_N>" ,1,3,FE,fix_none ,dec_Bin_frNfrM(shop_fsub)}, //fsub <FREG_M>,<FREG_N>
{0 ,i1111_nnnn_mmmm_0010 ,Mask_n_m ,0xF002,Normal ,"fmul <FREG_M_SD_F>,<FREG_N>" ,1,3,FE,fix_none ,dec_Bin_frNfrM(shop_fmul)}, //fmul <FREG_M>,<FREG_N>
{0 ,i1111_nnnn_mmmm_0011 ,Mask_n_m ,0xF003,Normal ,"fdiv <FREG_M_SD_F>,<FREG_N>" ,1,12,FE,fix_none ,dec_Bin_frNfrM(shop_fdiv)},//fdiv <FREG_M>,<FREG_N>
{0 ,i1111_nnnn_mmmm_0100 ,Mask_n_m ,0xF004,Normal ,"fcmp/eq <FREG_M>,<FREG_N>" ,1,4,FE,fix_none ,dec_cmp(shop_fseteq,PRM_FRN,PRM_FRM)}, //fcmp/eq <FREG_M>,<FREG_N>
{0 ,i1111_nnnn_mmmm_0101 ,Mask_n_m ,0xF005,Normal ,"fcmp/gt <FREG_M>,<FREG_N>" ,1,4,FE,fix_none ,dec_cmp(shop_fsetgt,PRM_FRN,PRM_FRM)}, //fcmp/gt <FREG_M>,<FREG_N>
{0 ,i1111_nnnn_mmmm_0110 ,Mask_n_m ,0xF006,Normal ,"fmov.s @(R0,<REG_M>),<FREG_N>" ,1,2,LS,fix_none ,dec_MRd(PRM_FRN_SZ,PRM_RM_R0,4)}, //fmov.s @(R0,<REG_M>),<FREG_N>
{0 ,i1111_nnnn_mmmm_0111 ,Mask_n_m ,0xF007,Normal ,"fmov.s <FREG_M>,@(R0,<REG_N>)" ,1,1,LS,fix_none ,dec_MWt(PRM_RN_R0,PRM_FRM_SZ,4)}, //fmov.s <FREG_M>,@(R0,<REG_N>)
{0 ,i1111_nnnn_mmmm_1000 ,Mask_n_m ,0xF008,Normal ,"fmov.s @<REG_M>,<FREG_N>" ,1,2,LS,fix_none ,dec_MRd(PRM_FRN_SZ,PRM_RM,4)}, //fmov.s @<REG_M>,<FREG_N>
{0 ,i1111_nnnn_mmmm_1001 ,Mask_n_m ,0xF009,Normal ,"fmov.s @<REG_M>+,<FREG_N>" ,1,2,LS,fix_none ,dec_MRd(PRM_FRN_SZ,PRM_RM,-4)}, //fmov.s @<REG_M>+,<FREG_N>
{0 ,i1111_nnnn_mmmm_1010 ,Mask_n_m ,0xF00A,Normal ,"fmov.s <FREG_M>,@<REG_N>" ,1,1,LS,fix_none ,dec_MWt(PRM_RN,PRM_FRM_SZ,4)}, //fmov.s <FREG_M>,@<REG_N>
{0 ,i1111_nnnn_mmmm_1011 ,Mask_n_m ,0xF00B,Normal ,"fmov.s <FREG_M>,@-<REG_N>" ,1,1,LS,rn_fpu_4 ,dec_MWt(PRM_RN,PRM_FRM_SZ,-4)}, //fmov.s <FREG_M>,@-<REG_N>
{0 ,i1111_nnnn_mmmm_1100 ,Mask_n_m ,0xF00C,Normal ,"fmov <FREG_M>,<FREG_N>" ,1,0,LS,fix_none ,dec_Fill(DM_UnaryOp,PRM_FRN_SZ,PRM_FRM_SZ,shop_mov32)}, //fmov <FREG_M>,<FREG_N>
{0 ,i1111_nnnn_0101_1101 ,Mask_n ,0xF05D,Normal ,"fabs <FREG_N>" ,1,0,LS,fix_none ,dec_Un_frNfrN(shop_fabs)}, //fabs <FREG_N>
{0 ,i1111_nnn0_1111_1101 ,Mask_nh3bit ,0xF0FD,Normal ,"FSCA FPUL, <DR_N>" ,1,4,FE,fix_none ,dec_Fill(DM_UnaryOp,PRM_FPN,PRM_FPUL,shop_fsca)}, //FSCA FPUL, DRn//F0FD//1111_nnnn_1111_1101
{0 ,i1111_nnnn_1011_1101 ,Mask_n ,0xF0BD,Normal ,"fcnvds <DR_N>,FPUL" ,1,4,FE,fix_none}, //fcnvds <DR_N>,FPUL
{0 ,i1111_nnnn_1010_1101 ,Mask_n ,0xF0AD,Normal ,"fcnvsd FPUL,<DR_N>" ,1,4,FE,fix_none}, //fcnvsd FPUL,<DR_N>
{0 ,i1111_nnmm_1110_1101 ,Mask_n ,0xF0ED,Normal ,"fipr <FV_M>,<FV_N>" ,1,4,FE,fix_none ,dec_Fill(DM_fiprOp,PRM_FVN,PRM_FVM,shop_fipr)}, //fipr <FV_M>,<FV_N>
{0 ,i1111_nnnn_1000_1101 ,Mask_n ,0xF08D,Normal ,"fldi0 <FREG_N>" ,1,0,LS,fix_none ,dec_Fill(DM_UnaryOp,PRM_FRN,PRM_ZERO,shop_mov32)}, //fldi0 <FREG_N>
{0 ,i1111_nnnn_1001_1101 ,Mask_n ,0xF09D,Normal ,"fldi1 <FREG_N>" ,1,0,LS,fix_none ,dec_Fill(DM_UnaryOp,PRM_FRN,PRM_ONE_F32,shop_mov32)}, //fldi1 <FREG_N>
{0 ,i1111_nnnn_0001_1101 ,Mask_n ,0xF01D,Normal ,"flds <FREG_N>,FPUL" ,1,0,LS,fix_none ,dec_Fill(DM_UnaryOp,PRM_FPUL,PRM_FRN,shop_mov32)}, //flds <FREG_N>,FPUL
{0 ,i1111_nnnn_0010_1101 ,Mask_n ,0xF02D,Normal ,"float FPUL,<FREG_N>" ,1,3,FE,fix_none ,dec_Fill(DM_UnaryOp,PRM_FRN,PRM_FPUL,shop_cvt_i2f_n)}, //float FPUL,<FREG_N>
{0 ,i1111_nnnn_0100_1101 ,Mask_n ,0xF04D,Normal ,"fneg <FREG_N> " ,1,0,LS,fix_none ,dec_Un_frNfrN(shop_fneg)}, //fneg <FREG_N>
{dec_i1111_1011_1111_1101 ,i1111_1011_1111_1101 ,Mask_none ,0xFBFD,WritesFPSCR ,"frchg" ,1,2,FE,fix_none}, //frchg
{dec_i1111_0011_1111_1101 ,i1111_0011_1111_1101 ,Mask_none ,0xF3FD,WritesFPSCR ,"fschg" ,1,2,FE,fix_none}, //fschg
{0 ,i1111_nnnn_0110_1101 ,Mask_n ,0xF06D,Normal ,"fsqrt <FREG_N>" ,1,12,FE,fix_none ,dec_Un_frNfrN(shop_fsqrt)},//fsqrt <FREG_N>
{0 ,i1111_nnnn_0011_1101 ,Mask_n ,0xF03D,Normal ,"ftrc <FREG_N>, FPUL" ,1,4,FE,fix_none ,dec_Fill(DM_UnaryOp,PRM_FPUL,PRM_FRN,shop_cvt_f2i_t)}, //ftrc <FREG_N>, FPUL // ,dec_Fill(DM_UnaryOp,PRM_FPUL,PRM_FRN,shop_cvt)
{0 ,i1111_nnnn_0000_1101 ,Mask_n ,0xF00D,Normal ,"fsts FPUL,<FREG_N>" ,1,0,LS,fix_none ,dec_Fill(DM_UnaryOp,PRM_FRN,PRM_FPUL,shop_mov32)}, //fsts FPUL,<FREG_N>
{0 ,i1111_nn01_1111_1101 ,Mask_nh2bit ,0xF1FD,Normal ,"ftrv xmtrx,<FV_N>" ,1,6,FE,fix_none ,dec_Fill(DM_BinaryOp,PRM_FVN,PRM_XMTRX,shop_ftrv,1)}, //ftrv xmtrx,<FV_N>
{0 ,i1111_nnnn_mmmm_1110 ,Mask_n_m ,0xF00E,Normal ,"fmac <FREG_0>,<FREG_M>,<FREG_N>" ,1,4,FE,fix_none ,dec_Fill(DM_BinaryOp,PRM_FRN,PRM_FRM_FR0,shop_fmac,1)}, //fmac <FREG_0>,<FREG_M>,<FREG_N>
{0 ,i1111_nnnn_0111_1101 ,Mask_n ,0xF07D,Normal ,"FSRRA <FREG_N>" ,1,4,FE,fix_none ,dec_Un_frNfrN(shop_fsrra)}, //FSRRA <FREG_N> (1111nnnn 01111101)
{0 ,i1111_nnnn_mmmm_0000 ,Mask_n_m ,0xF000,UsesFPU ,"fadd <FREG_M_SD_F>,<FREG_N>" ,1,3,FE,fix_none ,dec_Bin_frNfrM(shop_fadd)}, //fadd <FREG_M>,<FREG_N>
{0 ,i1111_nnnn_mmmm_0001 ,Mask_n_m ,0xF001,UsesFPU ,"fsub <FREG_M_SD_F>,<FREG_N>" ,1,3,FE,fix_none ,dec_Bin_frNfrM(shop_fsub)}, //fsub <FREG_M>,<FREG_N>
{0 ,i1111_nnnn_mmmm_0010 ,Mask_n_m ,0xF002,UsesFPU ,"fmul <FREG_M_SD_F>,<FREG_N>" ,1,3,FE,fix_none ,dec_Bin_frNfrM(shop_fmul)}, //fmul <FREG_M>,<FREG_N>
{0 ,i1111_nnnn_mmmm_0011 ,Mask_n_m ,0xF003,UsesFPU ,"fdiv <FREG_M_SD_F>,<FREG_N>" ,1,12,FE,fix_none ,dec_Bin_frNfrM(shop_fdiv)},//fdiv <FREG_M>,<FREG_N>
{0 ,i1111_nnnn_mmmm_0100 ,Mask_n_m ,0xF004,UsesFPU ,"fcmp/eq <FREG_M>,<FREG_N>" ,1,4,FE,fix_none ,dec_cmp(shop_fseteq,PRM_FRN,PRM_FRM)}, //fcmp/eq <FREG_M>,<FREG_N>
{0 ,i1111_nnnn_mmmm_0101 ,Mask_n_m ,0xF005,UsesFPU ,"fcmp/gt <FREG_M>,<FREG_N>" ,1,4,FE,fix_none ,dec_cmp(shop_fsetgt,PRM_FRN,PRM_FRM)}, //fcmp/gt <FREG_M>,<FREG_N>
{0 ,i1111_nnnn_mmmm_0110 ,Mask_n_m ,0xF006,UsesFPU ,"fmov.s @(R0,<REG_M>),<FREG_N>" ,1,2,LS,fix_none ,dec_MRd(PRM_FRN_SZ,PRM_RM_R0,4)}, //fmov.s @(R0,<REG_M>),<FREG_N>
{0 ,i1111_nnnn_mmmm_0111 ,Mask_n_m ,0xF007,UsesFPU ,"fmov.s <FREG_M>,@(R0,<REG_N>)" ,1,1,LS,fix_none ,dec_MWt(PRM_RN_R0,PRM_FRM_SZ,4)}, //fmov.s <FREG_M>,@(R0,<REG_N>)
{0 ,i1111_nnnn_mmmm_1000 ,Mask_n_m ,0xF008,UsesFPU ,"fmov.s @<REG_M>,<FREG_N>" ,1,2,LS,fix_none ,dec_MRd(PRM_FRN_SZ,PRM_RM,4)}, //fmov.s @<REG_M>,<FREG_N>
{0 ,i1111_nnnn_mmmm_1001 ,Mask_n_m ,0xF009,UsesFPU ,"fmov.s @<REG_M>+,<FREG_N>" ,1,2,LS,fix_none ,dec_MRd(PRM_FRN_SZ,PRM_RM,-4)}, //fmov.s @<REG_M>+,<FREG_N>
{0 ,i1111_nnnn_mmmm_1010 ,Mask_n_m ,0xF00A,UsesFPU ,"fmov.s <FREG_M>,@<REG_N>" ,1,1,LS,fix_none ,dec_MWt(PRM_RN,PRM_FRM_SZ,4)}, //fmov.s <FREG_M>,@<REG_N>
{0 ,i1111_nnnn_mmmm_1011 ,Mask_n_m ,0xF00B,UsesFPU ,"fmov.s <FREG_M>,@-<REG_N>" ,1,1,LS,rn_fpu_4 ,dec_MWt(PRM_RN,PRM_FRM_SZ,-4)}, //fmov.s <FREG_M>,@-<REG_N>
{0 ,i1111_nnnn_mmmm_1100 ,Mask_n_m ,0xF00C,UsesFPU ,"fmov <FREG_M>,<FREG_N>" ,1,0,LS,fix_none ,dec_Fill(DM_UnaryOp,PRM_FRN_SZ,PRM_FRM_SZ,shop_mov32)}, //fmov <FREG_M>,<FREG_N>
{0 ,i1111_nnnn_0101_1101 ,Mask_n ,0xF05D,UsesFPU ,"fabs <FREG_N>" ,1,0,LS,fix_none ,dec_Un_frNfrN(shop_fabs)}, //fabs <FREG_N>
{0 ,i1111_nnn0_1111_1101 ,Mask_nh3bit ,0xF0FD,UsesFPU ,"FSCA FPUL, <DR_N>" ,1,4,FE,fix_none ,dec_Fill(DM_UnaryOp,PRM_FPN,PRM_FPUL,shop_fsca)}, //FSCA FPUL, DRn//F0FD//1111_nnnn_1111_1101
{0 ,i1111_nnnn_1011_1101 ,Mask_n ,0xF0BD,UsesFPU ,"fcnvds <DR_N>,FPUL" ,1,4,FE,fix_none}, //fcnvds <DR_N>,FPUL
{0 ,i1111_nnnn_1010_1101 ,Mask_n ,0xF0AD,UsesFPU ,"fcnvsd FPUL,<DR_N>" ,1,4,FE,fix_none}, //fcnvsd FPUL,<DR_N>
{0 ,i1111_nnmm_1110_1101 ,Mask_n ,0xF0ED,UsesFPU ,"fipr <FV_M>,<FV_N>" ,1,4,FE,fix_none ,dec_Fill(DM_fiprOp,PRM_FVN,PRM_FVM,shop_fipr)}, //fipr <FV_M>,<FV_N>
{0 ,i1111_nnnn_1000_1101 ,Mask_n ,0xF08D,UsesFPU ,"fldi0 <FREG_N>" ,1,0,LS,fix_none ,dec_Fill(DM_UnaryOp,PRM_FRN,PRM_ZERO,shop_mov32)}, //fldi0 <FREG_N>
{0 ,i1111_nnnn_1001_1101 ,Mask_n ,0xF09D,UsesFPU ,"fldi1 <FREG_N>" ,1,0,LS,fix_none ,dec_Fill(DM_UnaryOp,PRM_FRN,PRM_ONE_F32,shop_mov32)}, //fldi1 <FREG_N>
{0 ,i1111_nnnn_0001_1101 ,Mask_n ,0xF01D,UsesFPU ,"flds <FREG_N>,FPUL" ,1,0,LS,fix_none ,dec_Fill(DM_UnaryOp,PRM_FPUL,PRM_FRN,shop_mov32)}, //flds <FREG_N>,FPUL
{0 ,i1111_nnnn_0010_1101 ,Mask_n ,0xF02D,UsesFPU ,"float FPUL,<FREG_N>" ,1,3,FE,fix_none ,dec_Fill(DM_UnaryOp,PRM_FRN,PRM_FPUL,shop_cvt_i2f_n)}, //float FPUL,<FREG_N>
{0 ,i1111_nnnn_0100_1101 ,Mask_n ,0xF04D,UsesFPU ,"fneg <FREG_N> " ,1,0,LS,fix_none ,dec_Un_frNfrN(shop_fneg)}, //fneg <FREG_N>
{dec_i1111_1011_1111_1101 ,i1111_1011_1111_1101 ,Mask_none ,0xFBFD,FWritesFPSCR ,"frchg" ,1,2,FE,fix_none}, //frchg
{dec_i1111_0011_1111_1101 ,i1111_0011_1111_1101 ,Mask_none ,0xF3FD,FWritesFPSCR ,"fschg" ,1,2,FE,fix_none}, //fschg
{0 ,i1111_nnnn_0110_1101 ,Mask_n ,0xF06D,UsesFPU ,"fsqrt <FREG_N>" ,1,12,FE,fix_none ,dec_Un_frNfrN(shop_fsqrt)},//fsqrt <FREG_N>
{0 ,i1111_nnnn_0011_1101 ,Mask_n ,0xF03D,UsesFPU ,"ftrc <FREG_N>, FPUL" ,1,4,FE,fix_none ,dec_Fill(DM_UnaryOp,PRM_FPUL,PRM_FRN,shop_cvt_f2i_t)}, //ftrc <FREG_N>, FPUL // ,dec_Fill(DM_UnaryOp,PRM_FPUL,PRM_FRN,shop_cvt)
{0 ,i1111_nnnn_0000_1101 ,Mask_n ,0xF00D,UsesFPU ,"fsts FPUL,<FREG_N>" ,1,0,LS,fix_none ,dec_Fill(DM_UnaryOp,PRM_FRN,PRM_FPUL,shop_mov32)}, //fsts FPUL,<FREG_N>
{0 ,i1111_nn01_1111_1101 ,Mask_nh2bit ,0xF1FD,UsesFPU ,"ftrv xmtrx,<FV_N>" ,1,6,FE,fix_none ,dec_Fill(DM_BinaryOp,PRM_FVN,PRM_XMTRX,shop_ftrv,1)}, //ftrv xmtrx,<FV_N>
{0 ,i1111_nnnn_mmmm_1110 ,Mask_n_m ,0xF00E,UsesFPU ,"fmac <FREG_0>,<FREG_M>,<FREG_N>" ,1,4,FE,fix_none ,dec_Fill(DM_BinaryOp,PRM_FRN,PRM_FRM_FR0,shop_fmac,1)}, //fmac <FREG_0>,<FREG_M>,<FREG_N>
{0 ,i1111_nnnn_0111_1101 ,Mask_n ,0xF07D,UsesFPU ,"FSRRA <FREG_N>" ,1,4,FE,fix_none ,dec_Un_frNfrN(shop_fsrra)}, //FSRRA <FREG_N> (1111nnnn 01111101)
//HLE ops
@ -476,6 +476,7 @@ static bool strcmp2(const char* &str1_o,const char * str2)
std::string disassemble_op(const char* tx1, u32 pc, u16 opcode)
{
std::string regs;
std::string text;
char buf[256];
@ -486,10 +487,14 @@ std::string disassemble_op(const char* tx1, u32 pc, u16 opcode)
tx1++;
if (strcmp2(tx1,"REG_N>"))
{
sprintf(buf,"R%d=%x ", GetN(opcode), p_sh4rcb->cntx.r[GetN(opcode)]);
regs += buf;
sprintf(buf,"R%d",GetN(opcode));
}
else if (strcmp2(tx1,"REG_M>") )
{
sprintf(buf,"R%d=%x ", GetM(opcode), p_sh4rcb->cntx.r[GetM(opcode)]);
regs += buf;
sprintf(buf,"R%d",GetM(opcode));
}
else if (strcmp2(tx1,"FREG_N>"))
@ -619,6 +624,6 @@ std::string disassemble_op(const char* tx1, u32 pc, u16 opcode)
}
}
return text;
return text + " ; " + regs;
}

4
core/hw/sh4/sh4_opcode_list.h
View File

@ -75,6 +75,10 @@ struct sh4_opcodelistentry
return (type & WritesFPSCR)!=0;
}
INLINE bool IsFloatingPoint() const
{
return (type & UsesFPU) != 0;
}
};
extern sh4_opcodelistentry* OpDesc[0x10000];