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aica: get rid of old sync dma timing

This commit is contained in:
Flyinghead 2019-09-28 22:34:36 +02:00
parent 3dac86d8f4
commit 84e0f9f118
2 changed files with 5 additions and 14 deletions
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18
core/hw/aica/aica_if.cpp
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@ -222,20 +222,12 @@ void Write_SB_ADST(u32 addr, u32 data)
// idicate that dma is in progress
SB_ADSUSP &= ~0x10;
if (!settings.aica.OldSyncronousDma)
{
// Schedule the end of DMA transfer interrupt
int cycles = len * (SH4_MAIN_CLOCK / 2 / 25000000); // 16 bits @ 25 MHz
if (cycles < 4096)
dma_end_sched(0, 0, 0);
else
sh4_sched_request(dma_sched_id, cycles);
}
else
{
// Schedule the end of DMA transfer interrupt
int cycles = len * (SH4_MAIN_CLOCK / 2 / 25000000); // 16 bits @ 25 MHz
if (cycles < 4096)
dma_end_sched(0, 0, 0);
}
else
sh4_sched_request(dma_sched_id, cycles);
}
}
}

1
core/types.h
View File

@ -488,7 +488,6 @@ struct settings_t
u32 GlobalFocus; //0 -> only hwnd , (1) -> Global
u32 CDDAMute;
bool DSPEnabled;
bool OldSyncronousDma; // 1 -> sync dma (old behavior), 0 -> async dma (fixes some games, partial implementation)
bool NoBatch;
bool NoSound;
} aica;