diff --git a/core/hw/sh4/dyna/ssa.cpp b/core/hw/sh4/dyna/ssa.cpp
index a27bc6fa4..3bf32258e 100644
--- a/core/hw/sh4/dyna/ssa.cpp
+++ b/core/hw/sh4/dyna/ssa.cpp
@@ -59,10 +59,10 @@ bool SSAOptimizer::ExecuteConstOp(shil_opcode* op)
 			rd = rs1;
 			break;
 		case shop_add:
-			rd = rs1 + rs2;
+			rd = shil_opcl_add::f1::impl(rs1, rs2);
 			break;
 		case shop_sub:
-			rd = rs1 - rs2;
+			rd = shil_opcl_sub::f1::impl(rs1, rs2);
 			break;
 		case shop_adc:
 		case shop_sbc:
@@ -86,7 +86,7 @@ bool SSAOptimizer::ExecuteConstOp(shil_opcode* op)
 
 				shil_param op2_rd = shil_param(op->rd2._reg);
 				op2_rd.version[0] = op->rd2.version[0];
-				InsertMov32Op(op2_rd, shil_param(FMT_IMM, (u32)(v >> 32)));
+				InsertMov32Op(op2_rd, shil_param(FMT_IMM, rd2));
 
 				// the previous insert might have invalidated our reference
 				op = &block->oplist[opnum - 1];
@@ -94,17 +94,16 @@ bool SSAOptimizer::ExecuteConstOp(shil_opcode* op)
 			}
 			break;
 		case shop_shl:
-			rd = rs1 << rs2;
+			rd = shil_opcl_shl::f1::impl(rs1, rs2);
 			break;
 		case shop_shr:
-			rd = rs1 >> rs2;
+			rd = shil_opcl_shr::f1::impl(rs1, rs2);
 			break;
 		case shop_sar:
-			rd = (s32) rs1 >> rs2;
+			rd = shil_opcl_sar::f1::impl(rs1, rs2);
 			break;
 		case shop_ror:
-			rd = (rs1 >> rs2)
-					| (rs1 << (32 - rs2));
+			rd = shil_opcl_ror::f1::impl(rs1, rs2);
 			break;
 		case shop_shld:
 			rd = shil_opcl_shld::f1::impl(rs1, rs2);
@@ -113,31 +112,31 @@ bool SSAOptimizer::ExecuteConstOp(shil_opcode* op)
 			rd = shil_opcl_shad::f1::impl(rs1, rs2);
 			break;
 		case shop_or:
-			rd = rs1 | rs2;
+			rd = shil_opcl_or::f1::impl(rs1, rs2);
 			break;
 		case shop_and:
-			rd = rs1 & rs2;
+			rd = shil_opcl_and::f1::impl(rs1, rs2);
 			break;
 		case shop_xor:
-			rd = rs1 ^ rs2;
+			rd = shil_opcl_xor::f1::impl(rs1, rs2);
 			break;
 		case shop_not:
-			rd = ~rs1;
+			rd = shil_opcl_not::f1::impl(rs1);
 			break;
 		case shop_ext_s16:
-			rd = (s32)(s16)rs1;
+			rd = shil_opcl_ext_s16::f1::impl(rs1);
 			break;
 		case shop_ext_s8:
-			rd = (s32)(s8)rs1;
+			rd = shil_opcl_ext_s8::f1::impl(rs1);
 			break;
 		case shop_mul_i32:
-			rd = rs1 * rs2;
+			rd = shil_opcl_mul_i32::f1::impl(rs1, rs2);
 			break;
 		case shop_mul_u16:
-			rd = (u16)(rs1 * rs2);
+			rd = shil_opcl_mul_u16::f1::impl(rs1, rs2);
 			break;
 		case shop_mul_s16:
-			rd = (s16)(rs1 * rs2);
+			rd = shil_opcl_mul_s16::f1::impl(rs1, rs2);
 			break;
 		case shop_mul_u64:
 		case shop_mul_s64:
@@ -160,10 +159,10 @@ bool SSAOptimizer::ExecuteConstOp(shil_opcode* op)
 			}
 			break;
 		case shop_test:
-			rd = (rs1 & rs2) == 0;
+			rd = shil_opcl_test::f1::impl(rs1, rs2);
 			break;
 		case shop_neg:
-			rd = -rs1;
+			rd = shil_opcl_neg::f1::impl(rs1);
 			break;
 		case shop_swaplb:
 			rd = shil_opcl_swaplb::f1::impl(rs1);
@@ -172,32 +171,19 @@ bool SSAOptimizer::ExecuteConstOp(shil_opcode* op)
 			rd = shil_opcl_swap::f1::impl(rs1);
 			break;
 		case shop_seteq:
+			rd = shil_opcl_seteq::f1::impl(rs1, rs2);
+			break;
 		case shop_setgt:
+			rd = shil_opcl_setgt::f1::impl(rs1, rs2);
+			break;
 		case shop_setge:
+			rd = shil_opcl_setge::f1::impl(rs1, rs2);
+			break;
 		case shop_setab:
+			rd = shil_opcl_setab::f1::impl(rs1, rs2);
+			break;
 		case shop_setae:
-			{
-				switch (op->op)
-				{
-				case shop_seteq:
-					rd = rs1 == rs2;
-					break;
-				case shop_setge:
-					rd = (s32)rs1 >= (s32)rs2;
-					break;
-				case shop_setgt:
-					rd = (s32)rs1 > (s32)rs2;
-					break;
-				case shop_setab:
-					rd = rs1 > rs2;
-					break;
-				case shop_setae:
-					rd = rs1 >= rs2;
-					break;
-				default:
-					break;
-				}
-			}
+			rd = shil_opcl_setae::f1::impl(rs1, rs2);
 			break;
 		case shop_setpeq:
 			rd = shil_opcl_setpeq::f1::impl(rs1, rs2);
@@ -273,42 +259,50 @@ bool SSAOptimizer::ExecuteConstOp(shil_opcode* op)
 				return true;
 			}
 		case shop_fneg:
-			rd = rs1 ^ 0x80000000;
+			{
+				f32 frd = shil_opcl_fneg::f1::impl(reinterpret_cast<f32&>(rs1));
+				rd = reinterpret_cast<u32&>(frd);
+			}
 			break;
 		case shop_fadd:
 			{
-				f32 frd = reinterpret_cast<f32&>(rs1) + reinterpret_cast<f32&>(rs2);
+				f32 frd = shil_opcl_fadd::f1::impl(reinterpret_cast<f32&>(rs1), reinterpret_cast<f32&>(rs2));
 				rd = reinterpret_cast<u32&>(frd);
 			}
 			break;
 		case shop_fsub:
 			{
-				f32 frd = reinterpret_cast<f32&>(rs1) - reinterpret_cast<f32&>(rs2);
+				f32 frd = shil_opcl_fsub::f1::impl(reinterpret_cast<f32&>(rs1), reinterpret_cast<f32&>(rs2));
 				rd = reinterpret_cast<u32&>(frd);
 			}
 			break;
 		case shop_fmul:
 			{
-				f32 frd = reinterpret_cast<f32&>(rs1) * reinterpret_cast<f32&>(rs2);
+				f32 frd = shil_opcl_fmul::f1::impl(reinterpret_cast<f32&>(rs1), reinterpret_cast<f32&>(rs2));
 				rd = reinterpret_cast<u32&>(frd);
 			}
 			break;
 		case shop_fdiv:
 			{
-				f32 frd = reinterpret_cast<f32&>(rs1) / reinterpret_cast<f32&>(rs2);
+				f32 frd = shil_opcl_fdiv::f1::impl(reinterpret_cast<f32&>(rs1), reinterpret_cast<f32&>(rs2));
 				rd = reinterpret_cast<u32&>(frd);
 			}
 			break;
 		case shop_cvt_i2f_n:
+			{
+				f32 frd = shil_opcl_cvt_i2f_n::f1::impl(rs1);
+				rd = reinterpret_cast<u32&>(frd);
+			}
+			break;
 		case shop_cvt_i2f_z:
 			{
-				f32 frd = (float)(s32) rs1;
+				f32 frd = shil_opcl_cvt_i2f_z::f1::impl(rs1);
 				rd = reinterpret_cast<u32&>(frd);
 			}
 			break;
 		case shop_fsqrt:
 			{
-				f32 frd = sqrtf(reinterpret_cast<f32&>(rs1));
+				f32 frd = shil_opcl_fsqrt::f1::impl(reinterpret_cast<f32&>(rs1));
 				rd = reinterpret_cast<u32&>(frd);
 			}
 			break;