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dsp: fix output shift 

fix wrungp ear rape
This commit is contained in:
Flyinghead 2020-04-17 18:04:58 +02:00
parent c364d6379b
commit 7058ffeb61
3 changed files with 7 additions and 7 deletions
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6
core/hw/aica/dsp_arm64.cpp
View File

@ -204,7 +204,7 @@ public:
Asr(Y, Y_REG, 11);
else if (op.YSEL == 3)
//Y = (Y_REG >> 4) & 0x0FFF;
Sbfx(Y, Y_REG, 4, 12);
Ubfx(Y, Y_REG, 4, 12);
if (op.YRL)
//Y_REG = INPUTS;
@ -324,9 +324,9 @@ public:
if (op.EWT)
{
//DSPData->EFREG[op.EWA] = SHIFTED >> 4;
//DSPData->EFREG[op.EWA] = SHIFTED >> 8;
MemOperand mem_operand = dspdata_operand(DSPData->EFREG, op.EWA);
Asr(w1, SHIFTED, 4);
Asr(w1, SHIFTED, 8);
Str(w1, mem_operand);
}
#if 0

2
core/hw/aica/dsp_interp.cpp
View File

@ -272,7 +272,7 @@ void AICADSP_Step(struct dsp_t *DSP)
if (EWT)
{
u32 EWA = (IPtr[2] >> 8) & 0x0F;
DSPData->EFREG[EWA] = SHIFTED >> 4;
DSPData->EFREG[EWA] = SHIFTED >> 8;
}
}

6
core/hw/aica/dsp_x64.cpp
View File

@ -209,7 +209,7 @@ public:
//Y = (Y_REG >> 4) & 0x0FFF;
mov(Y, Y_REG);
sar(Y, 4);
and_(Y, 0x0fff); // FIXME is this right?
and_(Y, 0x0fff);
}
if (op.YRL)
@ -346,8 +346,8 @@ public:
if (op.EWT)
{
//DSPData->EFREG[op.EWA] = SHIFTED >> 4;
sar(edx, 4); // SHIFTED
//DSPData->EFREG[op.EWA] = SHIFTED >> 8;
sar(edx, 8); // SHIFTED
mov(dword[rbp + dspdata_operand(DSPData->EFREG, op.EWA)], edx);
}
}